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检索条件"任意字段=2024 International Symposium on Computer Architecture and High Performance Computing Workshops"
5225 条 记 录,以下是261-270 订阅
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Awareness of MPI Virtual Process Topologies on the Single-Chip Cloud computer
Awareness of MPI Virtual Process Topologies on the Single-Ch...
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26th IEEE international Parallel and Distributed Processing symposium (IPDPS) / Workshop on high performance Data Intensive computing
作者: Christgau, Steffen Schnor, Bettina Univ Potsdam Inst Comp Sci Potsdam Germany
This paper presents an approach to improve the communication bandwidth between MPI tasks by evaluating the application's communication graph and making optimal use of communication buffers. It was implemented on t... 详细信息
来源: 评论
Energy-Efficient Time Series Analysis Using Transprecision computing  32
Energy-Efficient Time Series Analysis Using Transprecision C...
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32nd IEEE international symposium on computer architecture and high-performance computing (SBAC-PAD) / 11th Workshop on Applications for Multi-Core architectures (WAMCA)
作者: Fernandez, Ivan Quislant, Ricardo Gutierrez, Eladio Plata, Oscar Univ Malaga Dept Comp Architecture Malaga Spain
Time series analysis is a key step in monitoring and predicting events over time in domains such as epidemiology, genomics, medicine, seismology, speech recognition, and economics. Matrix Profile has been recently pro... 详细信息
来源: 评论
Speedup for Multi-Level Parallel computing
Speedup for Multi-Level Parallel Computing
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26th IEEE international Parallel and Distributed Processing symposium (IPDPS) / Workshop on high performance Data Intensive computing
作者: Tang, Shanjiang Lee, Bu-Sung He, Bingsheng Nanyang Technol Univ Sch Comp Engn Singapore 639798 Singapore
This paper studies the speedup for multi-level parallel computing. Two models of parallel speedup are considered, namely, fixed-size speedup and fixed-time speedup. Based on these two models, we start with the speedup... 详细信息
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Java and grande applications
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computing IN SCIENCE & ENGINEERING 2003年 第1期5卷 60-62页
作者: Fox, G
Soon after Java became popular for Internet applications, many other fields began looking at it. While Java's original thrust was client-side applets, today its dominant use is in large enterprise servers running ... 详细信息
来源: 评论
OpenMP Offload Features and Strategies for high performance across architectures and Compilers
OpenMP Offload Features and Strategies for High Performance ...
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37th IEEE international Parallel and Distributed Processing symposium (IPDPS)
作者: Bhattacharjee, Arijit Daley, Christopher S. Jannesari, Ali Iowa State Univ Ames IA 50011 USA LBNL Berkeley CA USA
high performance accelerated computing has dawned in a new era of highly specialized code that depends on the target architecture. All the latest pre-exascale and exascale class supercomputers are accelerated systems.... 详细信息
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high Volume Throughput computing: Identifying and Characterizing Throughput Oriented Workloads in Data Centers
High Volume Throughput Computing: Identifying and Characteri...
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26th IEEE international Parallel and Distributed Processing symposium (IPDPS) / Workshop on high performance Data Intensive computing
作者: Zhan, Jianfeng Zhang, Lixin Sun, Ninghui Wang, Lei Jia, Zhen Luo, Chunjie Chinese Acad Sci Inst Comp Technol State Key Lab Comp Architecture Beijing Peoples R China
For the first time, this paper systematically identifies three categories of throughput oriented workloads in data centers: services, data processing applications, and interactive real-time applications, whose targets... 详细信息
来源: 评论
Object Placement for high Bandwidth Memory Augmented with high Capacity Memory  29
Object Placement for High Bandwidth Memory Augmented with Hi...
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29th international symposium on computer architecture and high performance computing SBAC-PAD
作者: Laghari, Mohammad Unat, Didem Koc Univ Comp Sci & Engn Istanbul Turkey
high bandwidth memory (HBM) is a new emerging technology that aims to improve the performance of bandwidth-limited applications. Even though it provides high bandwidth, it must be augmented with DRAM to meet the memor... 详细信息
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performance Evaluation of Dynamic Cell Allocation Cache using Cycle Accurate Simulator  6
Performance Evaluation of Dynamic Cell Allocation Cache usin...
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6th international symposium on computing and Networking (CANDAR) - Across Practical Development and Theoretical Research
作者: Kitou, Masato Sasaki, Takahiro Ohno, Kazuhiko Mie Univ Grad Sch Engn Tsu Mie Japan Aichi Prefectural Univ Grad Sch Informat Sci & Technol Nagakute Aichi Japan
Multi-core processors are widely used to improve performance of computer systems. To achieve both high performance and low power consumption, we propose Cell allocation cache. It allocates cache spaces called 'Cel... 详细信息
来源: 评论
Designing high performance Heterogeneous Broadcast for Streaming Applications on GPU Clusters  28
Designing High Performance Heterogeneous Broadcast for Strea...
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28th IEEE international symposium on computer architecture and high performance computing (SBAC-PAD)
作者: Chu, C. -H. Hamidouche, K. Subramoni, H. Venkatesh, A. Elton, B. Panda, D. K. Ohio State Univ Dept Comp Sci & Engn Columbus OH 43210 USA Engility Corp Dayton OH USA
high-performance streaming applications are beginning to leverage the compute power offered by graphics processing units (GPUs) and high network throughput offered by high performance interconnects such as InfiniBand ... 详细信息
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Design and Analysis of an APU for Exascale computing  23
Design and Analysis of an APU for Exascale Computing
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23rd IEEE international symposium on high performance computer architecture (HPCA)
作者: Vijayaraghavan, Thiruvengadam Eckert, Yasuko Loh, Gabriel H. Schulte, Michael J. Ignatowski, Mike Beckmann, Bradford M. Brantley, William C. Greathouse, Joseph L. Huang, Wei Karunanithi, Arun Kayiran, Onur Meswani, Mitesh Paul, Indrani Poremba, Matthew Raasch, Steven Reinhardt, Steven K. Sadowski, Greg Sridharan, Vilas Adv Micro Devices Inc AMD Res Sunnyvale CA 94088 USA Univ Wisconsin Dept Elect & Comp Engn Madison WI 53706 USA AMD Res Sunnyvale CA USA
The challenges to push computing to exaflop levels are difficult given desired targets for memory capacity, memory bandwidth, power efficiency, reliability, and cost. This paper presents a vision for an architecture t... 详细信息
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