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检索条件"任意字段=2024 International Symposium on Computer Architecture and High Performance Computing Workshops"

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FHNTT: A flexible Number Theoretic Transform design based on hybrid-radix butterfly 22

FHNTT: A flexible Number Theoretic Transform design based on...

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22nd IEEE international symposium on Parallel and Distributed Processing with Applications, ISPA 2024

作者： Li, Li Li, Rengang Zhao, Yaqian Li, Ruyang Su, Zhiyuan Li, Xuelei Ieit Systems Co. Ltd Jinan China Electronic Information Industry Co. Ltd Beijing China

ISBN: (纸本)9798331509712

Emerging technologies, such as cloud computing and artificial intelligence, significantly arouse concern about data security and privacy. Homomorphic encryption (HE) is a promising invention, which enables computation on encrypted data without decrypting it so as to ensure data security and privacy. Nevertheless, computation within homomorphic encryption involves time-consuming operations, e.g., Number Theoretic Transform (NTT). The tremendous computation overhead is the critical obstacle in deploying HE applications widely. Besides, in order to meet the performance and security requirements of different applications, it is pivotal to design parametric NTT architecture. In this paper, we propose a flexible and parametric NTT accelerating scheme based on hybrid-radix butterfly, named FHNTT. Specifically, we construct high radix butterfly units and divide the computation of them into several stages such that every stage can be performed pipelined. The number of required twiddle factors declines with the increase of radix value. In addition, we adopt address offset strategy to reduce memory consumption. We implement FHNTT on FPGA due to its fine-grained parallel computing capabilities and customized architecture. Empirical results show that FHNTT has an improved performance compared with other NTT architectures and supports a wide range of parameters. Concretely, FHNTT achieves up to 1.99 × to 2.78 × improvement in latency over other FPGA implementations and the memory utilization rate is up to 94%. Moreover, the flexibility makes FHNTT applicable to multiple use cases. © 2024 IEEE.

关键词： FPGA Acceleration Number Theoretic Transform Parallel computing Parametric architecture

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AccelES: Accelerating Top-K SpMV for Embedding Similarity via Low-bit Pruning 31

AccelES: Accelerating Top-K SpMV for Embedding Similarity vi...

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31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Zhai, Jiaqi Shi, Xuanhua Huang, Kaiyi Ye, Chencheng Hu, Weifang He, Bingsheng Jin, Hai Huazhong University of Science and Technology National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Wuhan430074 China National University of Singapore School of Computing 119077 Singapore

ISBN: (纸本)9798331506476

In the realm of recommendation systems, achieving real-time performance in embedding similarity tasks is often hindered by the limitations of traditional Top-K sparse matrix-vector multiplication (SpMV) methods, which suffer from high latency due to inefficient memory access patterns. This paper identifies these critical gaps and introduces AccelES, a novel approach that significantly enhances the efficiency of Top-K SpMV. Our method employs a two-stage calculation scheme: the first stage utilizes a compact, low-bit dataset to quickly identify the most relevant entries, while the second stage performs full-precision calculations solely on this pruned subset, thereby minimizing computational overhead. Furthermore, AccelES incorporates innovative matrix representations, Ultra-CSR and Random-CSR, which optimize memory bandwidth utilization. Experimental results demonstrate that AccelES accelerates performance, surpassing state-of-the-art FPGA, GPU, and CPU solutions by factors of 3.4×, 2.5×, and 153.3×, respectively, under controlled conditions. These advancements not only enhance processing speed but also significantly improve real-time performance in recommendation systems, establishing AccelES as a pivotal contribution to the field of Top-K sparse matrix-vector multiplication. © 2025 IEEE.

关键词： Embeddings

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Proceedings of the 21st ACM international Conference on computing Frontiers 2024 workshops and Special Sessions, CF 2024 Companion

Proceedings of the 21st ACM International Conference on Comp...

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21st ACM international Conference on computing Frontiers, CF 2024

ISBN: (纸本)9798400704925

The proceedings contain 27 papers. The topics discussed include: a general-purpose analog computer to population protocol compiler;compile-time optimization of the energy consumption of numerical computations;effective HPC programming via domain specific abstractions and compilation;high-level synthesis for complex applications: the Bambu approach;relaxed threshold implementations;using a performance model to implement a superscalar CVA6;seeing beyond the order: a LEN5 to sharpen edge microprocessors with dynamic scheduling;integrating SystemC-AMS power modeling with a RISC-V ISS for virtual prototyping of battery-operated embedded devices;a gigabit, DMA-enhanced open-source ethernet controller for mixed-criticality systems;and model theft attack against a tinyML application running on an ultra-low-power open-source SoC.

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DS-GL: Advancing Graph Learning via Harnessing Nature's Power within Scalable Dynamical Systems 51

DS-GL: Advancing Graph Learning via Harnessing Nature's Powe...

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ACM/IEEE 51st Annual international symposium on computer architecture (ISCA)

作者： Song, Ruibing Wu, Chunshu Liu, Chuan Li, Ang Huang, Michael Geng, Tony Tong Univ Rochester Rochester NY 14642 USA Pacific Northwest Natl Lab Richland WA 99352 USA

ISBN: (纸本)9798350326598;9798350326581

With the rapid digitization of the world, an increasing number of real-world applications are turning to non-Euclidean data, modeled as graphs. Due to their intrinsic high complexity and irregularity, learning from graph data demands tremendous computational power. Recently, CMOS-compatible Ising machines, i.e., dynamical systems fabricated with CMOS technologies, have emerged as a new approach that harnesses the inherent power of nature within dynamical systems to efficiently resolve binary optimization problems and have been adopted for traditional graph computation, such as max-cut. However, when performing complex Graph Learning (GL) tasks, Ising machines face significant hurdles: (i) they are binary and thus ill-suited for real-valued problems;(ii) their expensive all-to-all coupling network that guarantees generality for optimization problems poses daunting scalability concerns. To address these challenges, this paper proposes a nature-powered graph learning framework dubbed DS-GL, which is the first effort to transform the process of solving graph learning problems into the natural annealing process within a parameterized dynamical system embodied as a CMOS chip. To tackle the two major hurdles, DS-GL first augments the Ising machine architecture to modify the self-reaction term of its Hamiltonian function from linear to quadratic, effectively serving as an energy regulator. This adjustment maintains the system's original physical interpretation while enabling it to process continuous, real-valued data. Second, to address the scaling issue, DS-GL further upgrades the real-valued dense Ising machine by decomposing it into a mesh-based multi-PE dynamical system that supports efficient distributed spatial-temporal co-annealing across different PEs through sparse interconnects. By exploiting the inherent sparsity and community structures in real-world graphs, DS-GL is able to map complex graph learning tasks onto the scalable dynamical system while maintaining hi

关键词： Dynamical System Graph Learning Nature-Powered computing

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Proceedings - 2023 IEEE 35th international symposium on computer architecture and high performance computing, SBAC-PAD 2023

Proceedings - 2023 IEEE 35th International Symposium on Comp...

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35th IEEE international symposium on computer architecture and high performance computing, SBAC-PAD 2023

ISBN: (纸本)9798350305487

The proceedings contain 23 papers. The topics discussed include: performance modeling and estimation of a configurable output stationary neural network accelerator;NeurOPar, a neural network-driven EDP optimization strategy for parallel workloads;exploiting the potential of flexible processing units;reverse time migration with lossy and lossless wavefield compression;performance tuning for GPU-embedded systems: machine-learning-based and analytical model-driven tuning methodologies;WCSim: a cloud computing simulator with support for bag of tasks workflows;performance modeling of MARE2DEM’s adaptive mesh refinement for makespan estimation;and comparing performance and portability between CUDA and SYCL for protein database search on NVIDIA, AMD, and Intel GPUs.

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CMB: A Configurable Messaging Benchmark to Explore Fine-Grained Communication 24

CMB: A Configurable Messaging Benchmark to Explore Fine-Grai...

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24th IEEE/ACM international symposium on Cluster, Cloud, and Internet computing (CCGrid)

作者： Marts, W. Pepper Kruse, Donald A. Dosanjh, Matthew G. F. Schonbein, Whit Levy, Scott Bridges, Patrick G. Sandia Natl Labs Ctr Comp Res POB 5800 Albuquerque NM 87185 USA Univ New Mexico Dept Comp Sci Albuquerque NM 87131 USA

ISBN: (纸本)9798350395679;9798350395662

Modern communication APIs provide increased ability to specify when, where, and how to send data between processes. One recent innovation is fine-grained communication, where processes are able to send subsets of data as it is ready rather than waiting for the entirety of the data to be completed. Allowing data to be sent when it is ready increases opportunities for overlapping communication and computation. However, with multiple fine-grained, thread-safe interfaces, the task of optimizing an application's peer-to-peer fine-grained communication is complex. In this paper, we present the Configurable Messaging Benchmark (CMB), a tool for evaluating the application impact of fine-grained communication. Using the CMB we perform a case study to measure the impact of different fine-grained implementations on a variety of realistic application profiles. Initial results reveal a large optimization space ranging from potential speedups as high as 52.97% to slowdowns as high as 289.55% relative to bulk-synchronous MPI message passing.

关键词： high-performance computing computer networks fine-grained communication models benchmarks

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Proceedings - 2024 IEEE international symposium on Parallel and Distributed Processing with Applications, ISPA 2024

Proceedings - 2024 IEEE International Symposium on Parallel ...

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22nd IEEE international symposium on Parallel and Distributed Processing with Applications, ISPA 2024

ISBN: (纸本)9798331509712

The proceedings contain 317 papers. The topics discussed include: HSDP: accelerating large-scale model training via efficient sharded data parallelism;multilevel load balancing algorithm for domestic heterogeneous manycore architecture;fast distributed polynomial multiplication algorithm for lattice-based cryptographic decryption in blockchain systems;carbon-aware distributed energy management for data center microgrids based on blockchain;distributed energy management for carbon neutral data centers;MTRP: a high-performance cost-efficient buffering scheme for multi-tenant cloud services;a diffusion-mamba approach with boundary sampling for imbalanced classification;a two-phase encrypted traffic classification scheme in programmable data plane;and a sorted and dynamic graph storage system of the hybrid memory architecture.

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GameStreamSR: Enabling Neural-Augmented Game Streaming on Commodity Mobile Platforms 51

GameStreamSR: Enabling Neural-Augmented Game Streaming on Co...

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ACM/IEEE 51st Annual international symposium on computer architecture (ISCA)

作者： Bhuyan, Sandeepa Ying, Ziyu Kandemir, Mahmut T. Gowda, Mahanth Das, Chita R. Penn State Univ Dept Comp Sci & Engn State Coll PA 16802 USA

ISBN: (纸本)9798350326598;9798350326581

Cloud gaming (also referred to as Game Streaming) is a rapidly emerging application that is changing the way people enjoy video games. However, if the user demands a high-resolution (e.g., 2K or 4K) stream, the game frames require high bandwidth and the stream often suffers from a significant number of frame drops due to network congestion degrading the Quality of Experience (QoE). Recently, the DNN-based Super Resolution (SR) technique has gained prominence as a practical alternative for streaming low-resolution frames and upscaling them at the client for enhanced video quality. However, performing such DNN-based tasks on resource-constrained and battery-operated mobile platforms is very expensive and also fails to meet the real-time requirement (60 frames per second (FPS)). Unlike traditional video streaming, where the frames can be downloaded and buffered, and then upscaled by their playback turn, Game Streaming is real-time and interactive, where the frames are generated on the fly and cannot tolerate high latency/lags for frame upscaling. Thus, state-of-the-art (SOTA) DNN-based SR cannot satisfy the mobile Game Streaming requirements. Towards this, we propose GameStreamSR, a framework for enabling real-time Super Resolution for Game Streaming applications on mobile platforms. We take visual perception nature into consideration and propose to only apply DNN-based SR to the regions with high visual importance and upscale the remaining regions using traditional solutions such as bilinear interpolation. Especially, we leverage the depth data from the game rendering pipeline to intelligently localize the important regions, called regions of importance (RoI), in the rendered game frames. Our evaluation of ten popular games on commodity mobile platforms shows that our proposal can enable realtime (60 FPS) neurally-augmented SR. Our design achieves a 13x frame rate speedup (and approximate to 4x Motion-to-Photon latency improvement) for the reference frames and a 1.6x

关键词： games mobile computing interactive systems real-time systems client/server systems emerging technologies

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Hydra: Scale-out FHE Accelerator architecture for Secure Deep Learning on FPGA 31

Hydra: Scale-out FHE Accelerator Architecture for Secure Dee...

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31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Yang, Yinghao Xu, Xicheng Zhang, Haibin Song, Jie Tang, Xin Lu, Hang Li, Xiaowei Institute of Computing Technology CAS State Key Laboratory of Processors Beijing China University of Chinese Academy of Sciences Beijing China Zhongguancun Laboratory Beijing China

ISBN: (纸本)9798331506476

Deep learning, including Convolutional Neural Network (CNN) and Large Language Model (LLM), under Fully Homomorphic Encryption (FHE) is very computationally intensive because of the burdensome computations like ciphertext convolution and matrix multiplication, non-linear layers, and bootstrapping. Existing FHE accelerators focus on the high throughput computational units, stacking parallelized clusters to maximize ciphertext inference performance. Nevertheless, this design philosophy cannot leverage the substantial parallelism at the application level and is not scalable for further performance enhancement by simply adding additional compute nodes to cope with the ever-increasing model sizes in the future. In this paper, we propose the high-performance FHE acceleration architecture in a 'scale-out' manner for secure deep learning, termed as Hydra. It supports the multi-server scaling and arbitrary computational nodes theoretically, each handling a portion of the deep learning model governed by the central scheduling mechanism on the host server. Hydra exhibits excellent scalability and delivers outstanding performance across a range of compute resource sizes. We highlight the following results: (1) up to 74 × and 160 × speedup over the SOTA single card accelerator Poseidon and FAB;(2) outperforms 8-card FAB-2 by 12 × to 21 × for FHE-based CNNs and LLMs;(3) outperforms SOTA ASIC accelerators, CraterLake and SHARP, by 8.1 × and 2.5 × for LLM OPT-6.7B, and achieves comparable or superior energy efficiency under the same chip technology. © 2025 IEEE.

关键词： Convolutional neural networks

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AIO: Automating I/O Optimization Pipeline for Data-Intensive Applications in HPC 22

AIO: Automating I/O Optimization Pipeline for Data-Intensive...

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22nd IEEE international symposium on Parallel and Distributed Processing with Applications, ISPA 2024

作者： Wang, Wanxin Wu, Huijun Yang, Lihua Liu, Zhangyu Zheng, Bin Changsha University of Science and Technology School of Computer and Communication Engineering China National University of Defense Technology College of Computer Science and Technology China

ISBN: (纸本)9798331509712

high-performance computing (HPC) systems has entered the exascale era, but I/O performance has lagged behind due to storage hardware limitations, creating a "storage wall effect"that hinders HPC systems full potential. Modern HPC storage systems employ a layered storage architecture with local node storage, burst buffers, and global parallel file systems to improve I/O performance. However, application workloads vary, and fast storage layers may not always outperform global parallel file systems, while a static storage software stack configuration may not achieve optimal performance across different applications. Traditional I/O optimization is time-consuming, laborintensive, and prone to human error. To address this issue, this paper proposes AIO, a data-driven I/O optimization method. AIO automatically selects the optimal storage hierarchy and software stack based on the task's I/O patterns, and further enhances performance by identifying and applying the most efficient configuration settings. We evaluated AIO with eight applications in a cluster that features shared burst buffers, local burst buffers, and a global shared file system. The experiments demonstrate that AIO effectively optimizes I/O performance, achieving an overall speedup of 2.74. © 2024 IEEE.

关键词： Buffer storage

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