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检索条件"任意字段=2024 International Symposium on Computer Architecture and High Performance Computing Workshops"

共 5225 条记录，以下是261-270 订阅

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A Small-Scale Testbed for Large-Scale Reliable computing 31

A Small-Scale Testbed for Large-Scale Reliable Computing

引用

31st IEEE international Parallel and Distributed Processing symposium workshops (IPDPS)

作者： John, Jason St. Hacker, Thomas J. Purdue Univ Comp & Informat Technol W Lafayette IN 47907 USA

ISBN: (纸本)9780769561493

high performance computing (HPC) systems frequently suffer errors and failures from hardware components that negatively impact the performance of jobs run on these systems. We analyzed system logs from two HPC systems at Purdue University and created statistical models for memory and hard disk errors. We created a small-scale error injection testbed-using a customized QEMU build, libvirt, and Python-that could be used by HPC application programmers to test and debug their programs in a faulty environment so that programmers can write more robust and resilient programs before deploying them on an actual HPC system.

关键词： Testbeds

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EASIS: An Optimized Information Service for high performance computing Environment 32

EASIS: An Optimized Information Service for High Performance...

引用

32nd IEEE international Parallel and Distributed Processing symposium (IPDPS)

作者： Wu, Can Wang, Xiaoning Xiao, Haili Cao, Rongqiang Zhao, Yining Chi, Xuebin Chinese Acad Sci Univ Chinese Acad Sci Comp Network Informat Ctr Beijing Peoples R China Chinese Acad Sci Comp Network Informat Ctr Beijing Peoples R China

ISBN: (纸本)9781538655559

The high performance computing Environment aggregates the majority of China's supercomputers including Sunway TaihuLight and Milkyway-2, and provides unified and convenient high-performance computing services for users. With the advent of the Big Data Era and the development of high-performance computer manufacturing, there are more and more supercomputers joining in the high performance computing Environment. In the meantime, a single supercomputer provides larger resource scale and supports more number of application tasks, which brings a huge challenge to the information service. This paper proposes an optimized information service called EASIS, which is efficient, available and simple. The experiment results show that EASIS provides efficient information service which can process 1000 pieces of key resource information with no more than 4s and low system load, and it improves information update accuracy and security which gives users better experience.

关键词： high performance computing Environment information service EASIS SCE

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Balancing load of GPU subsystems to accelerate image reconstruction in parallel beam tomography 30

Balancing load of GPU subsystems to accelerate image reconst...

引用

30th international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Chilingaryan, Suren Ametova, Evelina Kopmann, Andreas Mirone, Alessandro Karlsruhe Inst Technol Karlsruhe Germany Katholieke Univ Leuven Leuven Belgium ESRF Grenoble France

ISBN: (纸本)9781538677698

Synchrotron X-ray imaging is a powerful method to investigate internal structures down to the micro-and nanoscopic scale. Fast cameras recording thousands of frames per second allow time-resolved studies with a high temporal resolution. Fast image reconstruction is essential to provide the synchrotron instrumentation with the imaging information required to track and control the process under study. Traditionally Filtered Back Projection algorithm is used for tomographic reconstruction. In this article, we discuss how to implement the algorithm on nowadays GPGPU architectures efficiently. The key is to achieve balanced utilization of available GPU subsystems. We present two highly optimized algorithms to perform back projection on parallel hardware. One is relying on the texture engine to perform reconstruction, while another one utilizes the Core computational units of the GPU. Both methods outperform current state-of-the-art techniques found in the standard reconstructions codes significantly. Finally, we propose a hybrid approach combining both algorithms to better balance load between GPU subsystems. It further boosts the performance by about 30% on NVIDIA Pascal micro-architecture.

关键词： Graphics processing units Image reconstruction Engines computer architecture Open area test sites Tomography

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LibPreemptible: Enabling Fast, Adaptive, and Hardware-Assisted User-Space Scheduling 30

LibPreemptible: Enabling Fast, Adaptive, and Hardware-Assist...

引用

30th IEEE international symposium on high-performance computer architecture (HPCA)

作者： Li, Yueying Lazarev, Nikita Koufaty, David Yin, Tenny Anderson, Andy Zhang, Zhiru Suh, G. Edward Kaffes, Kostis Delimitrou, Christina Cornell Univ Ithaca NY 14853 USA MIT Cambridge MA USA Intel Labs Hillsboro OR USA Columbia Univ New York NY USA

ISBN: (纸本)9798350393132;9798350393149

Modern cloud applications are prone to high tail latencies since their requests typically follow highly-dispersive distributions. Prior work has proposed both OS- and systemlevel solutions to reduce tail latencies for microsecond-scale workloads through better scheduling. Unfortunately, existing approaches like customized dataplane OSes, require significant OS changes, experience scalability limitations, or do not reach the full performance capabilities hardware offers. We propose LibPreemptible, a preemptive user-level threading library that is flexible, lightweight, and scalable. LibPreemptible is based on three key techniques: 1) a fast and lightweight hardware mechanism for delivery of timed interrupts, 2) a general-purpose user-level scheduling interface, and 3) an API for users to express adaptive scheduling policies tailored to the needs of their applications. Compared to the prior state-of-the-art scheduling system Shinjuku, our system achieves significant tail latency and throughput improvements for various workloads without the need to modify the kernel. We also demonstrate the flexibility of LibPreemptible across scheduling policies for real applications experiencing varying load levels and characteristics.

关键词： cloud computing datacenter performance and quality of service scheduling

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A high performance Massively Parallel Approach for Real Time Deformable Body Physics Simulation

A High Performance Massively Parallel Approach for Real Time...

引用

20th international symposium on computer architecture and high performance computing

作者： de Farias, Thiago S. M. C. Almeida, Mozart W. S. Teixeira, Joao Marcelo X. N. Teichrieb, Veronica Kelner, Judith Univ Fed Pernambuco UFPE Comp Sci Ctr CIn Virtual Real & Multimedia Res Grp GRVM BR-50670901 Recife PE Brazil

ISBN: (纸本)9780769534237

Single processor technology has been evolving across last decades, but due to physical limitations of chip manufacturing process, the industry is pursuing alternatives to sustain computational power growth, including the creation of multi-core systems. Parallel computing targets problems that are scalable and possibly distributed, dividing the problem into smaller pieces. This approach may be explored to satisfy real time constraints required by real time physics simulation. This work introduces an optimal solution to implement accurate simulation of deformable bodies in real time. This is accomplished through the use of a meshless simulation technique, known as Point Based Animation, implemented using a parallel framework 'the NVIDIA Compute Unified Device architecture (CUDA). Our implementation showed significative improvements on performance in comparison to the former CPU one: impressive speedups around 20x could be achieved in the simulation of deformable bodies with 575 physical elements (phyxels) and 53,504 surface elements (surfels).

关键词： Deformation

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Log Visualization Tool for Message-Passing Programming in Pilot 31

Log Visualization Tool for Message-Passing Programming in Pi...

引用

31st IEEE international Parallel and Distributed Processing symposium workshops (IPDPS)

作者： Bao, Tianyi Gardner, William B. Univ Guelph Sch Comp Sci Guelph ON Canada

ISBN: (纸本)9780769561493

The Pilot library is aimed at novice high-performance computing (HPC) programmers and has been used for years to teach message-passing programming to undergraduates. While built on top of standard Message Passing Interface (MPI), it offers a compact application programming interface (API) based upon simple abstractions from the process/channel model of Communicating Sequential Processes (CSP), extensive error-checking, and an integrated deadlock detector. This work enhances Pilot with a log visualization facility adapted from MPI Parallel Environment (MPE) and Jumpshot-4. This new feature is a pedagogical tool helping beginners to understand actual run-time message-passing between processes, and a debugging tool for diagnosing logic that impedes parallelism.

关键词： MPI parallel programming message-passing programming high-performance computing log visualization

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GraphPIM: Enabling Instruction-Level PIM Offloading in Graph computing Frameworks 23

GraphPIM: Enabling Instruction-Level PIM Offloading in Graph...

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23rd IEEE international symposium on high performance computer architecture (HPCA)

作者： Nai, Lifeng Hadidi, Ramyad Sim, Jaewoong Kim, Hyojong Kumar, Pranith Kim, Hyesoon Georgia Inst Technol Atlanta GA 30332 USA Intel Labs Portland OR USA

ISBN: (纸本)9781509049851

With the emergence of data science, graph computing has become increasingly important these days. Unfortunately, graph computing typically suffers from poor performance when mapped to modern computing systems because of the overhead of executing atomic operations and inefficient utilization of the memory subsystem. Meanwhile, emerging technologies, such as Hybrid Memory Cube (HMC), enable the processing-in-memory (PIM) functionality with offloading operations at an instruction level. Instruction offloading to the PIM side has considerable potentials to overcome the performance bottleneck of graph computing. Nevertheless, this functionality for graph workloads has not been fully explored, and its applications and shortcomings have not been well identified thus far. In this paper, we present GraphPIM, a full-stack solution for graph computing that achieves higher performance using PIM functionality. We perform an analysis on modern graph workloads to assess the applicability of PIM offloading and present hardware and software mechanisms to efficiently make use of the PIM functionality. Following the real-world HMC 2.0 specification, GraphPIM provides performance benefits for graph applications without any user code modification or ISA changes. In addition, we propose an extension to PIM operations that can further bring performance benefits for more graph applications. The evaluation results show that GraphPIM achieves up to a 2.4x speedup with a 37% reduction in energy consumption.

关键词： processing-in-memory PIM graph computing hybrid memory cube HMC

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Beyond the Fog: Bringing Cross-Platform Code Execution to Constrained IoT Devices 29

Beyond the Fog: Bringing Cross-Platform Code Execution to Co...

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29th international symposium on computer architecture and high performance computing SBAC-PAD

作者： Pisani, Flavia Brunetta, Jeferson Rech do Rosario, Vanderson Martins Borin, Edson Univ Estadual Campinas Inst Comp BR-13083852 Campinas SP Brazil

ISBN: (纸本)9781509012336

Considering the prediction that there will be over 50 billion devices connected to the Internet of Things (IoT) in the near future, the demand for efficient ways to process data streams generated by sensors grows ever larger, highlighting the necessity to re-evaluate current approaches, such as sending all data to the cloud for processing and analysis. In this paper, we explore one of the methods for improving this scenario: bringing the computation closer to data sources. By executing the code on the IoT devices themselves instead of on the network edge or the cloud, solutions can better meet the latency requirements of several applications, avoid problems with slow and intermittent network connections, prevent network congestion, and potentially save energy by reducing communication. To this end, we propose the LMC framework and compare it with Edgent, an open-source project that is under development by the Apache Incubator. By using a DragonBoard 410c to execute a simple filter, an outlier detector, and a program that calculates the FFT, we obtained results that indicate that LMC outperforms Edgent when dynamic translation is disabled for both of them and is more suitable for lightweight quick queries otherwise. More importantly, the LMC also enables us to perform cross-platform code execution on small, cheap devices that do not have enough resources to run Edgent, like the NodeMCU 1.0.

关键词： Sensors Cloud computing Servers performance evaluation Tools Virtual machining Edge computing

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AWEDF: An architecture-Aware Execution and Debugging Workflow for a highly Reliable Chip

AWEDF: An Architecture-Aware Execution and Debugging Workflo...

引用

IEEE 19th international Conference on high performance computing and Communications (HPCC)

作者： Wang, Yuewei Gui, Qirui Wang, Meng Wang, Lizhe Zomaya, Albert Y. China Univ Geosci Sch Comp Sci Wuhan Peoples R China Univ Sydney Sch Informat Technol Sydney NSW Australia Chinese Acad Sci Inst Remote Sensing & Digital Earth Beijing Peoples R China

ISBN: (纸本)9781538659304

As the technology node of the semiconductor chip enters the nano region, which can help very large scale integration (VLSI) circuits achieve better integration of production density which are companied with faster system operation speed, the embedded industry has been significantly boosted up. Despite the embedded industry trend to embrace the nano region technology, research is lacking on combining the architecture of the chip with the specific workflow to enhance the performance. This paper illustrates a system, focusing on a specific chip, that provides an execution and debugging workflow with a visibility interface to allow user access and operate. Since the existing workflow is primarily applied to common system-on-chip (SoC), and for chips requiring high reliability and execution and energy efficiency that make it difficult to execute programs with good performance, a workflow designed for the unique hardware architecture of the chip is proposed to make good use of hardware. Apart from the high performance of the system, the user-friendly condition is taken into consideration to reduce the developing difficulties. When assessing systems, while correctness,execution and energy efficiency are guaranteed, and, due to the design of workflow, users can conveniently operate the chip even for a beginner, while consuming roughly the same time as or even slightly less time than programming directly on the chip.

关键词： Tools Monitoring computer architecture Software Reliability Hardware Industries computer architecture computer hardware Workflow computer chips DNA Microarrays Legal Executions computer software semiconductor die industries hardware architecture Very large scale integration Energy efficiency Debugging

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Direct Spatial Implementation of Sparse Matrix Multipliers for Reservoir computing 28

Direct Spatial Implementation of Sparse Matrix Multipliers f...

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28th Annual IEEE international symposium on high-performance computer architecture (HPCA)

作者： Denton, Matthew Schmit, Herman Google Res Mountain View CA 94043 USA

ISBN: (纸本)9781665420273

Reservoir computing is a nascent sub-field of machine learning which relies on the recurrent multiplication of a very large, sparse, fixed matrix. We argue that direct spatial implementation of these fixed matrices minimizes the work performed in the computation, and allows for significant reduction in latency and power through constant propagation and logic minimization. Bit-serial arithmetic enables massive static matrices to be implemented. We present the structure of our bit-serial matrix multiplier, and evaluate using canonical signed digit representation to further reduce logic utilization. We have implemented these matrices on a large FPGA and provide a cost model that is simple and extensible. These FPGA implementations, on average, reduce latency by 50x up to 86x versus GPU libraries. Comparing against a recent sparse DNN accelerator, we measure a 4.1x to 47x reduction in latency depending on matrix dimension and sparsity.

关键词： Costs Graphics processing units computer architecture Machine learning Reservoirs Throughput Minimization

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