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GreenPipe: a Hadoop Based Workflow System on Energy-efficient Clouds

GreenPipe: a Hadoop Based Workflow System on Energy-efficien...

26th IEEE international Parallel and Distributed Processing symposium (IPDPS) / Workshop on high performance Data Intensive computing

作者： Mao, Yaokuan Wu, Wenjun Zhang, Hui Luo, Liang Beihang Univ State Key Software Dev Environm Lab Beijing Peoples R China

ISBN: (纸本)9780769546766

Cloud computing is increasingly becoming a popular solution to massive data analysis in bioinformatics. In order to enable scientists to harness the computing power provided by Cloud platforms, we designed GreenPipe, a scalable computational workflow system, which runs jobs as MapReduce tasks on virtual Hadoop clusters. This paper introduces a power-aware scheduling algorithm in the workflow engine to optimize workflow execution in terms of running time and energy consumption. Experimental results demonstrate the performance improvement in GreenPipe.

关键词： workflow cloud computing virtual machine schedule

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Java and grande applications

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computing IN SCIENCE & ENGINEERING 2003年第1期5卷 60-62页

作者： Fox, G

Soon after Java became popular for Internet applications, many other fields began looking at it. While Java's original thrust was client-side applets, today its dominant use is in large enterprise servers running business middleware. Its original client-side use is of secondary importance. Java for high-performance computing has been a popular issue and the subject of annual workshops over the last seven years, including the latest event, Java Grande ISCOPE, JGI'02, (http://***/javagrandeIscope/) held in Seattle from 3-5 November 2002. This meeting series joined forces with the international symposium on computing in Object-Oriented Parallel Environments (ISCOPE), aimed primarily at object-oriented methods in science and engineering with an emphasis on the use of C++.

关键词： Java Parallel processing Internet Optimizing compilers Scientific computing Libraries Robustness Web server computer aided instruction Arithmetic

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Controlling Garbage Collection and Request Admission to Improve performance of FaaS Applications 32

Controlling Garbage Collection and Request Admission to Impr...

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32nd IEEE international symposium on computer architecture and high-performance computing (SBAC-PAD) / 11th Workshop on Applications for Multi-Core architectures (WAMCA)

作者： Quaresma, David Fireman, Daniel Pereira, Thiago Emmanuel Univ Fed Campina Grande Campina Grande Paraiba Brazil Fed Inst Alagoas Arapiraca Brazil

ISBN: (纸本)9781728199245

Runtime environments like Java's JRE, .NET's CLR, and Ruby's MRI, are popular choices for cloud-based applications and particularly in the Function as a Service (FaaS) serverless computing context. A critical component of runtime environments of these languages is the garbage collector (GC). The GC frees developers from manual memory management, which could potentially ease development and avoid bugs. The benefits of using the GC come with a negative impact on performance;that impact happens because either the GC needs to pause the runtime execution or competes with the running program for computational resources. In this work, we evaluated the usage of a technique - Garbage Collector Control Interceptor (GCI) that eliminates the negative impact of GC on performance by controlling GC executions and transparently shedding requests while the collections are happening. We executed experiments simulating AWS Lambda's behavior and found that GCI is a viable solution. It benefited the user by improving the response time up to 10:86% at 99.9th percentile and reducing cost by 7:22%, but it also helped the platform provider by improving resource utilization by 14:52%

关键词： serverless faas garbage collector cold start gci cloud computing cloud services

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Deriving a Methodology for Code Deployment on Multi-Core Platforms via Iterative Manual Optimizations

Deriving a Methodology for Code Deployment on Multi-Core Pla...

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26th IEEE international Parallel and Distributed Processing symposium (IPDPS) / Workshop on high performance Data Intensive computing

作者： McCool, Stuart Milligan, Peter Sage, Paul Queens Univ Belfast Sch Elect Elect Engn & Comp Sci Belfast Antrim North Ireland

ISBN: (纸本)9780769546766

In recent years, there has been what can only be described as an explosion in the types of processing devices one can expect to find within a given computer system. These include the multi-core CPU, the General Purpose Graphics Processing Unit (GPGPU) and the Accelerated Processing Unit (APU), to name but a few. The widespread uptake of these systems presents would-be users with at least two problems. Firstly, each device exposes a complex underlying architecture which must be appreciated in order to attain optimal performance. This is coupled with the fact that a single system can support an arbitrary number of such devices. Consequently, fully leveraging the performance capabilities of such a system must come at a cost - increasingly prolonged development times. Adhering to a methodology will have the significant industrial impact of reducing these development times. This paper describes the continued formulation of such a novel methodology. Two real world scientific programs are optimized for execution on the CUDA platform. Double precision accuracy and optimized speedups (which include PCI-E transfer times) of 15x and 17x are achieved.

关键词： heterogeneous computing GPGPU methodology toolset artificial intelligence characterization Racah Slater

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Speedup for Multi-Level Parallel computing

Speedup for Multi-Level Parallel Computing

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26th IEEE international Parallel and Distributed Processing symposium (IPDPS) / Workshop on high performance Data Intensive computing

作者： Tang, Shanjiang Lee, Bu-Sung He, Bingsheng Nanyang Technol Univ Sch Comp Engn Singapore 639798 Singapore

ISBN: (纸本)9780769546766

This paper studies the speedup for multi-level parallel computing. Two models of parallel speedup are considered, namely, fixed-size speedup and fixed-time speedup. Based on these two models, we start with the speedup formulation that takes into account uneven allocation and communication latency, and gives an accurate estimation. Next, we propose a high-level abstract case with providing a global view of possible performance enhancement, namely E-Amdahl's Law for fixed-size speedup and E-Gustafson's Law for fixed-time speedup. These two laws demonstrate seemingly opposing views about the speedup of multi-level parallel computing. Our study illustrates that they are not contradictory but unified and complementary. The results lead to a better understanding in the performance and scalability of multi-level parallel computing. The experimental results show that E-Amdahl's Law can be applied as a prediction model as well as a guide for the performance optimization in multi-level parallel computing.

关键词： E-Amdahl's Law E-Gustafson's Law Multi-Level Parallel computing

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Many SVDs on GPU for Image Mosaic Assemble 27

Many SVDs on GPU for Image Mosaic Assemble

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IEEE 27th international symposium on computer architecture and high performance computing

作者： Badolato, Irving de Paula, Luciano Farias, Ricardo Univ Fed Rio de Janeiro COPPE Syst Engn Ctr Technol Bldg HRoom 319 BR-21945970 Rio De Janeiro RJ Brazil

ISBN: (纸本)9781467386210

In this paper we present a homography algorithm to produce image mosaics using parallelism to solve a multiple Singular Value Decomposition (SVD) system. We analyse four state of art SVD methods and choose the one which better suites the expected size of the matrices derived from the datasets of interest. Then we use cuda to accelerate the solution of the transformation homogeneous matrices.

关键词： Homography GPU computing SVD solver

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Ascend: a Scalable and Unified architecture for Ubiquitous Deep Neural Network computing 27

Ascend: a Scalable and Unified Architecture for Ubiquitous D...

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27th IEEE international symposium on high-performance computer architecture (HPCA)

作者： Liao, Heng Tu, Jiajin Xia, Jing Liu, Hu Zhou, Xiping Yuan, Honghui Hu, Yuxing Huawei Shenzhen Peoples R China

ISBN: (纸本)9781665422352

Deep neural networks (DNNs) have been successfully applied to a great variety of applications, ranging from small IoT devices to large scale services in a data center. In order to improve the efficiency of processing these DNN models, dedicated hardware accelerators are required for all these scenarios. Theoretically, there exists an optimized acceleration architecture for each application. However, considering the cost of chip design and corresponding tool-chain development, researchers need to trade off between efficiency and generality. In this work, we demonstrate that it is practical to use a unified architecture, called Ascend, to support those applications, ranging from IoT devices to data-center services. We provide a lot of design details to explain that the success of Ascend relies on contributions from different levels. First, heterogeneous computing units are employed to support various DNN models. And the datapath is adapted according to the requirement of computing and data access. Second, when scaling the Ascend architecture from a single core to a cluster containing thousands of cores, it involves design efforts, such as memory hierarchy and system level integration. Third, a multi-tier compiler, which provides flexible choices for developers, is the last critical piece. Experimental results show that using accelerators based on the Ascend architecture can achieve comparable or even better performance in different applications. In addition, various chips based on the Ascend architecture have been successfully commercialized. More than 100 million chips have been used in real products.

关键词： n/a

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HPC Data Storage at a Glance: The Santos Dumont Experience 33

HPC Data Storage at a Glance: The Santos Dumont Experience

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33rd IEEE international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Carneiro, Andre Ramos Bez, Jean Luca Osthoff, Carla Schnorr, Lucas Mello Navaux, Philippe O. A. Fed Univ Rio Grande do Sul UFRGS Inst Informat Porto Alegre RS Brazil Natl Lab Sci Comp LNCC Petropolis RJ Brazil

ISBN: (纸本)9781665443012

high-performance computing (HPC) platforms are used to solve the most diverse scientific problems in research areas, such as biology, chemistry, physics, and health sciences. Researchers use a multitude of scientific software, which have different requirements. These requirements include input and output operations, which directly impact performance due to the existing difference in processing and data access speeds. Thus, supercomputers must efficiently handle a mixed workload scenario when storing data from the applications. Knowledge of the application set and its performance running in a supercomputer is needed to understand the storage system's usage, pinpoint possible bottlenecks, and guide optimization techniques. This research proposes a methodology and visualization tool to evaluate a supercomputer's data storage infrastructure's performance, taking into account the diverse workload and demands of the system over a long period of operation. As a study case, we focus on the Santos Dumont supercomputer, where we were able to identify inefficient usage and problematic factors of performance.

关键词： Lustre Parallel File System high-performance Storage I/O Workload I/O Characterization Visualization

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Phase-Based Data Placement Scheme for Heterogeneous Memory Systems 30

Phase-Based Data Placement Scheme for Heterogeneous Memory S...

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30th international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Laghari, Mohammad Ahmad, Najeeb Unat, Didem Koc Univ Comp Sci & Engn Istanbul Turkey

ISBN: (纸本)9781538677698

Heterogeneous memory systems are equipped with two or more types of memories, which work in tandem to complement the capabilities of each other. The multiple memories can vary in latency, bandwidth and capacity characteristics across systems and they come in various configurations that can be managed by the programmer. This introduces an added programming complexity for the programmer. In this paper, we present a dynamic phase-based data placement scheme to assist the programmer in making decisions about program object allocations. We devise a cost model to assess the benefit of having an object in one type of memory over the other and apply the cost model at every application phase to capture the dynamic behaviour of an application. Our cost model takes into account the reference counts of objects and incurred transfer overhead when making a suggestion. In addition, objects can be transferred across memories asynchronously between phases to mask some of the transfer overhead. We test our cost model with a diverse set of applications from NAS Parallel and Rodinia benchmarks and perform experiments on Intel KNL, which is equipped with a high bandwidth memory (MCDRAM) and a high capacity memory (DDR). Our dynamic phase-based data placement performs better than initial placement and achieves comparable or better performance than cache mode of MCDRAM.

关键词： high bandwidth memory object placement MCDRAM DRAM KNL

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Exploring Power Budget Scheduling Opportunities and Tradeoffs for AMR-based Applications 30

Exploring Power Budget Scheduling Opportunities and Tradeoff...

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30th international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Qin, Yubo Rodero, Ivan Subedi, Pradeep Parashar, Manish Rigo, Sandro Rutgers State Univ Rutgers Discovery Informat Inst RDI2 Piscataway NJ 08854 USA Univ Estadual Campinas Campinas SP Brazil

ISBN: (纸本)9781538677698

Computational demand has brought major changes to Advanced Cyber-Infrastructure (ACI) architectures. It is now possible to run scientific simulations faster and obtain more accurate results. However, power and energy have become critical concerns. Also, the current roadmap toward the new generation of ACI includes power budget as one of the main constraints. Current research efforts have studied power and performance tradeoffs and how to balance these (e.g., using Dynamic Voltage and Frequency Scaling (DVFS) and power capping for meeting power constraints, which can impact performance). However, applications may not tolerate degradation in performance, and other tradeoffs need to be explored to meet power budgets (e.g., involving the application in making energy-performance-quality tradeoff decisions). This paper proposes using the properties of AMR-based algorithms (e.g., dynamically adjusting the resolution of a simulation in combination with power capping techniques) to schedule or re-distribute the power budget. It specifically explores the opportunities to realize such an approach using checkpointing as a proof-of-concept use case and provides a characterization of a representative set of applications that use Adaptive Mesh Refinement (AMR) methods, including a Low-Mach-Number Combustion (LMC) application. It also explores the potential of utilizing power capping to understand power-quality tradeoffs via simulation.

关键词： Power demand Task analysis Degradation Power system management Power measurement Two dimensional displays computer architecture

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