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检索条件"任意字段=2024 International Symposium on Computer Architecture and High Performance Computing Workshops"

共 5226 条记录，以下是301-310 订阅

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AI4Sys 2024 - Proceedings of the 2024 Workshop on AI For Systems, Part of: HPDC 2024 - 33rd international symposium on high-performance Parallel and Distributed computing

AI4Sys 2024 - Proceedings of the 2024 Workshop on AI For Sys...

引用

2024 Workshop on AI For Systems, AI4Sys 2024

The proceedings contain 3 papers. The topics discussed include: ECO-LLM: LLM-based edge cloud optimization;toward using representation learning for cloud resource usage forecasting;and MPIrigen: MPI code generation th...

ISBN: (纸本)9798400706523

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performance Portability of Electron Repulsion Integrals and Their Related Methods across Peta to Exascale architectures

Performance Portability of Electron Repulsion Integrals and ...

引用

2024 workshops of the international Conference for high performance computing, Networking, Storage and Analysis, SC workshops 2024

作者： Sattasathuchana, Tosaporn Xu, Peng Oryspayev, Dossay Bertoni, Colleen Roskop, Luke B. Gordon, Mark S. University of Hawai'i at Manoa Department of Chemistry HonoluluHI United States Iowa State University Ames National Laboratory Department of Chemistry AmesIA United States Stony Brook University Institute for Advanced Computational Science Stony BrookNY United States Argonne National Laboratory Leadership Computing Facility LemontIL United States Hewlett Packard Enterprise HPC Systems Software BloomingtonMN United States

ISBN: (纸本)9798350355543

Entering the exascale era, graphical processing units (GPUs) have been developed by various vendors for large-scale HPC machines. Nine of the top 10 computers on the Top500 List have heterogeneous architectures containing GPUs as accelerators. To take advantage of these computational resources, it is essential to maintain a balance between performance and portability, i.e., making the codes functional, performant, and portable across GPU vendors. In this work, the efforts of restructuring and porting several key CPU kernels in the GAMESS quantum chemistry software package to AMD, Intel, and NVIDIA GPUs via an OpenMP API will be discussed. The use of the OpenMP directive model allows one to successfully run the same code across many GPUs of different vendors. However, since OpenMP is a high-level programming model, it relies on vendor implementations to handle the GPU code generation, and since implementations vary, there are large differences in performance even on the same hardware with different vendor compilers. Presented here are challenges faced during porting CPU code to GPU code with OpenMP, which other porting efforts may also face, such as memory limitations, major restructuring needed for code with branching, and differences in compiler optimizations and tuning. The strategies and approaches to address these challenges are discussed. In this work, the performance results across the supercomputing systems, Summit, Aurora, Frontier, and Perlmutter with a variety of vendor software stacks are presented. © 2024 IEEE.

关键词： Aurora CPHF Frontier Hartree Fock Perlmutter Summit TDHF

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GPU-Accelerated Tree-Search in Chapel versus CUDA and HIP

GPU-Accelerated Tree-Search in Chapel versus CUDA and HIP

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1st international Conference on Smart Energy Systems and Artificial Intelligence (SESAI)

作者： Helbecque, Guillaume Krishnasamy, Ezhilmathi Melab, Nouredine Bouvry, Pascal Univ Luxembourg DCS FSTM SnT Luxembourg Luxembourg Univ Lille CNRS CRIStAL UMR 9189 Ctr Inria Lille France

ISBN: (纸本)9798350364613;9798350364606

In the context of exascale programming, the PGAS-based Chapel is among the rare languages targeting the holistic handling of high-performance computing issues including the productivity-aware harnessing of Nvidia and AMD GPUs. In this paper, we propose a pioneering proof-of-concept dealing with this latter issue in the context of tree-based exact optimization. Actually, we revisit the design and implementation of a generic multi-pool GPU-accelerated tree-search algorithm using Chapel. This algorithm is instantiated on the backtracking method and experimented on the N-Queens problem. For performance evaluation, the Chapel-based approach is compared to Nvidia CUDA and AMD HIP low-level counterparts. The reported results show that in a single-GPU setting, the high GPU abstraction of Chapel results in a loss of only 8% (resp. 16%) compared to CUDA (resp. HIP). In a multi-GPU setting, up to 80% (resp. 71%) of the baseline speed-up is achieved for coarse-grained problem instances on Nvidia (resp. AMD) GPUs.

关键词： Chapel Tree-Search GPU computing CUDA HIP N-Queens AMD Nvidia

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SEATED 2024 - Proceedings of the 2024 Workshop on Serverless at the Edge, Part of: HPDC 2024 - 33rd international symposium on high-performance Parallel and Distributed computing

SEATED 2024 - Proceedings of the 2024 Workshop on Serverless...

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1st Workshop on Serverless at the Edge, SEATED 2024

ISBN: (纸本)9798400706479

The proceedings contain 3 papers. The topics discussed include: analysis and evaluation of load management strategies in a decentralized FaaS environment: a simulation-based framework;live migration of multi-container Kubernetes pods in multi-cluster serverless edge systems;and comparing actor-critic and neuroevolution approaches for traffic offloading in FaaS-powered edge systems.

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HAL: Hardware-assisted Load Balancing for Energy-efficient SNIC-Host Cooperative computing 51

HAL: Hardware-assisted Load Balancing for Energy-efficient S...

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ACM/IEEE 51st Annual international symposium on computer architecture (ISCA)

作者： Huang, Jinghan Lou, Jiaqi Vanavasam, Srikar Kong, Xinhao Ji, Houxiang Jeong, Ipoom Zhuo, Danyang Lee, Eun Kyung Kim, Nam Sung Univ Illinois Urbana IL 61801 USA Duke Univ Durham NC USA IBM Res Yorktown Hts NY USA

ISBN: (纸本)9798350326598;9798350326581

A typical SmartNIC (SNIC) integrates a processor comprising Arm CPU and accelerators with a conventional NIC. The processor is designed to energy-efficiently execute network functions frequently used by datacenter applications. With such a processor, the SNIC has promised to notably improve the system-wide energy efficiency of datacenter servers. Nevertheless, the latest trend of integrating accelerators into server CPUs for these functions sparks a question on the SNIC processor's superiority over a host processor (i.e., server CPU with accelerators) in system-wide energy efficiency, especially under given tail latency constraints. Answering this question, we first take an Intel Xeon processor, integrated with various accelerators (e.g., QuickAssist Technology), as a host processor, and then compare it to an NVIDIA BlueField-2 SNIC processor. This uncovers that (1) the host accelerator, coupled with a more powerful memory subsystem, can outperform the SNIC accelerator, and (2) the SNIC processor can improve system-wide energy efficiency only at low packet rates for most functions under tail latency constraints. To provide high system-wide energy efficiency without compromising tail latency at any packet rates, we propose HAL, consisting of a hardware-based load balancer and an intelligent load balancing policy implemented inside the SNIC. When HAL determines that the SNIC processor cannot efficiently process a given function beyond a specific packet rate, it limits the rate of packets to the SNIC processor and lets the host processor handle the excess. We implement a HAL-enabled SNIC with a commodity FPGA and a BlueField-2 SNIC, plug it into a commodity server, and run 10 popular network functions. Our evaluation shows that HAL can improve the system-wide energy efficiency and throughput of the server running these functions by 31% and 10%, respectively, without notably increasing the tail latency.

关键词： Energy efficiency

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Auto-Generating Diverse Heterogeneous Designs

Auto-Generating Diverse Heterogeneous Designs

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1st international Conference on Smart Energy Systems and Artificial Intelligence (SESAI)

作者： Vandebon, Jessica Coutinho, Jose G. F. Luk, Wayne Imperial Coll London Dept Comp London England

ISBN: (纸本)9798350364613;9798350364606

This paper presents a novel architecture for endto -end design automation, facilitating high-level design portability across diverse technologies. We introduce programmatic, customizable and reusable design-flows capable of generating multiple implementations (e.g., CPU, GPU, FPGA) from a single technology-agnostic high-level application source. Notably, our approach incorporates design-flow branch points and automated path selection strategies, mitigating the manual effort currently needed for efficient design production, particularly for heterogeneous platforms. To validate our approach, we implement optimizing design-flows tailored to different hardware platforms. Through experiments on five AI and HPC benchmarks, we demonstrate significant speed improvements compared to single threaded CPU execution. Our approach generates multi-thread CPU, CPU+FPGA, and CPU+GPU designs from a single highlevel source description, achieving speedups of up to 30 times for OpenMP multi-thread CPU, 32 times for oneAPI CPU+FPGA, and 779 times for HIP CPU+GPU designs. We also showcase cost-effective implementations targeting heterogeneous computing platforms. Additionally, these performance advancements are accompanied by gains in developer productivity, quantified based on added lines of code.

关键词： customizable design-flows high-level design portability across diverse technologies

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FAAST: An Efficient Serverless Framework Made Snapshot-based Function Response Fast 24

FAAST: An Efficient Serverless Framework Made Snapshot-based...

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33rd international symposium on high-performance Parallel and Distributed computing (HPDC)

作者： Bai, Yongshu Yang, Zhihui Gao, Fen Zhejiang Lab Hangzhou Zhejiang Peoples R China Zhejiang Univ Hangzhou High Tech Zone Binjiang Inst Blockchain & Data Secur Hangzhou Zhejiang Peoples R China

ISBN: (纸本)9798400704130

Recent years have seen the rapid popularity of serverless computing, benefiting from its seamless scalability and pay-as-you-go charging model. Despite recent efforts to enhance function cold-start performance by utilizing snapshot and working set mechanisms, the existing methods still suffered considerable overheads in end-to-end response time as functions' inputs varied. In this paper, we propose FAAST, a novel solution designed to improve function response time by enhancing virtual machine snapshot-based startup while guaranteeing function execution performance. Our system introduces a preparation phase to generate a lightweight working set, which excludes stale pages that do not require loading from snapshot files for each function to expedite startup. Additionally, FAAST facilitates network connectivity for the snapshot by implementing NAT within the virtio-net device model bypassing the time-consuming network namespace setup. To guarantee execution performance, a divergent page fault handling mechanism is designed to address page faults related to stale and non-stale pages separately, effectively mitigating sluggish disk I/O accesses. FAAST also incrementally adapts the working set file across various function invocations to bolster functions' resilience to diverse inputs. Extensive experiments demonstrate that FAAST reduces function end-to-end time by up to 63% compared to the state-of-the-art.

关键词： cloud computing serverless computing virtualization snapshot working set

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A Near-Sensor Image Processing Accelerator for Low-end FPGA Design 32

A Near-Sensor Image Processing Accelerator for Low-end FPGA ...

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32nd IEEE Annual international symposium on Field-Programmable Custom computing Machines, FCCM 2024

作者： Mbua, Peter Wang, Zhaoqi Panoff, Maximillian Bobda, Christophe Electrical and Computer Engineering University of Florida Gainesville United States

ISBN: (纸本)9798350372434

This abstract proposes a lightweight near-sensor image preprocessor for video data. The hardware system design targets low-power devices with constrained power and hardware resources. Our approach is a two-stage hierarchical architecture consisting of saliency-based generators that feed a saliency filter. Preliminary results demonstrated significant energy and hardware optimization compared to previous work in this field. Specifically, the proposed architecture uses 0.24%, 0.60%, and 9% of the total processing elements used by examined related work. Similarly, the total on-chip power usage of 0.686W, which is 34.5 % and 5.3% less for the same baseline. This motivates the integration of our near-sensor logic into a system where a high-level algorithm can benefit from data filtering. © 2024 IEEE.

关键词： Digital storage

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Zebra: Efficient Redundant Array of Zoned Namespace SSDs Enabled by Zone Random Write Area (ZRWA) 31

Zebra: Efficient Redundant Array of Zoned Namespace SSDs Ena...

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31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Jiang, Tianyang Zhang, Guangyan Liao, Xiaojian Zhou, Yuqi Huawei Technologies Co. Ltd. China BNRist Tsinghua University Department of Computer Science and Technology China Beihang University China China University of Geosciences China

ISBN: (纸本)9798331506476

Zoned Namespace (ZNS) SSDs have emerged as a promising solution for eliminating device-level garbage collection and achieving predictable performance through the zone abstraction, which supports append-only writes. However, integrating ZNS SSDs into RAID configurations presents challenges, particularly concerning partial parity updates (PPUs) due to the no-overwrite property of ZNS SSDs. Existing solutions introduce dedicated metadata zones to manage PPUs, but these zones become performance bottlenecks, especially under high PPU *** this paper, we introduce Zebra, a novel architecture for ZNS RAID that leverages the Zone Random Write Area (ZRWA) feature of modern ZNS SSDs. Our key insight is that the SSD's write buffer (or ZRWA) in front of each zone is ideal for PPUs that exhibit a repeated sequential overwrite I/O pattern. By ensuring that the parity chunk fits within the ZRWA window, Zebra enables efficient PPUs within the ZRWA. Combined with a set of techniques, Zebra ensures both high performance and reliability. We evaluate Zebra on both large-zone and small-zone ZNS SSDs, two typical ZNS models. Our experiments with micro and application benchmarks show that Zebra improves the throughput by 1.1×-4.2× compared to RAIZN, a state-of-the-art ZNS RAID system. © 2025 IEEE.

关键词： Zinc Selenide

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A LLM Checkpointing System of the Hybrid Memory architecture 22

A LLM Checkpointing System of the Hybrid Memory Architecture

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22nd IEEE international symposium on Parallel and Distributed Processing with Applications, ISPA 2024

作者： Chen, Gengbin Zhu, Yuan Li, Dingding Tang, Yong South China Normal University School of Computer Science Guangzhou510631 China

ISBN: (纸本)9798331509712

The training process of large language models (LLMs) sometimes may raise an error, often necessitating the usage of checkpointing mechanisms to save training states periodically. However, this can lead to a waste of training time and impact performance due to frequent I/O operations. Intel Optane Data Center Persistent Memory Module (DCPMM) is a novel memory device that combines non-volatility, high bandwidth, and low latency. Intuitively, deploying LLMs on DCPMM could enhance I/O performance, but the DCPMM cannot fully adapt to the current deep learning frameworks and the read/write granularity mismatch of DCPMM needs to be resolved. To this end, we propose PMCKPT, a checkpointing scheme customized for hybrid memory architectures (DRAM-PM). PMCKPT provides a storage engine to mitigate the impact of frequent I/O operations on training. Furthermore, PMCKPT ensures data persistence and consistency through a persistence scheme based on the persistent memory development kit (PMDK). Finally, it also incorporates a checkpointing management strategy to handle historical version checkpointing and optimize storage management. We implement PMCKPT in ChatGLM and the experimental results demonstrate that PMCKPT can effectively reduce training time by about 34% compared to traditional schemes which use SSDs. © 2024 IEEE.

关键词： Memory architecture

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