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检索条件"任意字段=2024 International Symposium on Computer Architecture and High Performance Computing Workshops"

共 5225 条记录，以下是311-320 订阅

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NUMA-Aware Dense Matrix Factorizations and Inversion with Look-Ahead on Multicore Processors 34

NUMA-Aware Dense Matrix Factorizations and Inversion with Lo...

引用

34th IEEE international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Catalan, Sandra Igual, Francisco D. Rodriguez-Sanchez, Rafael Herrero, Jose R. Quintana-Orti, Enrique S. Univ Complutense Madrid Madrid Spain Univ Politecn Cataluna Barcelona Spain

ISBN: (数字)9781665451550

ISBN: (纸本)9781665451550

We address the efficient design and implementation of dense matrix factorizations and inversion (DMFI) on modern multicore processors with several NUMA (non-uniform memory access) nodes. Our approach enhances the DMFI routines with a look-ahead strategy, in order to overcome the "panel factorization bottleneck". In addition, it exploits both hybrid task- and loop-level parallelizations while taking into account the NUMA organization of the memory hierarchy. The experiments on a Huawei Kunpeng-based server, with two sockets and 48 cores per socket, for three representative dense linear algebra operations, expose the necessity of adapting both the codes and their execution environment parameters to improve data access locality. The results of these changes deliver performance across inter- and intra-socket NUMA configurations superior to that of reference implementations from state-of-the-art libraries for this platform.

关键词： Multicore processors NUMA dense linear algebra look-ahead multi-threaded parallelism high performance

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FlexFlow: A Flexible Dataflow Accelerator architecture for Convolutional Neural Networks 23

FlexFlow: A Flexible Dataflow Accelerator Architecture for C...

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23rd IEEE international symposium on high performance computer architecture (HPCA)

作者： Lu, Wenyan Yan, Guihai Li, Jiajun Gong, Shijun Han, Yinhe Li, Xiaowei Chinese Acad Sci Inst Comp Technol State Key Lab Comp Architecture Beijing Peoples R China Univ Chinese Acad Sci Beijing Peoples R China

ISBN: (纸本)9781509049851

Convolutional Neural Networks (CNN) are very computation-intensive. Recently, a lot of CNN accelerators based on the CNN intrinsic parallelism are proposed. However, we observed that there is a big mismatch between the parallel types supported by computing engine and the dominant parallel types of CNN workloads. This mismatch seriously degrades resource utilization of existing accelerators. In this paper, we propose a flexible dataflow architecture (FlexFlow) that can leverage the complementary effects among feature map, neuron, and synapse parallelism to mitigate the mismatch. We evaluated our design with six typical practical workloads, it acquires 2-10x performance speedup and 2.5-10x power efficiency improvement compared with three state-of-the-art accelerator architectures. Meanwhile, FlexFlow is highly scalable with growing computing engine scale.

关键词： Parallel processing Neurons computer architecture Kernel Clocks Pipelines Biological neural networks

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GPU-accelerated high-speed Eye Pupil Tracking System 27

GPU-accelerated High-speed Eye Pupil Tracking System

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IEEE 27th international symposium on computer architecture and high performance computing

作者： Mompean, Juan Aragon, Juan L. Prieto, Pedro Artal, Pablo Univ Murcia Dept Ingn & Tecnol Computadores Murcia Spain Univ Murcia LUiOyN Lab Opt Murcia Spain

ISBN: (纸本)9781467380119

Pupil tracking under infrared illumination is an important tool for many researchers in physiological visual optics and ophthalmology. It is also a relevant topic for gaze tracking which is used in psychological and medical research, marketing, human-computer interaction, virtual reality and other areas. A typical setup can be either a low-cost webcam with some infrared LEDs or glasses with mounted cameras and infrared illumination. In this work, we evaluate and parallelize several pupil tracking algorithms with the aim of estimating the pupil's position and size with high accuracy in order to develop a high-speed pupil tracking system. To achieve high processing speed the original non-parallel algorithms have been parallelized by using CUDA and OpenMP. Graphics cards are designed to process images at very high frequencies and resolutions, and CUDA enables them to be used for general purpose computing. Our experimental results show that pupil tracking can be efficiently performed at high speeds with high-resolution images (up to 530 Hz with images of 1280x1024 pixels) using a state-of-the-art GP-GPU.

关键词： Eye tracking

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An architecture for high performance computing and Data Systems Using Byte-Addressable Persistent Memory 34th

An Architecture for High Performance Computing and Data Syst...

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34th international Conference on high performance computing (ISC high performance)

作者： Jackson, Adrian Weiland, Michele Parsons, Mark Homoelle, Bernhard Univ Edinburgh EPCC Edinburgh Midlothian Scotland SVA Syst Vertrieb Alexander GmbH Paderborn Germany

ISBN: (纸本)9783030343569;9783030343552

Non-volatile and byte-addressable memory technology with performance close to main memory has the potential to revolutionise computing systems in the near future. Such memory technology provides the potential for extremely large memory regions (i.e. >3TB per server), very high performance I/O, and new ways of storing and sharing data for applications and workflows. This paper proposes hardware and system software architectures that have been designed to exploit such memory for high performance computing and high performance Data Analytics systems, along with descriptions of how applications could benefit from such hardware, and initial performance results on a system with Intel Optane DC Persistent Memory.

关键词： Non-volatile memory Persistent memory System architecture Systemware NVRAM B-APM

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Controlling Garbage Collection and Request Admission to Improve performance of FaaS Applications 32

Controlling Garbage Collection and Request Admission to Impr...

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32nd IEEE international symposium on computer architecture and high-performance computing (SBAC-PAD) / 11th Workshop on Applications for Multi-Core architectures (WAMCA)

作者： Quaresma, David Fireman, Daniel Pereira, Thiago Emmanuel Univ Fed Campina Grande Campina Grande Paraiba Brazil Fed Inst Alagoas Arapiraca Brazil

ISBN: (纸本)9781728199245

Runtime environments like Java's JRE, .NET's CLR, and Ruby's MRI, are popular choices for cloud-based applications and particularly in the Function as a Service (FaaS) serverless computing context. A critical component of runtime environments of these languages is the garbage collector (GC). The GC frees developers from manual memory management, which could potentially ease development and avoid bugs. The benefits of using the GC come with a negative impact on performance;that impact happens because either the GC needs to pause the runtime execution or competes with the running program for computational resources. In this work, we evaluated the usage of a technique - Garbage Collector Control Interceptor (GCI) that eliminates the negative impact of GC on performance by controlling GC executions and transparently shedding requests while the collections are happening. We executed experiments simulating AWS Lambda's behavior and found that GCI is a viable solution. It benefited the user by improving the response time up to 10:86% at 99.9th percentile and reducing cost by 7:22%, but it also helped the platform provider by improving resource utilization by 14:52%

关键词： serverless faas garbage collector cold start gci cloud computing cloud services

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GreenPipe: a Hadoop Based Workflow System on Energy-efficient Clouds

GreenPipe: a Hadoop Based Workflow System on Energy-efficien...

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26th IEEE international Parallel and Distributed Processing symposium (IPDPS) / Workshop on high performance Data Intensive computing

作者： Mao, Yaokuan Wu, Wenjun Zhang, Hui Luo, Liang Beihang Univ State Key Software Dev Environm Lab Beijing Peoples R China

ISBN: (纸本)9780769546766

Cloud computing is increasingly becoming a popular solution to massive data analysis in bioinformatics. In order to enable scientists to harness the computing power provided by Cloud platforms, we designed GreenPipe, a scalable computational workflow system, which runs jobs as MapReduce tasks on virtual Hadoop clusters. This paper introduces a power-aware scheduling algorithm in the workflow engine to optimize workflow execution in terms of running time and energy consumption. Experimental results demonstrate the performance improvement in GreenPipe.

关键词： workflow cloud computing virtual machine schedule

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MaPU: A Novel Mathematical computing architecture 22

MaPU: A Novel Mathematical Computing Architecture

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22nd IEEE international symposium on high-performance computer architecture (HPCA)

作者： Wang, Donglin Xie, Shaolin Zhang, Zhiwei Du, Xueliang Wang, Lei Liu, Zijun Lin, Xiao Hao, Jie Yin, Leizu Wang, Tao Yang, Yongyong Lin, Chen Ma, Hong Pu, Zhonghua Ding, Guangxin Sun, Wenqin Zhou, Fabiao Ren, Weili Wang, Huijuan Zhu, Mengchen Yang, Lipeng Xiao, NuoZhou Cui, Qian Wang, Xingang Guo, Ruoshan Wang, Xiaoqin CASIA Beijing Peoples R China Spreadtrum Comm Inc Tianjin Peoples R China Huawei Tech Co Ltd Bengaluru Karnataka India

ISBN: (纸本)9781467392112

As the feature size of the semiconductor process is scaling down to 10nm and below, it is possible to assemble systems with high performance processors that can theoretically provide computational power of up to tens of PLOPS. However, the power consumption of these systems is also rocketing up to tens of millions watts, and the actual performance is only around 60% of the theoretical performance. Today, power efficiency and sustained performance have become the main foci of processor designers. Traditional computing architecture such as superscalar and GPGPU are proven to be power inefficient, and there is a big gap between the actual and peak performance. In this paper, we present the MaPU architecture, a novel architecture which is suitable for data-intensive computing with great power efficiency and sustained computation throughput. To achieve this goal, MaPU attempts to optimize the application from a system perspective, including the hardware, algorithm and corresponding program model. It uses an innovative multi-granularity parallel memory system with intrinsic shuffle ability, cascading pipelines with wide SIMD data paths and a state-machine-based program model. When executing typical signal processing algorithms, a single MaPU core implemented with a 40nm process exhibits a sustained performance of 134 GLOPS while consuming only 2.8 W in power, which increases the actual power efficiency by an order of magnitude comparable with the traditional CPU and GPGPU.

关键词： Program processors

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Phase-Based Data Placement Scheme for Heterogeneous Memory Systems 30

Phase-Based Data Placement Scheme for Heterogeneous Memory S...

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30th international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Laghari, Mohammad Ahmad, Najeeb Unat, Didem Koc Univ Comp Sci & Engn Istanbul Turkey

ISBN: (纸本)9781538677698

Heterogeneous memory systems are equipped with two or more types of memories, which work in tandem to complement the capabilities of each other. The multiple memories can vary in latency, bandwidth and capacity characteristics across systems and they come in various configurations that can be managed by the programmer. This introduces an added programming complexity for the programmer. In this paper, we present a dynamic phase-based data placement scheme to assist the programmer in making decisions about program object allocations. We devise a cost model to assess the benefit of having an object in one type of memory over the other and apply the cost model at every application phase to capture the dynamic behaviour of an application. Our cost model takes into account the reference counts of objects and incurred transfer overhead when making a suggestion. In addition, objects can be transferred across memories asynchronously between phases to mask some of the transfer overhead. We test our cost model with a diverse set of applications from NAS Parallel and Rodinia benchmarks and perform experiments on Intel KNL, which is equipped with a high bandwidth memory (MCDRAM) and a high capacity memory (DDR). Our dynamic phase-based data placement performs better than initial placement and achieves comparable or better performance than cache mode of MCDRAM.

关键词： high bandwidth memory object placement MCDRAM DRAM KNL

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performance Analysis of Scientific Applications on an NVIDIA Grace System

Performance Analysis of Scientific Applications on an NVIDIA...

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2024 workshops of the international Conference for high performance computing, Networking, Storage and Analysis, SC workshops 2024

作者： Ruhela, Amit Cazes, John Mccalpin, John Del-Castillo-Negrete, Carlos Li, Junjie Liu, Hang Chen, Hanning Lu, Chun-Yaung Milfeld, Kent Zhang, Wenyang Wang, Ian Koesterke, Lars Desantis, John Lewis, Nic Hempel, Sean Stanzione, Dan Texas Advanced Computing Center AustinTX United States

ISBN: (纸本)9798350355543

The NSF funded Frontera system has supported many important scientific applications over the last five years, not only in HPC but also in the area of Big Data and Machine Learning. Applications leveraged the petascale computational capabilities of the system to achieve new breakthroughs in science and engineering. Frontera is currently the fastest academic supercomputer in the US and is used by hundreds of scientists and engineers daily, enabling researchers to tackle more significant and complex challenges than ever before. As Frontera is nearing the end of its production life, it will be replaced by a new system, "Horizon". An intermediate system, "Vista", will bridge the gap by enabling researchers to access updated software and hardware technologies before Horizon is available. This paper summarizes early experiences on Vista by reporting on the performance of key applications and presenting its design and architecture. Early results are presented from the CPU architecture of Vista, "Grace-Grace", and compared with other processor technologies at TACC from Intel and AMD. A future paper will discuss the performance of the "Grace-Hopper"component of Vista. © 2024 IEEE.

关键词： Grace-Hopper HPC NVIDIA Petascale

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Exploring Power Budget Scheduling Opportunities and Tradeoffs for AMR-based Applications 30

Exploring Power Budget Scheduling Opportunities and Tradeoff...

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30th international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Qin, Yubo Rodero, Ivan Subedi, Pradeep Parashar, Manish Rigo, Sandro Rutgers State Univ Rutgers Discovery Informat Inst RDI2 Piscataway NJ 08854 USA Univ Estadual Campinas Campinas SP Brazil

ISBN: (纸本)9781538677698

Computational demand has brought major changes to Advanced Cyber-Infrastructure (ACI) architectures. It is now possible to run scientific simulations faster and obtain more accurate results. However, power and energy have become critical concerns. Also, the current roadmap toward the new generation of ACI includes power budget as one of the main constraints. Current research efforts have studied power and performance tradeoffs and how to balance these (e.g., using Dynamic Voltage and Frequency Scaling (DVFS) and power capping for meeting power constraints, which can impact performance). However, applications may not tolerate degradation in performance, and other tradeoffs need to be explored to meet power budgets (e.g., involving the application in making energy-performance-quality tradeoff decisions). This paper proposes using the properties of AMR-based algorithms (e.g., dynamically adjusting the resolution of a simulation in combination with power capping techniques) to schedule or re-distribute the power budget. It specifically explores the opportunities to realize such an approach using checkpointing as a proof-of-concept use case and provides a characterization of a representative set of applications that use Adaptive Mesh Refinement (AMR) methods, including a Low-Mach-Number Combustion (LMC) application. It also explores the potential of utilizing power capping to understand power-quality tradeoffs via simulation.

关键词： Power demand Task analysis Degradation Power system management Power measurement Two dimensional displays computer architecture

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