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检索条件"任意字段=2024 International Symposium on Computer Architecture and High Performance Computing Workshops"

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2024 IEEE international Parallel and Distributed Processing symposium workshops, IPDPSW 2024

2024 IEEE International Parallel and Distributed Processing ...

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2024 IEEE international Parallel and Distributed Processing symposium workshops, IPDPSW 2024

ISBN: (纸本)9798350364606

The proceedings contain 165 papers. The topics discussed include: understanding multi-dimensional efficiency of fine-tuning large language models using SpeedUp, MemoryUp, and EnergyUp;shared-memory parallel Edmonds blossom algorithm for maximum cardinality matching in general graphs;a reconfigurable architecture of a scalable, ultrafast, ultrasound, delay-and-sum beamformer;scheduling and allocation of disaggregated memory resources in HPC systems;GIM (ghost in the machine): a coarse-grained reconfigurable compute-in-memory platform for exploring machine-learning architectures;further optimizations and analysis of smith-waterman with vector extensions;measurement-based quantum approximate optimization;optimizing forward wavefield storage leveraging high-speed storage media;teaching performance metrics in parallel computing courses;and compiler-driven Swar parallelism for high-performance bitboard algorithms.

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Designing high performance Heterogeneous Broadcast for Streaming Applications on GPU Clusters 28

Designing High Performance Heterogeneous Broadcast for Strea...

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28th IEEE international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Chu, C. -H. Hamidouche, K. Subramoni, H. Venkatesh, A. Elton, B. Panda, D. K. Ohio State Univ Dept Comp Sci & Engn Columbus OH 43210 USA Engility Corp Dayton OH USA

ISBN: (纸本)9781509061082

high-performance streaming applications are beginning to leverage the compute power offered by graphics processing units (GPUs) and high network throughput offered by high performance interconnects such as InfiniBand (IB) to boost their performance and scalability. These applications rely heavily on broadcast operations to move data, which is stored in the host memory, from a single source-typically live-to multiple GPU-based computing sites. While homogeneous broadcast designs take advantage of IB hardware multicast feature to boost their performance, their heterogeneous counter-part requires an explicit data movement between Host and GPU, which significantly hurts the overall performance. There is a dearth of efficient heterogeneous broadcast designs for streaming applications especially on emerging multi-GPU configurations. In this work, we propose novel techniques to fully and conjointly take advantage of NVIDIA GPUDirect RDMA ( GDR), CUDA inter-process communication (IPC) and IB hardware multicast features to design high-performance heterogeneous broadcast operations for modern multi-GPU systems. We propose intra-node, topology-aware schemes to maximize the performance benefits while minimizing the utilization of valuable PCIe resources. Further, we optimize the communication pipeline by overlapping the GDR + IB hardware multicast operations with CUDA IPC operations. Compared to existing solutions, our designs show up to 3X improvement in the latency of a heterogeneous broadcast operation. Our designs also show up to 67% improvement in execution time of a streaming benchmark on a GPU-dense Cray CS-Storm system with 88 GPUs.

关键词： Graphics processing unit

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Towards a Transprecision Polymorphic Floating-Point Unit for Mixed-precision computing 31

Towards a Transprecision Polymorphic Floating-Point Unit for...

引用

31st international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Linhares, Alisson Azevedo, Rodolfo Univ Campinas Unicamp Inst Comp Campinas Brazil

ISBN: (纸本)9781728141947

Mixed-precision is a paradigm that tries to combine computations with different levels of precision to compose results. This approach has been used extensively to optimize scientific applications and has shown speed and energy gains, without causing any relevant precision loss. However, to exploit mixed precision opportunities most applications need to be recompiled to use different instructions and types. Thus, in this work, we present a new floating-point unit design, able to automatically decide when an instruction should be executed using less precision, without recompilation or user direct intervention. Our proposal takes advantage of ad-hoc polymorphism to perform computations with different data types, dynamically selecting a proper instruction on demand, and can also be configured according to overall precision requirements. Our simulated results show that, for some doubleprecision benchmarks, we are able to execute more than 90% of all floating-point operations in half-precision, without affecting its accuracy and resulting in a precision error below 1%. In addition, this new technology may increase instruction level parallelism and cut down the necessity for type casting operations.

关键词： Transprecision Mixed-Precision Floating-Point Unit RISC-V

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An Optimal Model for Optimizing the Placement and Parallelism of Data Stream Processing Applications on Cloud-Edge computing 32

An Optimal Model for Optimizing the Placement and Parallelis...

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32nd IEEE international symposium on computer architecture and high-performance computing (SBAC-PAD) / 11th Workshop on Applications for Multi-Core architectures (WAMCA)

作者： de Souza, Felipe Rodrigo de Assuncao, Marcos Dias Caron, Eddy Veith, Alexandre da Silva Univ Lyon EnsL INRIA UCBLCNRSLIP Lyon 07 France Univ Toronto Toronto ON Canada

ISBN: (纸本)9781728199245

The Internet of Things has enabled many application scenarios where a large number of connected devices generate unbounded streams of data, often processed by data stream processing frameworks deployed in the cloud. Edge computing enables offloading processing from the cloud and placing it close to where the data is generated, thereby reducing the time to process data events and deployment costs. However, edge resources are more computationally constrained than their cloud counterparts, raising two interrelated issues, namely deciding on the parallelism of processing tasks (a.k.a. operators) and their mapping onto available resources. In this work, we formulate the scenario of operator placement and parallelism as an optimal mixed-integer linear programming problem. The proposed model is termed as Cloud-Edge data Stream Placement (CESP). Experimental results using discrete-event simulation demonstrate that CESP can achieve an end-to-end latency at least similar or equal to 80% and monetary costs at least similar or equal to 30% better than traditional cloud deployment.

关键词： Data Stream Processing Operator Placement Operator Parallelism End-to-end Latency Edge computing

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I CAN HAS SUPERcomputer? A Novel Approach to Teaching Parallel and Distributed computing Concepts Using a Meme-Based Programming Language 31

I CAN HAS SUPERCOMPUTER? A Novel Approach to Teaching Parall...

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31st IEEE international Parallel and Distributed Processing symposium workshops (IPDPS)

作者： Richie, David A. Ross, James A. Brown Deer Technol Forest Hill MD 21050 USA US Army Res Lab Aberdeen Proving Ground MD USA

ISBN: (纸本)9780769561493

A novel approach is presented to teach the parallel and distributed computing concepts of synchronization and remote memory access. The single program multiple data (SPMD) partitioned global address space (PGAS) model presented in this paper uses a procedural programming language appealing to undergraduate students. We propose that the amusing nature of the approach may engender creativity and interest using these concepts later in more sober environments. Specifically, we implement parallel extensions to LOLCODE within a source-to-source compiler sufficient for the development of parallel and distributed algorithms normally implemented using conventional high-performance computing languages and APIs.

关键词： component meme-based learning parallel and distributed computing

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Energy-Efficient IaaS-PaaS Co-design for Flexible Cloud Deployment of Scientific Applications 30

Energy-Efficient IaaS-PaaS Co-design for Flexible Cloud Depl...

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30th international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Guyon, David Orgerie, Anne-Cecile Morin, Christine Univ Rennes CNRS INRIA IRISA Rennes France

ISBN: (纸本)9781538677698

Reducing the massive amount of energy consumed by cloud datacenters becomes of major importance. In the usual approach where resources are consolidated into fewer servers in order to power down the others, it still remains periods of time when servers are not fully utilized. Consequently, it exists unused resources that are not exploited although they could be used to execute applications compatible with the variable availability of these resources. In this work, we propose a cloud system where the Platform-as-a-Service (PaaS) and Infrastructure-as-a-Service (IaaS) layers interact to find execution trade-offs that exploit the unused resources at IaaS level. PaaS users are involved in the energy optimization by proposing to delay their executions and adapt resource sizes in order to fit with the available unused resources. Our evaluation by simulation is based on real data and expresses a realistic large scale cloud scenario. Results show that according to the proportion of energy-aware users, this system is able to reduce the amount of servers by using resources that would have been wasted otherwise. Therefore, our solution allows datacenters to consume less energy than with usual resource managers where all applications start their execution at submission time with their initial resource size.

关键词： Cloud computing Infrastructure-as-a-Service Platform-as-a-Service energy

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Microarchitectural comparison and in-core modeling of state-of-the-art CPUs: Grace, Sapphire Rapids, and Genoa

Microarchitectural comparison and in-core modeling of state-...

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2024 workshops of the international Conference for high performance computing, Networking, Storage and Analysis, SC workshops 2024

作者： Laukemann, Jan Hager, Georg Wellein, Gerhard Friedrich-Alexander-Universität Erlangen-Nürnberg Erlangen National High Performance Computing Center Erlangen Germany Erlangen National High Performance Computing Center Erlangen Germany

ISBN: (纸本)9798350355543

With Nvidia's release of the Grace Superchip, all three big semiconductor companies in HPC (AMD, Intel, Nvidia) are currently competing in the race for the best CPU. In this work we analyze the performance of these state-of-the-art CPUs and create an accurate in-core performance model for their microarchitectures Zen 4, Golden Cove, and Neoverse V2, extending the Open Source architecture Code Analyzer (OSACA) tool and comparing it with LLVM-MCA. Starting from the peculiarities and up- and downsides of a single core, we extend our comparison by a variety of microbenchmarks and the capabilities of a full node. The "write-allocate (WA) evasion"feature, which can automatically reduce the memory traffic caused by write misses, receives special attention;we show that the Grace Superchip has a next-to-optimal implementation of WA evasion, and that the only way to avoid write allocates on Zen 4 is the explicit use of non-temporal stores. © 2024 IEEE.

关键词： AMD Genoa Golden Cove in-core Intel Sapphire Rapids Neoverse V2 NVIDIA Grace CPU Superchip performance analysis performance modeling Zen 4

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A 64-bit Stream Processor architecture for Scientific Applications 07

A 64-bit Stream Processor Architecture for Scientific Applic...

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34th Annual international symposium on computer architecture

作者： Yang, Xuejun Yan, Xiaobo Xing, Zuocheng Deng, Yu Jiang, Jiang Zhang, Ying Natl Univ Def Technol Natl Lab Paralleling & Distributed Proc Sch Comp Changsha 410073 Hunan Peoples R China

ISBN: (纸本)9781595937063

Stream architecture is a novel microprocessor architecture with wide application potential. But as for whether it can be used efficiently in scientific computing, many issues await further study. This paper first gives the design and implementation of a 64-bit stream processor, FT64 (Fei Teng 64), for scientific computing. The carrying out of 64-bit extension design and scientific computing oriented optimization are described in such aspects as instruction set architecture, stream controller, micro controller, ALU cluster, memory hierarchy and interconnection interface here. Second, two kinds of communications as message passing and stream communications are put forward. An interconnection based on the communications is designed for FT64-based high performance computers. Third, a novel stream programming language, SF95 (Stream FORTRAN95), and its compiler, SF95Compiler (Stream FORTRAN95 Compiler), are developed to facilitate the development of scientific applications. Finally, nine typical scientific application kernels are tested and the results show the efficiency of stream architecture for scientific computing.

关键词： stream processor architecture program language compiler scientific application high performance computing

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Bosehedral: Compiler Optimization for Bosonic Quantum computing 51

Bosehedral: Compiler Optimization for Bosonic Quantum Comput...

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ACM/IEEE 51st Annual international symposium on computer architecture (ISCA)

作者： Zhou, Junyu Liu, Yuhao Shi, Yunong Javadi-Abhari, Ali Li, Gushu Univ Penn Dept Comp & Informat Sci 200 S 33Rd St Philadelphia PA 19104 USA AWS Quantum Technol New York NY USA IBM Quantum New York NY USA

ISBN: (纸本)9798350326598;9798350326581

Bosonic quantum computing, based on the infinite-dimensional qumodes, has shown promise for various practical applications that are classically hard. However, the lack of compiler optimizations has hindered its full potential. This paper introduces Bosehedral, an efficient compiler optimization framework for (Gaussian) Boson sampling on Bosonic quantum hardware. Bosehedral overcomes the challenge of handling infinite-dimensional qumode gate matrices by performing all its program analysis and optimizations at a higher algorithmic level, using a compact unitary matrix representation. It optimizes qumode gate decomposition and logical-to-physical qumode mapping, and introduces a tunable probabilistic gate dropout method. Overall, Bosehedral significantly improves the performance by accurately approximating the original program with much fewer gates. Our evaluation shows that Bosehedral can largely reduce the program size but still maintain a high approximation fidelity, which can translate to significant end-to-end application performance improvement.

关键词： Bosonic Quantum computing Gaussian Boson Sampling Compiler Optimization

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Metrics for Packing Efficiency and Fairness of HPC Cluster Batch Job Scheduling 34

Metrics for Packing Efficiency and Fairness of HPC Cluster B...

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34th IEEE international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Goponenko, Alexander, V Lamar, Kenneth Peterson, Christina Allan, Benjamin A. Brandt, Jim M. Dechev, Damian Univ Cent Florida Dept Comp Sci 211 Harris CtrBldg 1164000 Cent Florida Blvd Orlando FL 32816 USA Sandia Natl Labs POB 5800MS 0823 Albuquerque NM 87185 USA

ISBN: (数字)9781665451550

ISBN: (纸本)9781665451550

Development of job scheduling algorithms, which directly influence high-performance computing (HPC) clusters performance, is hindered because popular scheduling quality metrics, such as Bounded Slowdown, poorly correlate with global scheduling objectives that include job packing efficiency and fairness. This report proposes Area Weighted Response Time, a metric that offers an unbiased representation of job packing efficiency, and presents a class of new metrics, Priority Weighted Specific Response Time, that assess both packing efficiency and fairness of schedules. The provided examples of simulation of scheduling of real workload traces and analysis of the resulting schedules with the help of these metrics and conventional metrics, demonstrate that although Bounded Slowdown can be readily improved by modifying the standard First Come First Served backfilling algorithm and by using existing techniques of estimating job runtime, these improvements are accompanied by significant degradation of job packing efficiency and fairness. In contrast, improving job packing efficiency and fairness over the standard backfilling algorithm, which is designed to target those objectives, is difficult. It requires further algorithm development and more accurate runtime estimation techniques that reduce frequency of underpredictions.

关键词： high performance computing parallel job scheduling performance metrics schedule quality runtime estimates packing efficiency fairness weighted flow time weighted response time

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