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CORDOBA: Carbon-Efficient Optimization Framework for computing Systems 31

CORDOBA: Carbon-Efficient Optimization Framework for Computi...

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31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Elgamal, Mariam Carmean, Doug Ansari, Elnaz Zed, Okay Peri, Ramesh Manne, Srilatha Gupta, Udit Wei, Gu-Yeon Brooks, David Hills, Gage Wu, Carole-Jean Harvard University United States Meta United States

ISBN: (纸本)9798331506476

The world's push toward an environmentally sustainable society is highly dependent on the semiconductor industry. Despite existing carbon modeling efforts to quantify carbon footprint of computing systems, optimizing carbon footprint in large design spaces-while also considering trade-offs in power, performance, and area-is especially challenging. To address this need, we present CORDOBA, a carbon-aware optimization framework that optimizes carbon efficiency. We quantify carbon efficiency using the total Carbon Delay Product metric (tCDP): the product of total carbon and application execution time. We justify why tCDP is an effective metric for quantifying carbon efficiency. We use CORDOBA to explore the large design space for carbonefficient specialized hardware, and identify distinct carbonefficient optimal designs across operational use (eliminating up to {9 8%} of the design space) despite uncertainty in carbon footprint parameters. We quantify opportunities to improve tCDP for real system case studies: (a) optimizing hardware provisioning from 8 to 4 cores in real system CPUs improves tCDP by 1.25 ×;and (b) leveraging advanced three-dimensional (3D) integration techniques (3D stacking of separately-fabricated logic and memory chips) improves tCDP by 6.9 × versus conventional systems. © 2025 IEEE.

关键词： carbon footprint carbon-aware optimization carbon-efficient computing metrics

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Leveraging Valgrind to Assess Concurrent, Testing-Unaware C Programs 31

Leveraging Valgrind to Assess Concurrent, Testing-Unaware C ...

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31st IEEE international Conference on high performance computing, Data, and Analytics workshops, HiPCW 2024

作者： Dewan, Prasun Gaddis, Nalin Department of Computer Science University of North Carolina Chapel Hill United States

ISBN: (纸本)9798331509118

Concurrent programming has allowed software to increase the power of CPUs, but is inherently error-prone because of its complexity and non-determinism. A low-level language such as C further increases the difficulty of writing concurrent programs Existing solutions for checking application-specific functional concurrency constraints do not support C and require the tested concurrent programs to be testing-aware by producing special log traces. We have developed a new framework, called Valgrind++, which uses Valgrind to instrument binary code to generate traces automatically. The framework provides (a) a mechanism to specify traced method calls, and (b) initial high-level and flexible abstractions to create tests that process the traces of these calls. These abstractions allow instructors to trade programming effort with testing accuracy based on their experience with the kind of mistakes students make and their ability to catch these mistakes manually. This paper describes Valgrind++ and how it can be used to make these tradeoffs. It presents complete tests for a series of related introductory examples for trace-based instruction on threads, context switching, locks, and conditions. It also describes a case study of a complex operating systems assignment for advanced students, which shows the potential of using Valgrind++ to save grading effort, catch manual grading errors, and provide direction to those struggling to meet the concurrency requirements. © 2024 IEEE

关键词： Students

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CROSS: Compiler-Driven Optimization of Sparse DNNs Using Sparse/Dense Computation Kernels 31

CROSS: Compiler-Driven Optimization of Sparse DNNs Using Spa...

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31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Liu, Fangxin Huang, Shiyuan Yang, Ning Wang, Zongwu Li, Haomin Jiang, Li Shanghai Jiao Tong University Department of Computer Science and Engineering China Shanghai Qi Zhi Institute China

ISBN: (纸本)9798331506476

As deep learning models continue to grow larger and more complex, exploiting sparsity is becoming one of the most critical areas for enhancing efficiency and scalability. Several methods for leveraging sparsity have been proposed to more effectively balance the trade-off between compression ratio and accuracy. While these methods offer algorithmic advantages, they also introduce significant hardware overhead due to index-based encoding and decoding. In this paper, we propose CROSS, an end-to-end compilation optimization technique to achieve sparse DNN acceleration using GPU computation kernels. The key insight behind CROSS is to exploit parameter distribution locality and reconcile the 'sparse' DNN computation with the high-performance 'dense' computation kernels. Specifically, we perform an in-depth analysis of sparse operations in mainstream DNN computing frameworks. We then decompose the sparse workload into multiple components to create highly efficient, specialized operators with different sparsity levels. Additionally, we introduce a novel sparse graph translation technique to facilitate computation kernel processing of the sparse workload. The resulting CROSS framework can accommodate various sparsity patterns and optimization techniques, delivering an average 2.03 × speedup on inference latency compared to seven state-of-the-art solutions with smaller memory footprints across various models and datasets. © 2025 IEEE.

关键词： Program compilers

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NeuVSA: A Unified and Efficient Accelerator for Neural Vector Search 31

NeuVSA: A Unified and Efficient Accelerator for Neural Vecto...

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31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Yuan, Ziming Dai, Lei Li, Wen Zhang, Jie Liang, Shengwen Wang, Ying Liu, Cheng Li, Huawei Li, Xiaowei Guo, Jiafeng Wang, Peng Chen, Renhai Zhang, Gong Shanxi University School of Computer and Information Technology China Peking University School of Computer Science China Institute of Computing Technology CAS State Key Lab of Processors China University of Chinese Academy of Sciences China Zhongguancun National Laboratory Beijing China Institute of Computing Technology CAS Key Lab of Network Data Science and Technology China Huawei Technologies Co. Ltd. China

ISBN: (纸本)9798331506476

Neural Vector Search (NVS) has exhibited superior search quality over traditional key-based strategies for information retrieval tasks. An effective NVS architecture requires high recall, low latency, and high throughput to enhance user experience and cost-efficiency. However, implementing NVS on existing neural network accelerators and vector search accelerators is sub-optimal due to the separation between the embedding stage and vector search stage at both algorithm and architecture levels. Fortunately, we unveil that Product Quantization (PQ) opens up an opportunity to break separation. However, existing PQ algorithms and accelerators still focus on either the embedding stage or the vector search stage, rather than both simultaneously. Simply combining existing solutions still follows the beaten track of separation and suffers from insufficient parallelization, frequent data access conflicts, and the absence of scheduling, thus failing to reach optimal recall, latency, and throughput. To this end, we propose a unified and efficient NVS accelerator dubbed NeuVSA based on algorithm and architecture co-design philosophy. Specifically, on the algorithm level, we propose a learned PQ-based unified NVS algorithm that consolidates two separate stages into the same computing and memory access paradigm. It integrates an end-to-end joint training strategy to learn the optimal codebook and index for enhanced recall and reduced PQ complexity, thus achieving smoother acceleration. On the architecture level, we customize a homogeneous NVS accelerator based on the unified NVS algorithm. Each sub-accelerator is optimized to exploit all parallelism exposed by unified NVS, incorporating a structured index assignment strategy and an elastic on-chip buffer to alleviate buffer conflicts for reduced latency. All sub-accelerators are coordinated using a hardware-aware scheduling strategy for boosted throughput. Experimental results show that the joint training strategy improves recall

关键词： Network embeddings

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Extensions for compiler infrastructure for neural networks to support automated generation of high-performance tensor programs for DSPs 9

Extensions for compiler infrastructure for neural networks t...

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9th international symposium on Advances in Electrical, Electronics, and computer Engineering, ISAEECE 2024

作者： Huang, Rui Li, Zhe Ji, Yuxiong Yang, Jing Wang, Yaohua College of Computer National University of Defense Technology Changsha410073 China

ISBN: (纸本)9781510683303

To widely apply deep learning technology, it is necessary to deploy neural network models on different hardware platforms. Multi-core Digital Signal Processors (DSPs), as one of these platforms, exhibit the potential to accelerate deep learning in specific applications and scenarios due to their energy efficiency advantages. CINN, as an AI compiler, is been proposed for deploying DNN models on diverse hardware devices. However, due to differences in hardware architectures, there is a risk of poor utilization of memory and computing resources, leading to increased execution time. In this work, we propose several extensions to achieve optimization specific to DSPs, and allow CINN to automatically generate high-performance tensor programs for our DSPs through a search approach. Experimental result shows that there is a significant improvement in execution performance for the automatically generated tensor operators containing reduction operation compared to manual schedule. © 2024 SPIE.

关键词： Program compilers

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Empirical Study of Molecular Dynamics Workflow Data Movement: DYAD vs. Traditional I/O Systems

Empirical Study of Molecular Dynamics Workflow Data Movement...

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1st international Conference on Smart Energy Systems and Artificial Intelligence (SESAI)

作者： Lumsden, Ian Devarajan, Hariharan Marquez, Jack Brink, Stephanie Boehme, David Pearce, Olga Yeom, Jae-Seung Taufer, Michela Univ Tennessee Dept Elect Engn & Comp Sci Knoxville TN 37996 USA Lawrence Livermore Natl Lab Livermore CA 94550 USA

ISBN: (纸本)9798350364613;9798350364606

This experimental work examines data movement in molecular dynamics (MD) workflows, comparing the Dynamic and Asynchronous Data Streamliner (DYAD) middleware with traditional, industry-standard I/O systems such as XFS and Lustre. DYAD moves MD simulation frames to analytics processes, providing enhanced flexibility and efficiency for dynamic data transfers and in situ analytics. At the same time, traditional I/O storage systems provide durability and scalability for high-performance computing (HPC) systems. The study integrates MD workflows with common simulation codes, facilitating immediate capture and transfer of MD frames to a staging area. It explores various molecular models, from simple to complex, assessing data management performance and scalability. Different producer-consumer pairs, molecular models, and data transaction frequency enable testing across small to large-scale HPC scenarios, from single-node configurations to large, distributed environments. The findings reveal that adaptive mechanisms for minimizing synchronization, direct network communication between producer and consumer processes, and optimizations of both data movement and synchronization are crucial for performance and scalability in MD workflows.

关键词： Producer-Consumer Paradigm Molecular Dynamics Workflows Dynamic Data Management high-performance computing In Situ Analytics

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Improving Parallel Exhaustive Subgroup Discovery with Early Search Space Pruning 31

Improving Parallel Exhaustive Subgroup Discovery with Early ...

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31st IEEE international Conference on high performance computing, Data, and Analytics workshops, HiPCW 2024

作者： Jyoti Litoriya, Ashutosh Kailasam, Sriram School of Computing and Elect. Engg. Indian Institute of Technology Mandi India Dept. of Computer Sci. and Engg. and IT Jaypee University of Info. Tech. Solan India Genpact India Pvt. Ltd Bangalore India Dept. of Computer Sci. and Engg. National Institute of Technology Warangal India

ISBN: (纸本)9798331509118

In this digital era, vast amounts of data are generated from various applications, necessitating robust data mining algorithms to extract valuable insights. Subgroup discovery (SD) [1] is a widely used supervised descriptive data mining method that aims to find interesting subgroups of individuals (samples, objects) with high associations to a target property of interest. However, SD faces two major challenges. The first is the high computational expense of exploring the combinatorial search space of subgroups. Second, when testing multiple subgroups to identify a few significant associations, ensuring that each subgroup meets a quality threshold is not enough to control the occurrence of false positives. The latter issue has been addressed recently with permutation testing while for the former, exploring the search space of closed subgroups instead of all possible subgroups reduces the search space without loss of information. Pellegrina et al. [2] incorporated both these approaches and provided a sequential implementation TopKWY for discovering the top-k significant subgroups while controlling false discoveries. It is considered state-of-the-art. However, its huge computational requirement of assessing patterns against many permutations raises scalability concerns, while the specific optimizations in its algorithm for computing p-values do not generalize to other quality functions. Jyoti et al. [3] addressed both these concerns in their proposed framework ParaDiS. The algorithm of ParaDiS is parallel and distributed, employs efficient communication mechanisms for load sharing and generalizes to other quality functions. However, ParaDiS uses exhaustive search and therefore, suffers from performance bottlenecks. The existing heuristic techniques in SD neither control false discoveries nor consider the search space of closed subgroups. Further, these heuristics can miss potentially interesting subgroups w.r.t. quality. © 2024 IEEE

关键词： Economic and social effects

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Massively Parallel EEG Algorithms for Pre-exascale architectures

Massively Parallel EEG Algorithms for Pre-exascale Architect...

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29th international Conference on Parallel and Distributed computing (Euro-Par)

作者： Wang, Zeyu Juhasz, Zoltan Univ Pannonia Veszprem Hungary

ISBN: (纸本)9783031488023;9783031488030

high-density EEG is a non-invasive measurement method with millisecond temporal resolution that allows us to monitor how the human brain operates under different conditions. The large amount of data combined with complex algorithms results in unmanageable execution times. Large-scaleGPU parallelism provides the means to drastically reduce the execution time of EEG analysis and bring the execution of large cohort studies (over thousand subjects) within reach. This paper describes our effort to implement various EEG algorithms for multiGPUpre-exascale supercomputers. Several challenges arise during thiswork, such as the high cost of data movement and synchronisation compared to computation. A performance-oriented end-to-end design approach is chosen to develop highlyscalable, GPU-only implementations of full processing pipelines and modules. Work related to the parallel design of the family of Empirical Mode Decomposition algorithms is described in detail with preliminary performance results of single-GPU implementations. The research will continue with multi-GPU algorithm design and implementation aiming to achieve scalability up to thousands of GPU cards.

关键词： EEG Pre-exascale computing GPU

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RSQP: Problem-specific Architectural Customization for Accelerated Convex Quadratic Optimization 23

RSQP: Problem-specific Architectural Customization for Accel...

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50th Annual international symposium on computer architecture (ISCA)

作者： Wang, Maolin McInerney, Ian Stellato, Bartolomeo Boyd, Stephen So, Hayden Kwok-Hay AI Chip Ctr Emerging Smart Syst Hong Kong Peoples R China Univ Manchester Manchester Lancs England Princeton Univ Princeton NJ 08544 USA Stanford Univ Stanford CA 94305 USA Univ Hong Kong Hong Kong Peoples R China

ISBN: (纸本)9798400700958

Convex optimization is at the heart of many performance-critical applications across a wide range of domains. Although many high-performance hardware accelerators have been developed for specific optimization problems in the past, designing such accelerator is a challenging task and the resulting computing architecture is often so specific to the targeted application that they can hardly be reused even in a related application within the same domain. To accelerate general-purpose optimization solvers that must operate on diverse user input during run time, an ideal hardware solver should be able to adapt to the provided optimization problem dynamically while achieving high performance and power-efficiency. In this work, a hardware-accelerated general-purpose quadratic program solver, called RSQP, with reconfigurable functional units and data path that facilitate problem-specific customization is presented. RSQP uses a string-based encoding to describe the problem structure with fine granularity. Based on this encoding, functional units and datapath customized to the sparsity pattern of the problem are created by solving a dictionary-based lossless string compression problem and a mixed integer linear program respectively. RSQP has been integrated to accelerate the general-purpose quadratic programming solver OSQP and has been tested using an extensive benchmark with 120 optimization problems from 6 application domains. Through architectural customization, RSQP achieves up to 7x performance improvement over its baseline generic design. Furthermore, when compared with a CPU and a GPU-accelerated implementation, RSQP achieves up to 31.2x and 6.9x end-to-end speedup on these benchmark programs, respectively. Finally, the FPGA accelerator operates at up to 6.6x lower dynamic power consumption and up to 22.7x higher power efficiency over the GPU implementation, making it an attractive solution for power-conscious datacenter applications.

关键词： convex optimization FPGA quadratic programming domain-specific architectures reconfigurable computing

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Spectral-Blaze: A high-performance FFT-Based CNN Accelerator 20th

Spectral-Blaze: A High-Performance FFT-Based CNN Accelerator

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20th international symposium on Applied Reconfigurable computing (ARC)

作者： Sunny, Shine Parekkadan Das, Satyajit Indian Inst Technol IIT Palakkad Palakkad Kerala India

ISBN: (纸本)9783031556722;9783031556739

This paper presents Spectral-Blaze, a novel FFT-based CNN accelerator that effectively addresses computational and energy bottlenecks in spatial domain acceleration. The proposed architecture introduces Intra-Patch parallelization during the Hadamard product phase, which optimizes Complex MAC (CMAC) unit utilization and maintains consistent reuse patterns across multiple input feature map patches. This parallelization scheme simplifies the tiling, enabling independent selection of patch elements for efficient on-chip memory storage. Additionally, it leverages the Flex-Stationary dataflow to adaptively store tensors with high reuse opportunities in the on-chip memory, reducing the DRAM traffic. Spectral-Blaze also introduces an optimized FFT/IFFT process that integrates a modified row-column FFT, real FFT-based optimizations, and a vector-radix IFFT. The Spectral-Blaze prototype, implemented on the Zynq MPSoC (ZU7CG), demonstrates impressive performance gains, achieving a speedup of 4.98x for VGG-16 and 1.64x for AlexNet compared to baseline. The Energy-Delay Product (EDP) varies from 4.47x to 25.14x. Compared to flexible dataflow spatial accelerators, Spectral-Blaze achieves an average improvement of 8.82x over Eyeriss and 7.87x improvement over Flexflow in EDP while maintaining a comparable hardware setup. Spectral-Blaze also achieves a 4.59x reduction in MAC operations during convolution, even with VGG-16's compact filter sizes.

关键词： FFT-based convolution Tiling DNN Accelerator Intra-Patch Parallelization Flex-Stationary

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