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Enabling high performance Debugging for Variational Quantum Algorithms using Compressed Sensing 23

Enabling High Performance Debugging for Variational Quantum ...

引用

50th Annual international symposium on computer architecture (ISCA)

作者： Liu, Kun Hao, Tianyi Tannu, Swamit Carnegie Mellon Univ Pittsburgh PA 15213 USA Univ Wisconsin Madison Madison WI USA

ISBN: (纸本)9798400700958

Variational quantum algorithms (VQAs) can potentially solve practical problems using contemporary Noisy Intermediate Scale Quantum (NISQ) computers. VQAs find near-optimal solutions in the presence of qubit errors by classically optimizing a loss function computed by parameterized quantum circuits. However, developing and testing VQAs is challenging due to the limited availability of quantum hardware, their high error rates, and the significant overhead of classical simulations. Furthermore, VQA researchers must pick the right initialization for circuit parameters, utilize suitable classical optimizer configurations, and deploy appropriate error mitigation methods. Unfortunately, these tasks are done in an adhoc manner today, as there are no software tools to configure and tune the VQA hyperparameters. In this paper, we present OSCAR (cOmpressed Sensing based Cost lAndscape Reconstruction) to help configure: 1) correct initialization, 2) noise mitigation techniques, and 3) classical optimizers to maximize the quality of the solution on NISQ hardware. OSCAR enables efficient debugging and performance tuning by providing users with the loss function landscape without running thousands of quantum circuits as required by the grid search. Using OSCAR, we can accurately reconstruct the complete cost landscape with up to 100X speedup. Furthermore, OSCAR can compute an optimizer function query in an instant by interpolating a computed landscape, thus enabling the trial run of a VQA configuration with considerably reduced overhead.

关键词： Quantum computing Variational Quantum Algorithms Debugging

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VAQUERO: A Scratchpad-based Vector Accelerator for Query Processing 29

VAQUERO: A Scratchpad-based Vector Accelerator for Query Pro...

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29th IEEE international symposium on high-performance computer architecture (HPCA)

作者： Pavon, Julian Vargas Valdivieso, Ivan Marimon, Joan Figueras, Roger Moll, Francesc Unsal, Osman Valero, Mateo Cristal, Adrian Barcelona Supercomp Ctr Barcelona Spain Univ Politecn Cataluna Barcelona Spain

ISBN: (纸本)9781665476522

Database Management Systems (DBMS) have become an essential tool for industry and research and are often a significant component of data centers. There have been many efforts to accelerate DBMS application performance. One of the most explored techniques is the use of vector processing. Unfortunately, conventional vector architectures have not been able to exploit the full potential of DBMS acceleration. In this paper, we present VAQUERO, our Scratchpad-based Vector Accelerator for QUEry pROcessing. VAQUERO improves the efficiency of vector architectures for DBMS operations such as data aggregation and hash joins featuring lookup tables. Lookup tables are significant contributors to the performance bottlenecks in DBMS processing suffering from insufficient ISA support in the form of scatter-gather instructions. VAQUERO introduces a novel Advanced Scratchpad Memory specifically designed with two mapping modes - direct- and associative-mode. These mapping modes enable VAQUERO to accelerate real-world databases with workload sizes that significantly exceed the scratchpad memory capacity. Additionally, the associative-mode allows to use VAQUERO with DBMS operators that use hashed keys, e.g. hash-join and hash-aggregate. VAQUERO has been designed considering general DBMS algorithm requirements instead of being based on a particular database organization. For this reason, VAQUERO is capable to accelerate DBMS operators for both row- and column-oriented databases. In this paper, we evaluate the efficiency of VAQUERO using two highly optimized popular open-source DBMS, namely the row-based PostgreSQL and column-based MonetDB. We implemented VAQUERO at the RTL level and prototype it, by performing Place&Route, at the 7nm technology node. VAQUERO incurs a modest 0.15% area overhead compared with an Intel Ice Lake processor. Our evaluation shows that VAQUERO significantly outperforms PostgreSQL and MonetDB by 2.09x and 3.32x respectively, when processing operators and queries

关键词： Vector computing Scratchpad Memory Database Accelerator PostgreSQL MonetDB

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Exploiting FPGAs and Spiking Neural Networks at the Micro-Edge: The EdgeAI Approach 20th

Exploiting FPGAs and Spiking Neural Networks at the Micro-Ed...

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20th international symposium on Applied Reconfigurable computing (ARC)

作者： Meloni, Paolo Busia, Paola Leone, Gianluca Martis, Luca Scrugli, Matteo A. Univ Cagliari Cagliari Sardinia Italy

ISBN: (纸本)9783031556722;9783031556739

This paper outlines the initial FPGA-centric endeavors within the EdgeAI project, targeting scenarios where extremely constrained power-energy parameters intersect with the demand for high performance and accuracy in executing Artificial Intelligence (AI) algorithms. Our discussion, after presenting the generalities of the EdgeAI project, revolves around the project objective of leveraging simultaneously event-based spiking neural networks and low-end FPGA chips for very-low-power near-sensor AI inference. We present the hardware/software implementation of this approach and the early results on the project use cases.

关键词： FPGAs Spiking neural networks edge computing

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Approximate Memory with Protected Static Allocation 34

Approximate Memory with Protected Static Allocation

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34th IEEE international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Fabricio Filho, Joao Felzmann, Isaias Wanner, Lucas Univ Estadual Campinas Inst Comp Campinas Brazil Univ Tecnol Fed Parana Campus Campo Mourao Curitiba Parana Brazil

ISBN: (数字)9781665451550

ISBN: (纸本)9781665451550

Approximate memories provide energy savings or performance improvements at the cost of occasional errors in stored data. Applications that tolerate errors on their data profit from this trade-off by controlling these errors to not affect critical data. This control usually involves programmer intervention with annotations in the source code. To avoid annotations, some techniques protect critical data that are common on many applications, isolating specific memory regions from errors. In this work, we propose and explore alternatives for the protection of application critical data by managing a supervisor execution environment with an approximate memory system. We expose only dynamically allocated data to errors with secure data manipulation through an approximate allocation scheme that divide stored data based on the approximation of the heap area. We evaluate 6 applications with different data access profiles and obtain up to 20% of energy savings.

关键词： Approximate computing Approximate Memory Error Tolerance

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Evaluating HPX and Kokkos on RISC-V using an astrophysics application Octo-Tiger

Evaluating HPX and Kokkos on RISC-V using an astrophysics ap...

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2023 international Conference on high performance computing, Network, Storage, and Analysis, SC workshops 2023

作者： Diehl, Patrick Daiss, Gregor Brandt, Steven Kheirkhahan, Alireza Kaiser, Hartmut Taylor, Christopher Leidel, John Center of Computation & Technology Louisiana State University Baton RougeLA United States Tactical Computing Labs LindsayTX United States

ISBN: (纸本)9798400707858

In recent years, computers based on the RISC-V architecture have raised broad interest in the high-performance computing (HPC) community. As the RISC-V community develops the core instruction set architecture (ISA) along with ISA extensions, the HPC community has been actively ensuring HPC applications and environments [10, 29] are supported. In this context, assessing the performance of asynchronous many-task runtime systems (AMT) is essential. In this paper, we describe our experience with porting of a full 3D adaptive mesh-refinement, multi-scale, multi-model, and multi-physics application, Octo-Tiger, that is based on the HPX AMT, and we explore its performance characteristics on different RISC-V systems. Despite the (limited) capabilities of the RISC-V test systems we used, Octo-Tiger already shows promising results and good scaling. We, however, expect that additional hardware support based on dedicated ISA extensions (such as single-cycle context switches, extended atomic operations, and direct support for HPX's global address space) would allow for even better performance results. © 2023 Owner/Author.

关键词： computer architecture

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Structural Embedding Contrastive Graph Clustering 22

Structural Embedding Contrastive Graph Clustering

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22nd IEEE international symposium on Parallel and Distributed Processing with Applications, ISPA 2024

作者： Zhang, Linlin Zhao, Yaliang Wang, Jinke Henan University School of Computer and Information Engineering Kaifeng China

ISBN: (纸本)9798331509712

The advancement of deep clustering in recent years has been propelled by advances in deep learning technology, breaking through bottlenecks and being widely applied in multiple fields. However, current deep clustering algorithms focus only on single information or cannot fully balance the interrelationships between the original architecture and underlying institutions. Therefore, we propose a new method called structural embedding contrastive graph clustering (SECGC) that can effectively address the aforementioned issues. Firstly, We capture deeper representational information through higher-order neighborhood information models. Secondly, we designed an attribute structure fusion module that adaptively integrates the obtained high-order neighborhood information with the attribute information of the autoencoder. Simultaneously, the multi-scale feature fusion module fuses information from different dimensions to explor varying levels of semantic hierarchy. In addition, a dual self-supervised mechanism and high-confidence pseudo-label technique were designed to guide representation learning and clustering allocation. A new loss function has been designed to explore potential data structures and improve clustering performance by introducing contrastive loss. Extensive experiments on multiple benchmark datasets have shown that our method is comparable to state-of-the-art methods. © 2024 IEEE.

关键词： Contrastive Learning

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Exploring Mapping Strategies for Co-allocated HPC Applications

Exploring Mapping Strategies for Co-allocated HPC Applicatio...

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29th international Conference on Parallel and Distributed computing (Euro-Par)

作者： Vardar, Ioannis Hunold, Sascha Swartvagher, Philippe Traff, Jesper Larsson TU Wien A-1040 Vienna Austria

ISBN: (纸本)9783031488023;9783031488030

In modern HPC systems with deep hierarchical architectures, large-scale applications often struggle to efficiently utilize the abundant cores due to the saturation of resources such as memory. Co-allocating multiple applications to share compute nodes can mitigate these issues and increase system throughput. However, co-allocation may harm the performance of individual applications due to resource contention. Past research suggests that topology-aware mappings can improve the performance of parallel applications that do not share resources. In this work, we implement application-oblivious, topology-aware process-to-core mappings via different core enumerations that support the co-allocation of parallel applications. We show that these mappings have a significant impact on the available memory bandwidth. We explore how these process-to-core mappings can affect the individual application duration as well as the makespan of job schedules when they are combined with co-allocation. Our main objective is to assess whether co-allocation with a topology-aware mapping can be a viable alternative to the exclusive node allocation policies that are currently common in HPC clusters.

关键词： high performance computing Parallel computing performance Optimization Process Mapping Co-allocation

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Direct Spatial Implementation of Sparse Matrix Multipliers for Reservoir computing 28

Direct Spatial Implementation of Sparse Matrix Multipliers f...

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28th Annual IEEE international symposium on high-performance computer architecture (HPCA)

作者： Denton, Matthew Schmit, Herman Google Res Mountain View CA 94043 USA

ISBN: (纸本)9781665420273

Reservoir computing is a nascent sub-field of machine learning which relies on the recurrent multiplication of a very large, sparse, fixed matrix. We argue that direct spatial implementation of these fixed matrices minimizes the work performed in the computation, and allows for significant reduction in latency and power through constant propagation and logic minimization. Bit-serial arithmetic enables massive static matrices to be implemented. We present the structure of our bit-serial matrix multiplier, and evaluate using canonical signed digit representation to further reduce logic utilization. We have implemented these matrices on a large FPGA and provide a cost model that is simple and extensible. These FPGA implementations, on average, reduce latency by 50x up to 86x versus GPU libraries. Comparing against a recent sparse DNN accelerator, we measure a 4.1x to 47x reduction in latency depending on matrix dimension and sparsity.

关键词： Costs Graphics processing units computer architecture Machine learning Reservoirs Throughput Minimization

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Ring Road: A Scalable Polar-Coordinate-based 2D Network-on-Chip architecture 57

Ring Road: A Scalable Polar-Coordinate-based 2D Network-on-C...

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57th Annual IEEE/ACM international symposium on Microarchitecture, MICRO 2024

作者： Feng, Yinxiao Li, Wei Ma, Kaisheng Tsinghua University Beijing China Tsinghua University Department of Computer Science and Technology Beijing China

ISBN: (纸本)9798350350579

Networks-on-chip (NoCs) are scaled out to build large-scale multi-chip networks to meet the growing demand for computing. However, the traditional router-based NoC architecture has significant limitations: 1) The overhead of routers is high, especially for long-distance traffic that traverses numerous chips and hops;2) On/off-chip traffic is mixed up, so the local NoC performance is dragged down by the cross-chip traffic;3) The routing design of intra/inter-chip networks is also entangled. The alternative router-less solution based on isolated multi-ring (IMR) can address some of these issues;however, the complete lack of routers leads to wiring overhead and limited scalability thus not suitable for large-scale multi-chip networks. Therefore, we are motivated to design a new network architecture that can reduce router/wiring overhead, isolate on/off-chip traffic, and decouple inter/intra-chip routing design by combining the advantages of both routers and router-less rings. In this paper, we propose Ring Road, in which high-speed isolated multi-rings are integrated with compact routers, thus achieving flexible traffic delivery with less router usage and overhead. A polar-coordinate-based description is presented to describe the topology, and corresponding deadlock-free routing algorithms are discussed. As a standalone NoC, Ring Road is low-cost, low-latency, and high-performance. It can also be scaled out into multi-chip networks without redesigning the on-chip routing regardless of inter-chip topology. With low-cost isolated ring channels, no matter how heavy the cross-chip traffic is, the local NoC performance remains consistent. Circuit implementation and post-synthesis analysis show that Ring Road achieves 1.7∼2× bandwidth-per-Area and 1.6∼1.9× bandwidth-per-power compared with the traditional mesh router. Cycle-Accurate simulation shows that Ring Road achieves better performance and energy efficiency at various workloads and configurations. © 2024 IEEE.

关键词： Network-on-chip

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Hierarchical Access Control for Bilateral Security in Medical Privacy Data Retrieval 22

Hierarchical Access Control for Bilateral Security in Medica...

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22nd IEEE international symposium on Parallel and Distributed Processing with Applications, ISPA 2024

作者： Wang, Jianshe Xu, Guangping Wen, Yanyan Hao, Wei Tianjin University of Technology School of Computer Science and Engineering Tianjin China

ISBN: (纸本)9798331509712

The rapid growth of medical data in cloud servers offers a rich resource for medical research and analysis. However, the sensitive nature of this data necessitates robust access controls to ensure privacy and confidentiality. Balancing the utilization of valuable medical information with the protection of personal data privacy poses a significant challenge. To address this challenge, this paper proposes a Hierarchical Retrieval scheme with Bilateral security based on Attribute encryption (BAHR) to facilitate multi-level access control. Based on an attribute-based encryption architecture, the hierarchical access control categorizes users into distinct access groups, allowing for precise data retrieval while maintaining encryption integrity at specified levels. Furthermore, the proposed scheme ensures bilateral security, providing robust protection of patients' private data, database, and user access patterns within untrusted domains. Through security analysis and experimental evaluation, BA-HR demonstrates good performance regarding retrieval time, decryption time and storage space. © 2024 IEEE.

关键词： Differential privacy

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