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检索条件"任意字段=2024 International Symposium on Computer Architecture and High Performance Computing Workshops"

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MeHyper: Accelerating Hypergraph Neural Networks by Exploring Implicit Dataflows 31

MeHyper: Accelerating Hypergraph Neural Networks by Explorin...

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31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Zhao, Wenju Yao, Pengcheng Chen, Dan Zheng, Long Liao, Xiaofei Wang, Qinggang Ma, Shaobo Li, Yu Liu, Haifeng Xiao, Wenjing Sun, Yufei Zhu, Bing Jin, Hai Xue, Jingling Huazhong University of Science and Technology National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Wuhan430074 China National University of Singapore School of Computing 119077 Singapore Guangxi University School of Computer Electronics and Information NanNing530004 China University of New South Wales School of Computer Science and Engineering SydneyNSW2052 Australia

ISBN: (纸本)9798331506476

Hypergraph Neural Networks (HGNNs) are increasingly utilized to analyze complex inter-entity relationships. Traditional HGNN systems, based on a hyperedge-centric dataflow model, independently process aggregation tasks for hyperedges and vertices, leading to significant computational redundancy. This redundancy arises from recalculating shared information across different tasks. For the first time, we identify and harness implicit dataflows (i.e., dependencies) within HGNNs, introducing the microedge concept to effectively capture and reuse intricate shared information among aggregation tasks, thereby minimizing redundant computations. We have developed a new microedge-centric dataflow model that processes shared information as fine-grained microedge aggregation tasks. This dataflow model is supported by the Read-Process-Activate-Generate execution model, which aims to optimize parallelism among these tasks. Furthermore, our newly developed MeHyper, a microedge-centric HGNN accelerator, incorporates a decoupled pipeline for improved computational parallelism and a hierarchical feature management strategy to reduce off-chip memory accesses for large volumes of intermediate feature vectors generated. Our evaluation demonstrates that MeHyper substantially outperforms the leading CPUbased system PyG-CPU and the GPU-based system HyperGef, delivering performance improvements of 1,032.23 × and 10.51 ×, and energy efficiencies of 1,169.03 × and 9.96 ×, respectively. © 2025 IEEE.

关键词： Redundancy

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Pose Convolutional Routing Towards Lightweight Capsule Networks 22

Pose Convolutional Routing Towards Lightweight Capsule Netwo...

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22nd IEEE international symposium on Parallel and Distributed Processing with Applications, ISPA 2024

作者： Lv, Chengxin Jiang, Guangqi Xu, Shoukun Liu, Yi Changzhou University Academy of Computing and Artificial Intelligence Changzhou213164 China

ISBN: (纸本)9798331509712

An important branch of artificial intelligence systems and architectures is Capsule Networks (CapsNets) have been known extremely large amount of parameters and computation because of the complex capsule routing algorithm, making it difficult deep architectures in the era of deep learning. To address this challenge, in this paper, we propose a simple yet effective capsule routing algorithm. Specifically, we activate the pose of the entity using its activation probability. On top of that, a convolution on the activated pose matrix to learn the high-level capsules' pose matrices. Activations of the high-level capsules can be digged from their pose matrices via convolution and activation. Such mechanism generates fewer network parameters and lightweight computation, which make it practitable a deep CapsNets architecture. Experiments on CIFAR-10/100, Small-NORB, MINIST and even large-scale benchmark PASCAL VOC 2007, demonstrate the effectiveness of the proposed method. © 2024 IEEE.

关键词： Convolution

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IO-SEA: Storage I/O and Data Management for Exascale architectures 21

IO-SEA: Storage I/O and Data Management for Exascale Archite...

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21st ACM international Conference on computing Frontiers, CF 2024

作者： Medeiros, Daniel Gregory, Eric B. Couvee, Philippe Hawkes, James Gougeaud, Sebastien Gilliot, Maike Bressand, Olivier Valeri, Yoann Jaeger, Julien Chapon, Damien Bournaud, Frederic Strafella, Loïc Caviedes-Voullième, Daniel Tashakor, Ghazal Zjupa, Jolanta Holicki, Max Ridley, Tom Müller, Yanik Guimarães, Filipe Souza Mendes Frings, Wolfgang Mirus, Jan-Oliver Zhukov, Ilya Borba, Eric Rodrigues Moti, Nafiseh Salkhordeh, Reza Derbey, Nadia Mimouni, Salim Derr, Simon Gursoy, Buket Benek Grogan, James Furmánek, Radek Golasowski, Martin Slaninová, Kateåina Martinovič, Jan Faltýnek, Jan Wong, Jenny Cakircali, Metin Quintino, Tiago Smart, Simon Iffrig, Olivier Narasimhamurthy, Sai Happ, Sonja Rauh, Michael Krempel, Stephan Wiggins, Mark Nováček, Jiåí Brinkmann, André Markidis, Stefano Denier, Philippe KTH Royal Institute of Technology Sweden Forschungszentrum Jülich Germany Eviden France European Centre for Medium-Range Weather Forecasts United Kingdom Commissariat À l'Énergie Atomique et Aux Énergies Alternatives France ParTec AG Germany IT4Innovations VSB-Technical University of Ostrava Czech Republic SEAGATE United Kingdom Central European Institute of Technology Czech Republic Irish Centre for High-End Computing Ireland Johannes Gutenberg University Mainz Germany

ISBN: (纸本)9798400704925

The new emerging scientific workloads to be executed in the upcoming exascale supercomputers face major challenges in terms of storage, given their extreme volume of data. In particular, intelligent data placement, instrumentation, and workflow handling are central to application performance. The IO-SEA project developed multiple solutions to aid the scientific community in adressing these challenges: a Workflow Manager, a hierarchical storage management system, and a semantic API for storage. All of these major products incorporate additional minor products that support their mission. In this paper, we discuss both the roles of all these products and how they can assist the scientific community in achieving exascale performance. © 2024 Owner/Author.

关键词： Supercomputers

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Accelerating Function-Centric Applications by Discovering, Distributing, and Retaining Reusable Context in Workflow Systems 24

Accelerating Function-Centric Applications by Discovering, D...

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33rd international symposium on high-performance Parallel and Distributed computing (HPDC)

作者： Thanh Son Phung Thomas, Colin Ward, Logan Chard, Kyle Thain, Douglas Univ Notre Dame Notre Dame IN 46556 USA Argonne Natl Lab Lemont IL USA Univ Chicago Chicago IL USA

ISBN: (纸本)9798400704130

Workflow systems provide a convenient way for users to write large-scale applications by composing independent tasks into large graphs that can be executed concurrently on high-performance clusters. In many newer workflow systems, tasks are often expressed as a combination of function invocations in a high-level language. Because necessary code and data are not statically known prior to execution, they must be moved into the cluster at runtime. An obvious way of doing this is to translate function invocations into self-contained executable programs and run them as usual, but this brings a hefty performance penalty: a function invocation now needs to piggyback its context with extra code and data to a remote node, and the remote node needs to take extra time to reconstruct the invocation's context before executing it, both detrimental to lightweight short-running functions. A better solution for workflow systems is to treat functions and invocations as first-class abstractions: subsequent invocations of the same function on a worker node should only pay for the cost of context setup once and reuse the context between different invocations. The remaining problems lie in discovering, distributing, and retaining the reusable context among workers. In this paper, we discuss the rationale and design requirement of these mechanisms to support context reuse, and implement them in TaskVine, a data-intensive distributed framework and execution engine. Our results from executing a large-scale neural network inference application and a molecular design application show that treating functions and invocations as first-class abstractions reduces the execution time of the applications by 94.5% and 26.9%, respectively.

关键词： Workflow Systems Serverless computing Distributed Storage Burst Buffers

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Dynamic Tasks Scheduling with Multiple Priorities on Heterogeneous computing Systems

Dynamic Tasks Scheduling with Multiple Priorities on Heterog...

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1st international Conference on Smart Energy Systems and Artificial Intelligence (SESAI)

作者： Tayeb, Hayfa Bramas, Berenger Faverge, Mathieu Guermouche, Abdou Bordeaux Univ INRIA ICube Lab Bordeaux France Strasbourg Univ INRIA ICube Lab Strasbourg France Bordeaux Univ INRIA Bordeaux INP CNRS Bordeaux France Bordeaux Univ INRIA LaBRI Lab Bordeaux France

ISBN: (纸本)9798350364613;9798350364606

The efficient utilization of heterogeneous computing systems is crucial for scientists and industrial organizations to execute computationally intensive applications. Task-based programming has emerged as an effective approach for harnessing the processing power of these systems. However, effective scheduling of task-based applications is critical for achieving high performance. Typically, these applications are represented as directed acyclic graphs (DAGs), which can be optimized through careful scheduling to minimize execution time and maximize resource utilization. In this paper, we introduce MultiPrio, a dynamic task scheduler that aims to minimize the overall completion time of parallelized task-based applications. The goal is to find a trade-off between resource affinity, task criticality, and workload balancing on the resources. To this end, we compute scores for each task and manage the available tasks in the system with a data structure based on a set of priority queues. Tasks are assigned to available resources according to these scores, which are dynamically computed by heuristics based on task affinity and criticality. We also consider workload balancing across resources and data locality awareness. To evaluate the scheduler, we study the performance of dense and sparse linear algebra task-based applications and task-based FMM application using the StarPU runtime system on heterogeneous nodes. Our scheduler shows interesting results compared to other state-of-the-art schedulers in StarPU for regular applications, and excels at optimizing irregular workloads, improving performance by up to 31%.

关键词： Priority-based scheduling Runtime system heterogeneous computing systems

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Comparing Accuracy and Consistency: LLMs vs. SOTA Deep Learning Models in Text-to-SQL 31

Comparing Accuracy and Consistency: LLMs vs. SOTA Deep Learn...

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31st IEEE international Conference on high performance computing, Data, and Analytics workshops, HiPCW 2024

作者： Sai, Arvapelly Aryan Vignesh, Sai Sai Hemanth, S.V. Baruah, Pallav Kumar Department of Mathematics and Computer Science Sri Sathya Sai Institute of Higher Learning Prasanthi Nilayam Sri Sathya Sai District Andhra Pradesh 515134 India

ISBN: (纸本)9798331509118

Text-to-SQL is one of the most prominent areas where Large Language Models (LLMs) have seen extensive application. While Text-to-SQL systems using LLMs and pre-trained deep learning models are evaluated using standard metrics such as Exact Match (EM), Execution Accuracy (EX), and Valid Efficiency Score (VES), they overlook a critical aspect: consistency. This paper introduces a Consistency metric that evaluates a model’s reliability in generating the same SQL query for repeated inputs. In the study, we performed a comparative analysis of the pre-trained deep learning models and large language models (LLMs) using the Spider dataset. The study highlights that the pre-trained deep learning models tend to be more accurate, efficient, and consistent compared to LLMs. LLMs are consistently incorrect, and consistency alone does not guarantee correctness. As the difficulty of SQL queries increases, LLMs struggle more with accuracy, while the pre-trained deep learning models remain more robust. The paper’s findings suggest that consistency, combined with existing metrics, is essential for improving Text-to-SQL systems. © 2024 IEEE

关键词： Contrastive Learning

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LSQCA: Resource-Efficient Load/Store architecture for Limited-Scale Fault-Tolerant Quantum computing 31

LSQCA: Resource-Efficient Load/Store Architecture for Limite...

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31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Kobori, Takumi Suzuki, Yasunari Ueno, Yosuke Tanimoto, Teruo Todo, Synge Tokunaga, Yuuki The University of Tokyo Japan NTT Corporation Japan RIKEN Japan Kyushu University Japan

ISBN: (纸本)9798331506476

Current fault-tolerant quantum computer (FTQC) architectures utilize several encoding techniques to enable reliable logical operations with restricted qubit connectivity. However, such logical operations demand additional memory overhead to ensure fault tolerance. Since the main obstacle to practical quantum computing is the limited qubit count, our primary mission is to design floorplans that can reduce memory overhead without compromising computational capability. Despite extensive efforts to explore FTQC architectures, even the current state-of-the-art floorplan strategy devotes 50% of memory space to this overhead, not to data storage, to guarantee unit-time random access to all logical qubits. In this paper, we propose an FTQC architecture based on a novel floorplan strategy, Load/Store Quantum computer architecture (LSQCA), which can achieve almost 100% memory density. The idea behind our architecture is to separate the whole memory regions into small computational space called Computational Registers (CR) and space-efficient memory space called Scan-Access Memory (SAM). We define an instruction set for these abstract structures and provide concrete designs named point-SAM and line-SAM architectures. With this design, we can improve the memory density by allowing variable-latency memory access while concealing the latency with other bottlenecks. We also propose optimization techniques to exploit properties of quantum programs observed in our static analysis, such as access locality in memory reference timestamps. Our numerical results indicate that LSQCA successfully leverages this idea. In a resource-restricted situation, a specific benchmark shows that we can achieve approximately 90% memory density with 5% increase in the execution time compared to a conventional floorplan, which achieves at most 50% memory density for unit-time random access. Our design is defined as an abstract form, making this principle ubiquitous and applicable to a wide range of quant

关键词： Qubits

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LSTM-based Framework for 5G Resource Allocation Prediction 11

LSTM-based Framework for 5G Resource Allocation Prediction

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11th international symposium on Telecommunication, IST 2024

作者： Pourmahboubi, Amin Tabrizchi, Hamed University of Tabriz Faculty of Mathematics Statistics and Computer Science Department of Computer Science Tabriz Iran

ISBN: (纸本)9798350356250

During the rapid evolution of 5G networks, the efficient allocation of bandwidth, frequency spectrum, and computing power is critical to maintaining a high standard of service and performance. A methodology for predicting resource allocation percentages based on Long-Short-Term Memory (LSTM) is presented in this paper. The ability to predict resource allocation percentages enhances network operators' efficiency in terms of bandwidth, frequency spectrum, and computing power utilization. Network operators can maintain high service levels by accurately predicting resource needs and allocating resources dynamically. In high-latency and high-reliability applications such as VoIP calls, video streaming, and emergency services, this is particularly critical. From Iot sensor data to high-definition video calls and emergency services, our proposed model explores the specific resource requirements of a 5 G network. Our experimental results show that the LSTM model achieves a considerable improvement in performance when compared to the best-performing machine learning model, with an R2 score of 0.976 compared to 0.937 for the best-performing model. Predictive accuracy is improved by approximately 4.16 percent. This highlights the superiority of our proposed framework to recognizing patterns in time series data. © 2024 IEEE.

关键词： 5G mobile communication systems

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Combining TL and KD for Object Detection Model Compression 13

Combining TL and KD for Object Detection Model Compression

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Joint 13th international Conference on Soft computing and Intelligent Systems and 25th international symposium on Advanced Intelligent Systems, SCIS and ISIS 2024

作者： Peng, Yuhan Lyu, Yan Zhao, Qiangfu The University of Aizu Computer Science and Engineering Aizuwakamatsu965-8580 Japan Muroran Institute of Technology Sciences and Informatics Muroran050a-8585 Japan

ISBN: (纸本)9798350373332

In modern society, object detection tasks have become extremely important due to their numerous applications in fields such as autonomous driving, surveillance, and healthcare. Real-time detection is particularly crucial for many applications. However, with the advancements in deep learning-based object detection methods, high performance often comes with high computational resource requirements, posing challenges for real-time monitoring, especially on resource-constrained devices. To address this issue, we study model compression using both transfer learning (TL) and knowledge distillation (KD). Specifically, we use the YOLOv5n model as a test case to show the basic idea for improving the performance of a small student model using a larger dataset for TL and a larger model for KD. As for KD, we further investigate feature-based and output-based KD. Experimental results show that the small student model can be improved significantly using TL and KD, with the mean Average Precision (mAP0.5) being increased by 13.28% compared to the baseline model. These results demonstrate the effectiveness of TL and KD in achieving high detection performance while reducing computational demands, making them suitable for various real-world applications. © 2024 IEEE.

关键词： Adversarial machine learning

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HiHiSpMV: Sparse Matrix Vector Multiplication with Hierarchical Row Reductions on FPGAs with high Bandwidth Memory 32

HiHiSpMV: Sparse Matrix Vector Multiplication with Hierarchi...

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32nd IEEE Annual international symposium on Field-Programmable Custom computing Machines, FCCM 2024

作者： Tareen, Abdul Rehman Meyer, Marius Plessl, Christian Kenter, Tobias Paderborn University Paderborn Center for Parallel Computing Department of Computer Science Warburger Str. 100 Paderborn33098 Germany

ISBN: (纸本)9798350372434

The multiplication of a sparse matrix with a dense vector is a vital operation in linear algebra, with applications in numerous contexts. After earlier research on FPGA acceleration of this operation had shown the potential to achieve a high bandwidth efficiency, this workload has received renewed attention with the introduction of high bandwidth memory on FPGA platforms. However, previous designs fell short of scaling to the full bandwidth potential of current FPGA platforms with high bandwidth memory. In this work, we present HiHiSpMV with a novel design approach around hierarchical accumulation, which allows us to overcome several limitations of the related work. Our design is completely implemented with high-level synthesis and compiled with Vitis, and instantiates 16 independent compute units, each processing up to 16 matrix elements per clock cycle. The reduction of these elements is performed without any latency or resource overhead and the subsequent accumulation uses the well-established shift-register design pattern. Due to the independent nature of compute units, our design can connect to all of the 32 high bandwidth memory pseudo-channels in 512-bit interface mode on an Alveo U280 FPGA board. In our tests, we reach up to 86% of the theoretical available bandwidth of this FPGA platform, enabling a computational throughput of up to 98 GFLOPS. This is about 1.5 × faster than the peak throughput of the best related work in that regard, Serpens. On average, the throughput of HiHiSpMV is even 2.7× higher than Serpens. © 2024 IEEE.

关键词： Shift registers

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