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Scalable, high-Quality Scheduling of Data Center Workloads 23

Scalable, High-Quality Scheduling of Data Center Workloads

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23rd IEEE/ACM international symposium on Cluster, Cloud and Internet computing (CCGrid)

作者： Thiyyakat, Meghana Kalambur, Subramaniam Sitaram, Dinkar PES Univ Bangalore India Cloud Comp Innovat Council India Bangalore India

ISBN: (纸本)9798350302080

Data center schedulers must make complex trade-offs and optimizations to achieve their scalability and high-quality scheduling goals. Scalability refers to the scheduler's ability to support both the increasing scale of the workloads (in terms of arrival rate and resource demand) and the infrastructure required by these workloads. Scheduling quality refers to the scheduler's ability to meet the user's performance requirements (such as latency guarantees and placement constraints) without compromising the data center's resource utilization. We propose two solutions to achieve scalability and high-quality scheduling. The first is Megha, a decentralized, federated scheduling framework that uses an eventually-consistent global state to make fast, high-quality scheduling decisions for data centers with tens of thousands of nodes. The second is an intra-node scheduling technique called Niyama, which provides robust CPU bandwidth isolation to latency-sensitive tasks - protecting them from interference from co-located tasks. The two frameworks have been evaluated using workloads generated from publicly available cluster traces, and the results show significant improvements over existing state-of-the-art solutions.

关键词： data center scheduling resource isolation federated architecture cgroups

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DLHT: A Non-blocking Resizable Hashtable with Fast Deletes and Memory-awareness 24

DLHT: A Non-blocking Resizable Hashtable with Fast Deletes a...

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33rd international symposium on high-performance Parallel and Distributed computing (HPDC)

作者： Katsarakis, Antonios Gavrielatos, Vasilis Ntarmos, Nikos Huawei Res Shenzhen Peoples R China

ISBN: (纸本)9798400704130

This paper presents DLHT, a concurrent in-memory hashtable. Despite efforts to optimize hashtables, that go as far as sacrificing core functionality, state-of-the-art designs still incur multiple memory accesses per request and block request processing in three cases. First, most hashtables block while waiting for data to be retrieved from memory. Second, open-addressing designs, which represent the current state-of-the-art, either cannot free index slots on deletes or must block all requests to do so. Third, index resizes block every request until all objects are copied to the new index. Defying folklore wisdom, DLHT forgoes open-addressing and adopts a fully-featured and memory-aware closed-addressing design based on bounded cache-line-chaining. This design offers 1 lock-free operations and deletes that free slots instantly, 2 completes most requests with a single memory access, 3 utilizes software prefetching to hide memory latencies, and 4 employs a novel non-blocking and parallel resizing. In a commodity server and a memory-resident workload, DLHT surpasses 1.6B requests per second and provides 3.5x (12x) the throughput of the state-of-the-art closed-addressing (open-addressing) resizable hashtable on Gets (Deletes).

关键词： high throughput in-memory non-blocking hastable prefetching consistency memory-aware deletes resize close-addressing

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A high-performance Hardware Accelerator for Genome Alignment 22

A High-performance Hardware Accelerator for Genome Alignment

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22nd IEEE international symposium on Parallel and Distributed Processing with Applications, ISPA 2024

作者： Liao, Haoyu Li, Yuan Wang, Qiang Lai, Mingche Su, Hui Li, Ziwen Qi, Xingyun National University of Defense Technology School of Computer Science Changsha China

ISBN: (纸本)9798331509712

Genome alignment is a vital process in genome sequencing and bio-informatics research. It entails aligning short DNA sequence fragments (usually tens to hundreds of base pairs) with a reference genome sequence, uncovering crucial biological information and variations. However, due to the high computational complexity of current sequence matching algorithms and the rapid growth of genetic data, there exists a computational bottleneck in sequence alignment workflows. Therefore, scholars have turned to using hardware to accelerate this computation, with a focus on high-performance computing. While existing acceleration solutions have mostly concentrated on the classical algorithm, showing significant improvements, there has been limited work on accelerating alignment algorithms in popular bio-informatics software tools (enhanced version). In this paper, we proposed a hardware accelerator for the alignment tasks in the popular sequence alignment tool minimap2 using the KSW2 algorithm. Our approach utilizes an anti-diagonal processing element(PE) array for parallel computation, implements the BAND technology in hardware, and enables support for longer input sequences without sacrificing accuracy. Additionally, we integrated the traceback stage of the KSW2 algorithm in hardware, reducing communication data overhead. We attained a 15.32x acceleration compared to software optimized with Streaming SIMD Extensions (SSE) instruction sets and hyper-threading technology. Additionally, our design shows a 3.42x speedup compared to other high-performance hardware. © 2024 IEEE.

关键词： Gene encoding

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Optimizing Forward Wavefield Storage Leveraging high -Speed Storage Media

Optimizing Forward Wavefield Storage Leveraging High -Speed ...

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1st international Conference on Smart Energy Systems and Artificial Intelligence (SESAI)

作者： Speglich, Joao Kukreja, Navjot Bisbas, George Saraiva, Atila Huckelheim, Jan Luporini, Fabio Washbourne, John SENAI CIMATEC Supercomp Ctr Salvador BA Brazil Univ Liverpool Liverpool Merseyside England Imperial Coll London London England Argonne Natl Lab 9700 S Cass Ave Argonne IL 60439 USA Devito Codes London England Chevron Tech Ctr Houston TX USA

ISBN: (纸本)9798350364613;9798350364606

Full-Waveform Inversion (FWI) is a commonly used adjoint-based optimization technique in geosciences. Similar to other adjoint-based optimizations, MI involves gradient calculations that impose a substantial memory footprint. This memory footprint is often considered the primary bottleneck in this FWI process and has been the subject of extensive research. Previous studies have explored various approaches to mitigate this issue, including optimal checkpointing strategies, lossy compression, subsampling in time, and other methods aimed at reducing the memory requirements. These investigations have typically operated under the assumption that writing the data to disk would result in significant and unacceptable performance degradation, leading to compromises in precision or increased computational costs to conserve memory resourcesin this work, we challenge this assumption in light of recent advancements in high -bandwidth storage, particularly the utilization of Non-Volatile Memory Express solid-state drives (NVMe SSDs). We provide empirical evidence that, with specific combinations of modern hardware, it is indeed feasible to write temporary data to disk during the forward propagation phase and subsequently read it back during the adjoint computation without experiencing substantial performance degradation.

关键词： waveform inversion Adjoint-based optimization Gradient calculations Memory footprint Large-scale inverse problems Parallel computing Non-volatile memory express solid-state drives (NVMe SSDs) high-speed storage

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Thermal Simulation computing Network Based on Deep Learning

Thermal Simulation Computing Network Based on Deep Learning

引用

2024 international symposium on Digital Home, ISDH 2024

作者： Wang, Ruomei Teng, Yi Zhang, Yaoquan Zhou, Fan School of Software and Engineering Guangzhou510303 China School of Computer Science Guangdong University of Education Guangzhou510303 China School of Computer Science Sun Yat-sen University National Engineering Research Center of Digital Life Guangzhou510006 China

ISBN: (纸本)9798331509873

The heat and moisture transfer simulation about human body and clothing is a method to simulate the regulation mechanism of human body, and heat and moisture performance of clothing in thermal environment by using computer technology. According to the simulation results, it can be used to the monitor and predicate the key physiological data of human body, and the functional clothing design. Some mathematical models about this area have been built. However, a large number of differential equations are involved to be used to the numerical computation in the simulation process, which leads to high computational complexity, large memo-ry consumption and long computing time. With the expansion of computing scale, these problems will become more obvious and directly affect the practical application of simulation models. The main work of this paper is to study the efficient solution method based on neural network, and proposed a deep learning-based differential equation computing network. The network uses differential equation as the constraint of the loss function of neural network, and integrates the differential equation into the training and prediction process of the network. The experimental results show that the proposed network can reduce the computational complexity of the simulation model and improve the computational efficiency. © 2024 IEEE.

关键词： Physiological models

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Nimblock: Scheduling for Fine-grained FPGA Sharing through Virtualization 23

Nimblock: Scheduling for Fine-grained FPGA Sharing through V...

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50th Annual international symposium on computer architecture (ISCA)

作者： Mandava, Meghna Reckamp, Paul Chen, Deming Univ Illinois Urbana IL 61801 USA

ISBN: (纸本)9798400700958

As FPGAs become ubiquitous compute platforms, existing research has focused on enabling virtualization features to facilitate fine-grained FPGA sharing. We employ an overlay architecture which enables arbitrary, independent user logic to share portions of a single FPGA by dividing the FPGA into independently reconfigurable slots. We then explore scheduling possibilities to effectively time- and space-multiplex the virtualized FPGA by introducing Nimblock. The Nimblock scheduling algorithm balances application priorities and performance degradation to improve response time and reduce deadline violations. Unlike other algorithms, Nimblock explores pre-emption as a scheduling parameter to dynamically change resource allocations, and automatically allocates resources to enable suitable parallelism for an application without additional user input. In our exploration, we evaluate five scheduling algorithms: a baseline, three existing algorithms, and our novel Nimblock algorithm. We demonstrate system feasibility by realizing the complete system on a Xilinx ZCU106 FPGA and evaluating on a set of real-world benchmarks. In our results, we achieve up to 5.7x lower average response times when compared to a no-sharing and no-virtualization scheduling algorithm and up to 2.1x average response time improvement over competitive scheduling algorithms that support sharing within our virtualization environment. We additionally demonstrate up to 49% fewer deadline violations and up to 2.6x lower tail response times when compared to other high-performance algorithms.

关键词： Virtualization Reconfigurable computing Real-time Scheduling Overlay architectures

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A Research Retrospective on the AMD Exascale computing Journey 50

A Research Retrospective on the AMD Exascale Computing Journ...

引用

50th Annual international symposium on computer architecture (ISCA)

作者： Loh, Gabriel H. Aga, Shaizeen Alsop, Johnathan Blagodurov, Sergey Chalmers, Noel Cownie, David Dutu, Alexandru Greathouse, Joseph L. Hossamani, Sachin Kalamatianos, John Lowell, Daniel Manne, Srilatha Mishkin, Michael Potter, Brandon Rao, Karthik Slice, John Vishnu, Abhinav Wyse, Mark Schulte, Michael J. Aguren, Derrick Bauman, Paul T. Boraten, Travis Chen, Shaoming Curtis, Nicholas Eckert, Yasuko Gurumurthi, Sudhanva Huang, Wei Kayiran, Onur Madan, Niti Mashimo, Susumu Nutter, Mark Punniyamurthy, Kishore Rodgers, Gregory Sridharan, Vilas Wasmundt, Samuel Yalavarti, Adithya Ignatowski, Mike Agrawal, Varun Beckmann, Bradford M. Boyer, Michael Cheng, Kevin Del Pino, Joris Erb, Christopher Gutierrez, Anthony Islam, Mahzabeen Kotra, Jagadish Majumdar, Abhinandan McDougall, Damon Paul, Indrani Puthoor, Sooraj Scrbak, Marko van Oostrum, Rene Wilkening, Mark Yudanov, Dmitri Adhinarayanan, Vignesh Aji, Ashwin M. Beigi, Majed Valad Brantley, William C. Chu, Michael L. Duong, Nam Freitag, Chip Hamidouche, Khaled Jayasena, Nuwan Lee, Alan Malaya, Nicholas Mednick, Elliot Poremba, Matthew Raasch, Steven E. Seyedzadeh, Mohammad van Tassell, Eric Wolfe, Noah Adv Micro Devices Inc Santa Clara CA 95054 USA

ISBN: (纸本)9798400700958

The pace of advancement of the top-end supercomputers historically followed an exponential curve similar to (and driven in part by) Moore's Law. Shortly after hitting the petaflop mark, the community started looking ahead to the next milestone: Exascale. However, many obstacles were already looming on the horizon, such as the slowing of Moore's Law, and others like the end of Dennard Scaling had already arrived. Anticipating significant challenges for the overall high-performance computing (HPC) community to achieve the next 1000x improvement, the U.S. Department of Energy (DOE) launched the Exascale computing Program to enable and accelerate fundamental research across the many technologies needed to achieve exascale computing. AMD had the opportunity to contribute to the so-called "*Forward" programs from the DOE, which were a series of public-private partnerships focused on research and co-design activities covering compute architectures, interconnects, memory systems, chiplets and packaging, software stacks, applications, and more. Some of the research from these programs can now be found in the world's first exascale supercomputer, some were a little ahead of their time and may have an impact in the coming years, and others simply did not pan out. In this paper, we provide a retrospective of AMD's nearly decade-long research journey covering how we tried to predict the architecture of a supercomputer a decade into the future, what we got right, what we got wrong, and some of the insights and learnings that we discovered along the way.

关键词： Exascale HPC high-performance computing supercomputing Frontier memory chiplets heterogeneous compute accelerated processing unit research

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An Instruction-Set Extension to Support Approximate Multicore Processors

An Instruction-Set Extension to Support Approximate Multicor...

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international symposium on computer architecture and high performance computing workshops (SBAC-PADW)

作者： Daniela Catelan Felipe Sovernigo Liana Duenha Ricardo Santos College of Computing (FACOM) Federal University of Mato Grosso do Sul (UFMS) Campo Grande MS Brazil

ISBN: (数字)9798331506735

ISBN: (纸本)9798331506742

Approximate computing encompasses several techniques that can be applied from the application level to the circuit level, offering better performance and lower power consumption at the cost of a lack of precision. Multicore architectures, by distributing the workload among several processing cores, can meet the demand for performance while remaining within the energy limitations. This work focuses on the usage of heterogeneous multicore designs, comprised of approximate cores. Specifically, this paper proposes an extension to RISC-V Instruction-Set architecture (ISA) that supports approximate operations. We have designed a sub-set of approximate integer and floating point instructions that, in turn, are embedded in the operations of mathematical functions (sine, cosine, tangent, exponential, and logarithmic). The proposed technique is named Instruction-Level Approximate Functions (ILAF) and it has been evaluated on accuracy, number of instructions, cycles, and power in six applications using the ACCEPT compiler framework and the SPIKE RISC-V simulator. We have performed experiments comparing our approach to non-approximate and approximate versions of each application. The results show significant improvements, such as a 94.18% reduction in power consumption in the CUBIC application and 78.39% cycles reduction in the IDENTITY_LOG2 application. Additionally, a detailed and comprehensive analysis of ILAF and a software-based approximate technique (FastApprox) in the BLACKSCHOLE application showed that ILAF achieved a reduction in power consumption of 3.02× with 19% code coverage.

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Beyond the Bottleneck: Enhancing high-Concurrency Systems with Lock Tuning 26th

Beyond the Bottleneck: Enhancing High-Concurrency Systems wi...

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26th international symposium on Formal Methods (FM)

作者： Ji, Juntao Cui, Yinyou Fu, Yubao Lin, Qingshan Alibaba Cloud Comp Co Ltd Beijing Peoples R China Apache RocketMQ Community New York NY 10013 USA

ISBN: (纸本)9783031711763;9783031711770

high-concurrency systems often suffer from performance bottlenecks [1]. This is often caused by waiting and context switching caused by fierce competition between threads for locks. As a cloud computing company, we place great emphasis on maximizing performance. In this regard, we transform the lightweight spin-lock and propose a concise parameter fine-tuning strategy, which can break through the system performance bottleneck with minimal risk conditions. This strategy has been validated in Apache RocketMQ [2], a high-throughput message queue system. Through this strategy, we achieved performance improvements of up to 37.58% on X86 CPU and up to 32.82% on ARM CPU. Furthermore, we confirmed the method's consistent effectiveness across different code versions and IO flush strategies, demonstrating its broad applicability in real-world settings. This work offers not only a practical tool for addressing performance issues in high-concurrency systems but also highlights the practical value of formal techniques in solving engineering problems.

关键词： high-Concurrency systems performance optimization Spin-lock backoff

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Investigating Nvidia GPU architecture Trends via Microbenchmarks

Investigating Nvidia GPU Architecture Trends via Microbenchm...

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IEEE international Conference on Cluster computing workshops and Posters (CLUSTER workshops)

作者： Lingqi Zhang Ryan Barton Peng Chen Xiao Wang Toshio Endo Satoshi Matsuoka Mohamed Wahib RIKEN Center for Computational Science Tokyo Institute of Technology National Institute of Advanced Industrial Science and Technology Oak Ridge National Laboratory

ISBN: (数字)9798350383454

ISBN: (纸本)9798350383461

In recent years, GPUs have become crucial tools in high performance computing. To understand the evolution of these devices, we conducted a study analyzing hardware trends in GPUs. This information provides valuable insights into GPU programming and emerging trends in this field. We mainly focus on three features: the floating-point operations per second (FLOPS) of floating-point units (FPUs), device memory access, and machine balance.

关键词： Conferences high performance computing Graphics processing units computer architecture Cluster computing Programming Market research Hardware

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