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检索条件"任意字段=2024 International Symposium on Computer Architecture and High Performance Computing Workshops"

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Towards Accelerating k-NN with MPI and Near-Memory Processing

Towards Accelerating k-NN with MPI and Near-Memory Processin...

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IEEE international symposium on Parallel and Distributed Processing workshops and Phd Forum (IPDPSW)

作者： Hooyoung Ahn Seonyoung Kim Yoomi Park Woojong Han Nick Contini Bharath Ramesh Mustafa Abduljabbar Dhabaleswar K. Panda Supercomputing Technology Research Center Electronics and Telecommunications Research Institute Department of Computer Science and Engineering The Ohio State University

ISBN: (数字)9798350364606

ISBN: (纸本)9798350364613

Message Passing Interface (MPI) is a common parallel programming model in high-performance computing fields. Recently, it has been widely used in Artificial Intelligence (AI) applications. However, the performance of those applications is limited by the memory wall problem, which is the performance gap between the processor and memory. To address these problems, we propose a novel computing architecture for accelerating k-NN query, which is the key operation of AI applications. The proposed computing architecture involves two or more computing nodes within a rack using the memory of an NMP device as a communication buffer and the accelerator of the NMP device for MPI collective communication. The superiority of the proposed method is that it reduces data copying during local computation and eliminates the network cost of gathering local computation results for global computation. Furthermore, it can enhance performance by processing data in the device's memory through near-memory processing. However, since these NMP devices are still in development, with no commercially available products currently, we have undertaken the task of developing them ourselves. Despite these circumstances, to demonstrate the feasibility of our proposed approach, we have implemented it in a single-node environment without making any unreasonable assumptions and have compared it with conventional approaches. Although we are using a single-node environment, we have designed a more sophisticated architecture, analyzed the time complexity, and compared the estimated performance of both the conventional and proposed approaches. We can conclude that the proposed computing architecture is feasible, and we anticipate an even more performance enhancement in a multi-node environment.

关键词： performance evaluation Costs Parallel programming Message passing high performance computing Conferences computer architecture

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performance Analysis and Optimization of Nvidia H100 Confidential computing for AI Workloads 22

Performance Analysis and Optimization of Nvidia H100 Confide...

引用

22nd IEEE international symposium on Parallel and Distributed Processing with Applications, ISPA 2024

作者： Tan, Yifan Mi, Zeyu Institute of Parallel and Distributed Systems Seiee Shanghai Jiao Tong University China

ISBN: (纸本)9798331509712

NVIDIA's H100 Confidential computing (CC) counters the security hazards inherent in cloud AI workloads. It enforces data encryption to achieve data confidentiality, which leads to substantial throughput reductions as high as 93% in various AI workloads (such as TensorRT, PEFT and vLLM). Confronting this substantial overhead issue, we first delve into the underlying causes through meticulous analysis. This groundwork enables us to devise an innovative runtime system that operates seamlessly in the background, completely transparent to end-users. The cornerstone of our system lies in leveraging multiple encryption workers. Experiments demonstrate that our solution effectively reduces throughput drop to less than 28.1%. © 2024 IEEE.

关键词： Confidential computing GPU H100 LLM

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Near-Stream computing: General and Transparent Near-Cache Acceleration 28

Near-Stream Computing: General and Transparent Near-Cache Ac...

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28th Annual IEEE international symposium on high-performance computer architecture (HPCA)

作者： Wang, Zhengrong Weng, Jian Liu, Sihao Nowatzki, Tony Univ Calif Los Angeles Los Angeles CA 90095 USA

ISBN: (纸本)9781665420273

Data movement and communication have become the primary bottlenecks in large multicore systems. The near-data computing paradigm provides a solution: move computation to where the data resides on-chip. Two challenges keep near-data computing from the mainstream: lack of programmer transparency and applicability. Programmer transparency requires providing sequential memory semantics with distributed computation, which requires burdensome coordination. Broad applicability requires support for combinations of address patterns (e.g. affine, indirect, multi-operand) and computation types (loads, stores, reductions, atomics). We find that streams - coarse grain memory access patterns - are a powerful ISA abstraction for near data offloading. Tracking data access at stream-granularity heavily reduces the burden of coordination for providing sequential semantics. Decomposing the problem using streams means that arbitrary combinations of address and computation patterns can be combined for broad generality. With this insight, we develop a paradigm called near-stream computing, comprising a compiler, CPU ISA extension, and a microarchitecture that facilitate programmer transparent computation offloading to shared caches. We evaluate our system on OpenMP kernels that stress broad addressing and compute behavior, and find that 46% of dynamic instructions can be offloaded to remote banks, reducing the network traffic by 76%. Overall it achieves 2.13x speedup over a state-of-the-art near-data computing technique, with a 1.90x energy efficiency gain.

关键词： Stream-Based ISAs Programmer-Transparent Acceleration Near-Data computing

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MXFaaS: Resource Sharing in Serverless Environments for Parallelism and Efficiency 23

MXFaaS: Resource Sharing in Serverless Environments for Para...

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50th Annual international symposium on computer architecture (ISCA)

作者： Stojkovic, Jovan Xu, Tianyin Franke, Hubertus Torrellas, Josep Univ Illinois Champaign IL 61820 USA IBM Res Yorktown Hts NY USA

ISBN: (纸本)9798400700958

Although serverless computing is a popular paradigm, current serverless environments have high overheads. Recently, it has been shown that serverless workloads frequently exhibit bursts of invocations of the same function. Such pattern is not handled well in current platforms. Supporting it efficiently can speed-up serverless execution substantially. In this paper, we target this dominant pattern with a new serverless platform design named MXFaaS. MXFaaS improves function performance by efficiently multiplexing (i.e., sharing) processor cycles, I/O bandwidth, and memory/processor state between concurrently executing invocations of the same function. MXFaaS introduces a new container abstraction called MXContainer. To enable efficient use of processor cycles, an MXContainer carefully helps schedule same-function invocations for minimal response time. To enable efficient use of I/O bandwidth, an MXContainer coalesces remote storage accesses and remote function calls from same-function invocations. Finally, to enable efficient use of memory/processor state, an MXContainer first initializes the state of its container and only later, on demand, spawns a process per function invocation, so that all invocations can share unmodified memory state and hence minimize memory footprint. We implement MXFaaS in two serverless platforms and run diverse serverless benchmarks. With MXFaaS, serverless environments are much more efficient. Compared to a state-of-the-art serverless environment, MXFaaS on average speeds-up execution by 5.2x, reduces P99 tail latency by 7.4x, and improves throughput by 4.8x. In addition, it reduces the average memory usage by 3.4x.

关键词： Serverless computing cloud computing resource management

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MapZero: Mapping for Coarse-grained Reconfigurable architectures with Reinforcement Learning and Monte-Carlo Tree Search 23

MapZero: Mapping for Coarse-grained Reconfigurable Architect...

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50th Annual international symposium on computer architecture (ISCA)

作者： Kong, Xiangyu Huang, Yi Zhu, Jianfeng Man, Xingchen Liu, Yang Feng, Chunyang Gou, Pengfei Tang, Minggui Wei, Shaojun Liu, Leibo Tsinghua Univ BNRist Sch Integrated Circuits Beijing Peoples R China GBA Innovat Inst High Performance Server Guangzhou Guangdong Peoples R China HEXIN Technol Co Ltd Guangzhou Guangdong Peoples R China

ISBN: (纸本)9798400700958

Coarse-grained reconfigurable architecture (CGRA) has become a promising candidate for data-intensive computing due to its flexibility and high energy efficiency. CGRA compilers map data flow graphs (DFGs) extracted from applications onto CGRAs, playing a fundamental role in fully exploiting hardware resources for acceleration. Yet the existing compilers are time-demanding and cannot guarantee optimal results due to the traversal search of enormous search spaces brought about by the spatio-temporal flexibility of CGRA structures and the complexity of DFGs. Inspired by the amazing progress in reinforcement learning (RL) and Monte-Carlo tree search (MCTS) for real-world problems, we consider constructing a compiler that can learn from past experiences and comprehensively understand the target DFG and CGRA. In this paper, we propose an architecture-aware compiler for CGRAs based on RL and MCTS, called MapZero - a framework to automatically extract the characteristics of DFG and CGRA hardware and map operations onto varied CGRA fabrics. We apply Graph Attention Network to generate an adaptive embedding for DFGs and also model the functionality and interconnection status of the CGRA, aiming at training an RL agent to perform placement and routing intelligently. Experimental results show that MapZero can generate superior-quality mappings and reduce compilation time hundreds of times compared to state-of-the-art methods. MapZero can find high-quality mappings very quickly when the feasible solution space is rather small and all other compilers fail. We also demonstrate the scalability and broad applicability of our framework.

关键词： Coarse-Grained Reconfigurable architecture Compiler Graph Neural Network Reinforcement Learning

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Data-Driven Locality-Aware Batch Scheduling

Data-Driven Locality-Aware Batch Scheduling

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1st international Conference on Smart Energy Systems and Artificial Intelligence (SESAI)

作者： Gonthier, Maxime Larsson, Elisabeth Marchal, Loris Nettelblad, Carl Thibault, Samuel Univ Chicago Dept Comp Sci Chicago IL 60637 USA ENS Lyon Lyon France INRIA Le Chesnay Rocquencourt France Uppsala Univ Dept Informat Technol Uppsala Sweden ENS Lyon CNRS Lyon France Univ Bordeaux LaBRI Talence France

ISBN: (纸本)9798350364613;9798350364606

Clusters employ workload schedulers such as the Sturm Workload Manager to allocate computing jobs onto nodes. These schedulers usually aim at a good trade-off between increasing resource utilization and user satisfaction (decreasing job waiting time). However, these schedulers are typically unaware of jobs sharing large input files, which may happen in data intensive scenarios. The same input files may end up being loaded several times, leading to a waste of resources. We study how to design a data-aware job scheduler that is able to keep large input files on the computing nodes, without impacting other memory needs, and can benefit from previously-loaded tiles to decrease data transfers in order to reduce the waiting times ofjobs. We present three schedulers capable of distributing the load between the computing nodes as well as re-using input files already loaded in the memory of some node as much as possible. We perform simulations with single node jobs using traces of real HPC-cluster usage, to compare them to classical job schedulers. The results show that keeping data in local memory between successive jobs and using data -locality information to schedule jobs improves performance compared to a widely -used scheduler (FCFS, with and without backfilling): a reduction in job waiting time (a 7.5% improvement in stretch), and a decrease in the amount of data transfers (7%).

关键词： Batch scheduling Job input sharing Data aware Job scheduling high performance Data Analytics

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Ph.D. Project: A Compiler-Driven Approach to HW/SW Co-Design of Deep-Learning Accelerators 32

Ph.D. Project: A Compiler-Driven Approach to HW/SW Co-Design...

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32nd IEEE Annual international symposium on Field-Programmable Custom computing Machines, FCCM 2024

作者： Kamucheka, Tendayi Andrews, David University of Arkansas Department of Electrical Engineering and Computer Science FayettevilleAR72701 United States

ISBN: (纸本)9798350372434

This work introduces SPAR, a compiler framework based on MLIR, tailored for deep learning inference applications. Alongside SPAR, we present SPAR HL, an extensible Instruction Set architecture (ISA) designed to seamlessly interface custom FPGA-based accelerators with the SPAR compiler. Historically, custom accelerators on FPGA have posed a challenge as a compiler target. Prior compiler initiatives have addressed this issue by generating application-specific hardware during compilation, necessitating expertise across both application and hardware domains. In response, we offer an alternative approach by proposing an ISA as a unified compiler target and hardware interface for custom accelerators. Furthermore, we introduce a compiler capable of translating high-level machine learning models encoded in ONNX into code compatible with our proposed ISA, thus enabling efficient deployment on FPGA-based custom accelerators. © 2024 IEEE.

关键词： Program compilers

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Exploring the Effects of Silent Data Corruption in Distributed Deep Learning Training 34

Exploring the Effects of Silent Data Corruption in Distribut...

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34th IEEE international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Rojas, Elvis Perez, Diego Meneses, Esteban Costa Rica Inst Technol Cartago Costa Rica Natl Univ Costa Rica Heredia Costa Rica Costa Rica Natl High Technol Ctr San Jose Costa Rica

ISBN: (数字)9781665451550

ISBN: (纸本)9781665451550

The profound impact of recent developments in artificial intelligence is unquestionable. The applications of deep learning models are everywhere, from advanced natural language processing to highly accurate prediction of extreme weather. Those models have been continuously increasing in complexity, becoming much more powerful than their original versions. In addition, data to train the models is becoming more available as technological infrastructures sense and collect more readings. Consequently, distributed deep learning training is often times necessary to handle intricate models and massive datasets. Running a distributed training strategy on a supercomputer exposes the models to all the considerations of a large-scale machine;reliability is one of them. As supercomputers integrate a colossal number of components, each fabricated on an ever decreasing feature-size, faults are common during execution of programs. A particular type of fault, silent data corruption, is troublesome because the system does not crash and does not immediately give an evident sign of an error. We set out to explore the effects of that type of faults by inspecting how distributed deep learning training strategies cope with bit-flips that affect their internal data structures. We used checkpoint alteration, a technique that permits the study of this phenomenon on different distributed training platforms and with different deep learning frameworks. We evaluated two distributed learning libraries (Distributed Data Parallel and Horovod) and found out Horovod is slightly more resilient to SDCs. However, fault propagation is similar in both cases, and the model is more sensitive to SDCs than the optimizer.

关键词： Deep learning resilience checkpoint neural networks HDF5 fault injection high performance computing

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PINNProv: Provenance for Physics-Informed Neural Networks

PINNProv: Provenance for Physics-Informed Neural Networks

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international symposium on computer architecture and high performance computing workshops (SBAC-PADW)

作者： Lyncoln S. de Oliveira Liliane Kunstmann Débora Pina Daniel de Oliveira Marta Mattoso Federal University of Rio de Janeiro (COPPE/UFRJ) Institute of Computing - Universidade Federal Fluminense (IC/UFF)

Machine Learning is being used increasingly in different application areas. Physics-Informed Neural Networks (PINN) stand out, adapting neural networks to predict solutions to Physics phenomena. Incorporating Physics knowledge into the loss function of a neural network, PINNs revolutionize the solutions of partial differential equations. Considering the lack of support for analytics and reproducibility of the trained models, in this paper we propose the capture and use of provenance data, aimed at the analysis of PINN models. We conducted experiments using TensorFlow and DeepXDE, in a high-performance computing environment. Our experiments show the contributions of these provenance queries in different PINN applications.

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Strategies for Fault-Tolerant Tightly-Coupled HPC Workloads Running on Low-Budget Spot Cloud Infrastructures 34

Strategies for Fault-Tolerant Tightly-Coupled HPC Workloads ...

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34th IEEE international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Munhoz, Vanderlei Castro, Marcio Mendizabal, Odorico Fed Univ Santa Catarina UFSC Florianopolis SC Brazil

ISBN: (数字)9781665451550

ISBN: (纸本)9781665451550

Cloud providers can rent their spare computing capacity at substantial discounts, reclaiming it whenever there is a more profitable higher-priority request - a business model well known as spot infrastructure market. Users can attain significant cloud investment savings using spot machines, however with the caveat of increasing software complexity, given the fault tolerance requirements of this environment. Improvements in virtualization and network technology, combined with the development of key new software tools, may allow the HPC community to effectively take advantage of cheap cloud resources, cutting expensive maintenance costs. This study aims to evaluate the viability of budget-constrained cloud environments for tightly-coupled MPI applications, exploring both spot and traditional low-budget infrastructures from real public cloud platforms. We propose and evaluate two different fault tolerance strategies tailored for unreliable spot cloud environments: system-level rollback restart with Berkeley Labs Checkpoint/Restart (BLCR) and in-memory rollback restart with User-Level Failure Mitigation (ULFM). We also propose a provider-agnostic empirical method for testing and predicting MPI workloads execution times and cloud infrastructure costs. A detailed cost analysis and performance benchmark of a case-study application is provided, with data gathered from experiments with both spot and persistent machines from AWS and Vultr Cloud, respectively. Our results show that: (i) adequate cluster sizing plays an important role in the overall job execution performance and cost-effectiveness, regardless of the type of selected instances;(ii) fault tolerance strategies based on BLCR may have worse performance than ULFM, but still be cost-effective considering software migration costs;(iii) the use of spot infrastructure does not guarantee costs savings depending on the chosen machine flavors and discounts, as experiments with persistent low-budget options attained better c

关键词： high-performance computing Cloud computing Spot Instances Fault Tolerance MPI Virtual Clusters

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