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检索条件"任意字段=2024 International Symposium on Computer Architecture and High Performance Computing Workshops"

共 5226 条记录，以下是411-420 订阅

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Cost-Effective Methodology for Complex Tuning Searches in HPC: Navigating Interdependencies and Dimensionality

Cost-Effective Methodology for Complex Tuning Searches in HP...

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1st international Conference on Smart Energy Systems and Artificial Intelligence (SESAI)

作者： Dieguez, Adrian P. Choi, Min Okyay, Mahmut Del Ben, Mauro Wong, Bryan M. Ibrahim, Khaled Z. Lawrence Berkeley Natl Lab Berkeley CA 94720 USA Univ Calif Riverside Riverside CA 92521 USA

ISBN: (纸本)9798350364613;9798350364606

Tuning searches in high-performance computing (HPC) are challenged not only by the need to finely tune parameters in application routines but also by considering their potential interdependencies, which renders traditional optimization methods inefficient. Instead of scrutinizing interdependencies among parameters and routines, practitioners often face a dilemma: either conduct independent tuning searches for each routine overlooking interdependence or pursue a more resource intensive joint search for all routines. This decision is influenced by the computational cost associated with some interdependence analysis techniques in the literature. Our methodology adapts and refines these methods to ensure computational feasibility in real -world scenarios. It leverages a cost-effective interdependence analysis to decide whether to merge several tuning searches into a joint search or conduct orthogonal searches. When tested on synthetic functions with varying levels of parameter interdependence, our methodology efficiently explores the search space. In comparison to Bayesian-optimization-based fully joint searches, it reduces the search time by up to 95%;compared to full -independent searches, it leads to final configurations up to 8% more accurate. When applied to GPU-offloaded RealTime Time-Dependent Density Functional Theory (RT-TDDFT), an application in computational materials science that challenges modern HPC autotuners, our methodology achieved an effective tuning search. Its adaptability and efficiency exiend beyond RT-TDDFT, making it valuable for related applications in HPC.

关键词： autotuning bayesian optimization density functional theory exascale gpu high dimensionality tuning

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Integrating UAV and LoRaWAN in WSN for Intelligent Monitoring in Large-scale Rural Farms

Integrating UAV and LoRaWAN in WSN for Intelligent Monitorin...

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2023 IEEE international Conference on Pervasive computing and Communications workshops and other Affiliated Events, PerCom workshops 2023

作者： Tao, Xu Silvestri, Simone University of Kentucky Department of Computer Science United States

ISBN: (纸本)9781665453813

With the growth of challenges to crop productivity caused by climate changes, high-performance, and sustainable farming techniques are essential to satisfy the growing worldwide food demands. However, today's farming modes still extensively rely on farmers for monitoring crop growth status and making decisions on management strategies, leaving it far behind the desired intelligence and automaticity. This paper proposes a decentralized architecture to enable energy-efficient solutions for intelligent crop monitoring in large-scale rural farms. We employ Unmanned aerial vehicle (UAV) as data mules for data collection with data inference techniques in Wireless Sensor Network (WSN). We then facilitate Bluetooth Low Energy (BLE) and LoRaWAN technologies to provide hierarchical edge-fog-cloud network infrastructure, enabling seamless communications among ground sensors, UAVs, fog-layer computational devices, and cloud servers. © 2023 IEEE.

关键词： Wireless sensor networks

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TaPaSCo-AIE: An Open-Source Framework for Streaming-based Heterogeneous Acceleration using AMD AI Engines

TaPaSCo-AIE: An Open-Source Framework for Streaming-based He...

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1st international Conference on Smart Energy Systems and Artificial Intelligence (SESAI)

作者： Heinz, Carsten Kalkhof, Torben Lavan, Yannick Koch, Andreas Tech Univ Darmstadt Embedded Syst & Applicat Grp Darmstadt Germany

ISBN: (纸本)9798350364613;9798350364606

AMD AI Engines (AIEs) extend the design space and open up new options for coarse -grained processing in re-configurable accelerators. Pure FPGA designs for machine learning often struggle to compete with the high clock frequencies of GPUs for data -intensive workloads with only limited control flow. Having AIEs available on-chip with an FPGA fabric allows for low -latency co -processing and permits parts of an application to be placed on the most suitable kind of processing unit. Many data -heavy workloads, particularly in the AI domain, benefit from data streaming. With TaPaSCo-AIE, we present a framework for heterogeneous systems centered around data streams. Our framework focuses on AMD Versal devices and incorporates AI Engines and 100G network. We demonstrate the efficient use of TaPaSCo-AIE in a real -world evaluation based on a neural network, and achieve significant performance improvements over CPUs, and even exceed the performance of an AIM GPU.

关键词： FPGA Versal AI Engine Heterogeneous computing Network

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Teaching performance Metrics in Parallel computing Courses

Teaching Performance Metrics in Parallel Computing Courses

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IEEE international symposium on Parallel and Distributed Processing workshops and Phd Forum (IPDPSW)

作者： Sandino Vargas-Pérez Department of Computer Science Kalamazoo College Kalamazoo MI USA

ISBN: (数字)9798350364606

ISBN: (纸本)9798350364613

As high-performance computing technologies advance, the significance of parallel programming in various domains is becoming increasingly evident since it allows us to harness the power of heterogeneous computing and solve complex problems more efficiently. However, for students to master this type of computation and be able to apply it in different contexts, it requires understanding how measuring and optimizing parallel code impacts its performance. This paper presents an approach to enhancing students' comprehension of parallel performance metrics through an interactive exercise that complements lectures on parallel performance and improves assessment.

关键词： Measurement Distributed processing Data analysis Parallel programming high performance computing Conferences Education

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RLPS: Reinforcement Learning based Periodic Strategy for 40/100Gbps Energy Efficient Ethernet 22

RLPS: Reinforcement Learning based Periodic Strategy for 40/...

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22nd IEEE international symposium on Parallel and Distributed Processing with Applications, ISPA 2024

作者： Jiang, Wanchun Tian, Zhuang Yao, Renfu Tan, Xunyong Wang, Kai Huang, Jiawei Wang, Jianxin Central South University School of Computer Science and Engineering Changsha China

ISBN: (纸本)9798331509712

The strategy for 40/100Gbps Energy Efficient Ethernet (EEE) determines when to enter and leave the power-saving modes. Accordingly, it directly decides both the energy savings and the incurred latency of frames in the EEE. The performance of the EEE strategy is greatly influenced by the network traffic, and thus existing EEE strategies need either proper parameter configuration under certain traffic loads or parameter adaptation mechanisms based on the traffic prediction under the assumptions of certain distribution. Consequently, these EEE strategies hardly keep consistent high performance under variable traffic in reality. To address this issue, we bring the reinforcement learning method into the design of the EEE strategy and propose the reinforcement learning based periodic strategy (RLPS) in this paper. Specifically, RLPS transmits existing frames at first and then stays in the selected power-saving mode for the rest time in each cycle. Moreover, RLPS learns the time length of each cycle online to reflect the impacts of traffic, instead of directly outputting power-saving mode transition decisions. In this way, the power consumption in each cycle is optimal with the help of learned information, and the overhead of online learning is reduced. Simulations driven by both synthetic traffic and real traces confirm that RLPS outperforms existing strategies, i.e., can achieve consistent high performance regardless of the traffic loads and distributions. © 2024 IEEE.

关键词： Energy saving

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BitMoD: Bit-serial Mixture-of-Datatype LLM Acceleration 31

BitMoD: Bit-serial Mixture-of-Datatype LLM Acceleration

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31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Chen, Yuzong Abouelhamayed, Ahmed F. Dai, Xilai Wang, Yang Andronic, Marta Constantinides, George A. Abdelfattah, Mohamed S. Cornell University Computer Systems Lab United States Systems and Networking Research Group Microsoft Research United States Imperial College London Department of Electrical and Electronic Engineering United Kingdom

ISBN: (纸本)9798331506476

Large language models (LLMs) have demonstrated remarkable performance across various machine learning tasks. Yet the substantial memory footprint of LLMs significantly hinders their deployment. In this paper, we improve the accessibility of LLMs through BitMoD1, an algorithm-hardware co-design solution that enables efficient LLM acceleration at low weight precision. On the algorithm side, BitMoD introduces fine-grained data type adaptation that uses a different numerical data type to quantize a group of (e.g., 128) weights. Through the careful design of these new data types, BitMoD is able to quantize LLM weights to very low precision (e.g., 4 bits and 3 bits) while maintaining high accuracy. On the hardware side, BitMoD employs a bitserial processing element to easily support multiple numerical precisions and data types;our hardware design includes two key innovations: First, it employs a unified representation to process different weight data types, thus reducing the hardware cost. Second, it adopts a bit-serial dequantization unit to rescale the per-group partial sum with minimal hardware overhead. Our evaluation on six representative LLMs demonstrates that BitMoD significantly outperforms state-of-the-art LLM quantization and acceleration methods. For discriminative tasks, BitMoD can quantize LLM weights to 4 -bit with © 2025 IEEE.

关键词： Integrated circuit design

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Output Manipulation via LoRA for Generative AI 23

Output Manipulation via LoRA for Generative AI

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23rd international symposium INFOTEH-JAHORINA (INFOTEH)

作者： Culafic, Igor Scekic, Zoja Dejan, Babic Popovic, Tomo Jovovic, Ivan Univ Donja Gorica Fac Appl Sci Podgorica Montenegro Univ Donja Gorica Fac Informat Syst & Technol Podgorica Montenegro

ISBN: (纸本)9798350329940;9798350307368

Generative Artificial Intelligence has witnessed a surge in popularity in recent years, characterized by the emergence of groundbreaking models like DALL-E 2, Midjourney, and Stable Diffusion, which have spearheaded advancements in this technological domain. This research aims to harness the potential of Stable Diffusion and its extensions for the purpose of training a LoRA (Low-Rank Adaptation) model to generate images that closely resemble the original subject matter, utilizing a predetermined amount of example data. The primary objective of this research is to demonstrate the prowess of Stable Diffusion and generative AI in a broader context, delving into the possibilities offered by open-source frameworks, highlighting the challenges associated with poorly organized training data and the advantages of properly organized and edited datasets, conducting a comparative analysis of diverse diffusion models and examining various LoRA strength examples. This research also aims to compare the results from larger training parameters on both small and relatively large training models for the purpose of determining if overfitting, over training on one specific subject, is more prevalent with smaller or larger datasets.

关键词： generative artificial Intelligence computer vision LoRA stable diffusion

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Teaching high-performance computing in Developing Countries: A Case Study in Mexican Universities 36

Teaching High-Performance Computing in Developing Countries:...

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36th IEEE international Parallel and Distributed Processing symposium (IEEE IPDPS)

作者： Antonio Trejo-Sanchez, Joel Javier Hernandez-Lopez, Francisco Uh Zapata, Miguel Angel Luis Lopez-Martinez, Jose Fajardo-Delgado, Daniel Cesar Ramirez-Pacheco, Julio CONACYT Ctr Invest Matemat AC Dept Comp Sci Merida Mexico Univ Autonoma Yucatan Dept Comp Sci Merida Mexico Tecnol Nacl Mexico Dept Syst & Computat Ciudad Guzman Mexico Univ Quintana Roo Dept Engn Cancun Mexico

ISBN: (纸本)9781665497473

Teaching high-performance computing (HPC) to undergraduate programs represents a significant challenge in most universities in developing countries like Mexico. Deficiencies in the required infrastructure and equipment, inadequate curricula in computer engineering programs (and resistance to change them), students' lack of interest, motivation, or knowledge of this area are the main difficulties to overcome. The COVID-19 pandemic represents an additional challenge to these difficulties in teaching HPC in these programs. Despite the detriments, some strategies have been developed to incorporate the HPC concepts to Mexican students without necessarily modifying the traditional curricula. This paper presents a case study over four public universities in Mexico based on our experience as instructors. We also propose a course that introduces the HPC principles considering the heterogeneous background of the students in such universities. The results are about the number of students enrolling in related classes and participating in extra-curricular projects.

关键词： high-performance computing undergraduate program curricula parallel computing

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Q2Logic: A Coarse-Grained FPGA Overlay targeting Schrödinger Quantum Circuit Simulations

Q2Logic: A Coarse-Grained FPGA Overlay targeting Schrödinge...

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2023 IEEE international Parallel and Distributed Processing symposium workshops, IPDPSW 2023

作者： Podobas, Artur KTH Royal Institute of Technology School of Electrical Engineering and Computer Science Stockholm Sweden

ISBN: (纸本)9798350311990

Quantum computing is emerging as an important (but radical) technology that might take us beyond Moore's law for certain applications. Today, in parallel with improving quantum computers, computer scientists are relying heavily on quantum circuit simulators to develop algorithms. Most existing quantum circuit simulators run on general-purpose CPUs or GPUs. However, at the same time, quantum circuits themselves offer multiple opportunities for parallelization, some of which could map better to other architecture- architectures such as reconfigurable systems. In this early work, we created a quantum circuit simulator system called Q2Logic. Q2Logic is a coarse-grained reconfigurable architecture (CGRA) implemented as an overlay on Field-Programmable Gate Arrays (FPGAs), but specialized towards quantum simulations. We described how Q2Logic has been created and reveal implementation details, limitations, and opportunities. We end the study by empirically comparing the performance of Q2Logic (running on a Intel Agilex FPGA) against the state-of-the-art framework SVSim (running on a modern processor), showing improvements in three large circuits(#qbit≥27), where Q2Logic can be up-to 7x faster. © 2023 IEEE.

关键词： Circuit simulation

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COMPASS: SRAM-Based computing-in-Memory SNN Accelerator with Adaptive Spike Speculation 57

COMPASS: SRAM-Based Computing-in-Memory SNN Accelerator with...

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57th Annual IEEE/ACM international symposium on Microarchitecture, MICRO 2024

作者： Wang, Zongwu Liu, Fangxin Yang, Ning Huang, Shiyuan Li, Haomin Jiang, Li Shanghai Jiao Tong University Department of Computer Science and Engineering China Shanghai Qi Zhi Institute China AI Institute Shanghai Jiao Tong University MoE Key Lab of Artificial Intelligence China

ISBN: (纸本)9798350350579

Brain-inspired spiking neural networks (SNNs) are considered energy-efficient alternatives to conventional deep neural networks (DNNs). By adopting event-driven information processing, SNNs can significantly reduce the computational demands associated with DNNs, while still achieving comparable performance. However, current SNNs primarily prioritize high accuracy by constructing complex neuron models that generate sparse spikes. Unfortunately, this approach results in low energy efficiency and high latency, posing a significant challenge for deploying SNNs at the edge. Furthermore, the dominant computation in SNNs, which involves spike-wise Accumulate-Compare operations, is well-suited for computing-in-Memory (CIM) architectures. However, exploiting high parallel processing and spike sparsity in CIM-based SNN accelerators is challenging due to the irregularity and time dependency of spikes. To address these limitations, the paper proposes COMPASS, a SRAM-based CIM architecture for efficient SNNs. We first introduce an efficient method to exploit irregular sparsity for both input spikes (explicit) and output spikes (implicit). This is achieved through a speculation mechanism that exploit dynamic spike patterns, enabling lean hardware for sparsity utilization. Additionally, the CIM architecture is carefully modified to facilitate dynamic spike pattern generation and exploitation with minimal overhead. Moreover, we design an adaptive dataflow with temporal spike representation tailored for input/output spikes, reducing memory footprint and enabling parallel execution. Comprehensive evaluation results demonstrate that COMPASS can achieve 26.7x end-to-end speedup over recent SNN accelerators hardware implementation with up to 386.7x less energy per inference. © 2024 IEEE.

关键词： Compasses (magnetic)

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