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检索条件"任意字段=2024 International Symposium on Computer Architecture and High Performance Computing Workshops"

共 5226 条记录，以下是41-50 订阅

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Leveraging Hybrid Classical-Quantum Methods for Efficient Load Rebalancing in HPC

Leveraging Hybrid Classical-Quantum Methods for Efficient Lo...

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2024 workshops of the international Conference for high performance computing, Networking, Storage and Analysis, SC workshops 2024

作者： Zawalska, Justyna Chung, Minh Rycerz, Katarzyna Schulz, Laura Schulz, Martin Kranzlmuller, Dieter AGH University of Krakow Institute of Computer Science Krakow Poland CYFRONET AGH Academic Computer Center Krakow Poland Garching bei München Germany Chair for Computer Architecture and Parallel Systems Germany MNM-Team Germany

ISBN: (纸本)9798350355543

Load imbalance is a challenge for parallel applications in high performance computing (HPC). It is caused by processes having different execution times or load values, leading to idle or wait times at synchronization points, where faster processes must wait for the slowest process to catch up. To mitigate this issue, applications can employ load balancing (LB) strategies, which migrate load between processes to even out load. This is often referred to as the Load Rebalancing Problem (LRP). While many approaches solving the LRP exist, they can only be heuristics and hence further optimization potential exists. In our work, we turn to a novel approach by using hybrid classical-quantum approaches and present two versions of the constrained quadratic model for solving the LRP;the two differ in how they balance the number of qubits required with the types of applied constraints. We compare the quantum-based methods with classical methods using heuristic algorithms Greedy, Karmarkar-Karp, and ProactLB. We evaluate our approaches using imbalance ratio and speedup as metrics, as well as the number of migrated tasks to indicate overhead caused by migrations. Our results show that the quantum-based methods outperform the classic methods. For example, we need only 1/4 of the number of migrated tasks in a realistic use case compared with classical methods, particularly Greedy and KK, to balance the load. © 2024 IEEE.

关键词： CQM HPC HPCQC integration Load Rebalancing Quantum computing task migration

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Proceeding - 2024 ACM/IEEE 51st Annual international symposium on computer architecture, ISCA 2024

Proceeding - 2024 ACM/IEEE 51st Annual International Symposi...

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51st ACM/IEEE Annual international symposium on computer architecture, ISCA 2024

ISBN: (纸本)9798350326581

The proceedings contain 87 papers. The topics discussed include: a SAT scalpel for lattice surgery: representation and synthesis of subroutines for surface-code fault-tolerant quantum computing;circular reconfigurable parallel processor for edge computing;MegIS: high-performance, energy-efficient, and low-cost metagenomic analysis with in-storage processing;TCP: a tensor contraction processor for AI workloads;DyLeCT: achieving huge-page-like translation performance for hardware-compressed memory;ElasticRec: a microservice-based model serving architecture enabling elastic resource scaling for recommendation models;waferscale network switches;Triangel: a high-performance, accurate, timely on-chip temporal prefetcher;compiler-directed whole-system persistence;and the dataflow abstract machine simulator framework.

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Top-Down Microarchitecture Analysis Approximation Based on performance Counter architecture for SiFive RISC-V Processors

Top-Down Microarchitecture Analysis Approximation Based on P...

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2024 workshops of the international Conference for high performance computing, Networking, Storage and Analysis, SC workshops 2024

作者： Mou, Chan-Yu Hsiao, Chao-Chieh Chou, Jerry National Tsing Hua University Software Performance Analysis SiFive Inc. Department of Computer Science Hsinchu Taiwan Software Performance Analysis SiFive Inc. Hsinchu Taiwan National Tsing Hua University Department of Computer Science Hsinchu Taiwan

ISBN: (纸本)9798350355543

Modern Out-of-Order RISC-V CPUs have complex mechanisms, making microarchitecture-level performance analysis challenging. Despite increasing performance Monitoring Units (PMUs), interpreting this data requires deep architectural knowledge. This paper introduces a Top-down Microarchitecture Analysis (TMA) approximation to analyze application performance on RISC-V CPUs. TMA classifies performance issues into four categories by calculating metrics that reflect their proportions using predefined formulas and PMU events. We present the results of applying this method to analyze SPEC CPU2006 benchmarks on a SiFive RISC-V processor. This work is an initial step in analyzing RISC-V CPUs using TMA Level 1. The contributions of this research are threefold: (1) designing and implementing TMA for a RISC-V CPU with clear metric definitions;(2) proposing test cases and methods to verify TMA metrics and PMU implementation;(3) enabling software developers to profile workloads without requiring extensive microarchitecture knowledge. © 2024 IEEE.

关键词： CPU Microarchitecture performance analysis RISC-V Top-Down Analysis

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Ponte Vecchio Across the Atlantic: Single-Node Benchmarking of Two Intel GPU Systems

Ponte Vecchio Across the Atlantic: Single-Node Benchmarking ...

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2024 workshops of the international Conference for high performance computing, Networking, Storage and Analysis, SC workshops 2024

作者： Applencourt, Thomas Sadawarte, Aditya Muralidharan, Servesh Bertoni, Colleen Kwack, JaeHyuk Luo, Ye Rangel, Esteban Tramm, John Ghadar, Yasaman Tamerus, Arjen Edsall, Chris Deakin, Tom Argonne National Laboratory Argonne Leadership Computing Facility LemontIL United States University of Bristol School of Computer Science Bristol United Kingdom University of Cambridge Cambridge United Kingdom

ISBN: (纸本)9798350355543

Intel Data Center GPU Max 1550, known as Ponte Vecchio (PVC), is a new Intel GPU architecture for high-performance computing. It is the basis of two systems on the June 2024 Top 500 list, Dawn (#51) and Aurora (#2).This work provides micro-benchmarking data on PVCs from which application developers may benefit, shows how the micro-benchmarking results are indicative of mini-app performance on PVC, and demonstrates real applications on large-scale Intel GPU *** quantify the obtainable performance from PVC systems through micro-benchmarking fundamental architectural properties. We evaluate the performance of four mini-apps with known performance characteristics, and two full applications, comparing performance on a node of Aurora and Dawn with a node of NVIDIA H100 GPUs and a node of AMD MI250 GPUs. We show the figure-of-merit of the mini-apps on a single PVC ranges from 0.6-1.8X the performance of an H100, and 0.8-7.5X of a MI250. © 2024 IEEE.

关键词： pvc

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HotTiles: Accelerating SpMM with Heterogeneous Accelerator architectures 30

HotTiles: Accelerating SpMM with Heterogeneous Accelerator A...

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30th IEEE international symposium on high-performance computer architecture (HPCA)

作者： Gerogiannis, Gerasimos Aananthakrishnan, Sriram Torrellas, Josep Hur, Ibrahim Intel Corp Santa Clara CA 95051 USA Univ Illinois Urbana IL 61801 USA

ISBN: (纸本)9798350393132;9798350393149

Sparse Matrix Dense Matrix Multiplication (SpMM) is an important kernel with application across a wide range of domains, including machine learning and linear algebra solvers. In many sparse matrices, the pattern of nonzeros is nonuniform: nonzeros form dense and sparse regions, rather than being uniformly distributed across the whole matrix. We refer to this property as Intra-Matrix Heterogeneity (IMH). Currently, SpMM accelerator designs do not leverage this heterogeneity. They employ the same processing elements (PEs) for all the regions of a sparse matrix, resulting in suboptimal acceleration. To address this limitation, we utilize heterogeneous SpMM accelerator architectures, which include different types of PEs to exploit IMH. We develop an analytical modeling framework to predict the performance of different types of accelerator PEs taking into account IMH. Furthermore, we present a heuristic for partitioning sparse matrices among heterogeneous PEs. We call our matrix modeling and partitioning method HotTiles. To evaluate HotTiles, we simulate three different heterogeneous architectures. Each one consists of two types of workers (i.e., PEs): one suited for compute-bound denser regions (Hot Worker) and one for memory-bound sparser regions (Cold Worker). Our results show that exploiting IMH with HotTiles is very effective. Depending on the architecture, heterogeneous execution with HotTiles outperforms homogeneous execution using only hot or only cold workers by 9.2-16.8x and 1.4-3.7x, respectively. In addition, HotTiles outperforms the best worker type used on a per-matrix basis by 1.3-2.5x. Finally, HotTiles outperforms an IMH-unaware heterogeneous execution strategy by 1.4-2.2x.

关键词： hardware accelerators heterogeneous computing sparse computations SpMM

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Comparing Control Schemas in Isometric Balanced-based Controllers

Comparing Control Schemas in Isometric Balanced-based Contro...

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2024 international symposium on Mixed and Augmented Reality-ISMAR-Annual

作者： Nelson, Michael G. Mousas, Christos Purdue Univ Dept Comp Graph Technol W Lafayette IN 47907 USA

ISBN: (纸本)9798331506926;9798331506919

Body-directed inputs allow users to utilize a transfer function mapped to shifts in the center of mass to control navigation in virtual reality. Researchers have evaluated various devices but have not assessed methods for controlling them. With this study, we aim to investigate factors contributing to control schemas in balance-based controllers. We developed four experimental conditions assigned to the transfer function mapping following a 2 (orientation: turning vs. no-turning) x 2 (acceleration: gradual vs. instantaneous) within-group study design. For our study, we collected data from 25 study participants to explore how the orientation and acceleration factors could impact participants' performance, accuracy, system usability, task load, and symptoms of motion sickness. Our data revealed that 1) orientation of the transfer function impacted performance, 2) acceleration impacted accuracy, 3) orientation impacted task load, 4) both orientation and acceleration individually impacted system usability, and 5) orientation impacted symptoms of motion sickness.

关键词： Human-centered computing-Human computer interaction (HCI)-Interaction paradigms-Virtual reality Human-centered computing-Human computer interaction (HCI)-Interaction devices-Graphics input devices

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Proceedings - 2024 IEEE international symposium on high-performance computer architecture, HPCA 2024

Proceedings - 2024 IEEE International Symposium on High-Perf...

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30th IEEE international symposium on high-performance computer architecture, HPCA 2024

ISBN: (纸本)9798350393132

The proceedings contain 78 papers. The topics discussed include: exploitation of security vulnerability on retirement;GadgetSpinner: a new transient execution primitive using the loop stream detector;uncovering and exploiting AMD speculative memory access predictors for fun and profit;Revet: a language and compiler for dataflow threads;an optimizing framework on MLIR for efficient FPGA-based accelerator generation;Celeritas: out-of-core based unsupervised graph neural network via cross-layer computing 2024;MEGA: a memory-efficient GNN accelerator exploiting degree-aware mixed-precision quantization;Gemini: mapping and architecture co-exploration for large-scale DNN Chiplet accelerators;STELLAR: energy-efficient and low-latency SNN algorithm and hardware co-design with spatiotemporal computation;and MIMDRAM: an end-to-end processing-using-DRAM system for high-throughput, energy-efficient and programmer-transparent multiple-instruction multiple-data computing.

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Acceleration of Graph Neural Networks with Heterogenous Accelerators architecture

Acceleration of Graph Neural Networks with Heterogenous Acce...

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2024 workshops of the international Conference for high performance computing, Networking, Storage and Analysis, SC workshops 2024

作者： Cao, Kaiwen Gajjar, Archit Gerstman, Liad Wu, Kun Chalamalasetti, Sai Rahul Dhakal, Aditya Pedretti, Giacomo Prakash, Pavana Hwu, Wen-Mei Chen, Deming Milojicic, Dejan Hewlett Packard Labs United States Technion-Israel Institute of Technology Israel D-Matrix United States University of Illinois Urbana-Champaign United States Nvidia United States

ISBN: (纸本)9798350355543

Graph Neural Networks (GNNs) have been used to solve complex problems of drug discovery, social media analysis, etc. Meanwhile, GPUs are becoming dominating accelerators to improve deep neural network performance. However, due to the characteristics of graph data, it is challenging to accelerate GNN-type workloads with GPUs alone. GraphSAGE is one representative GNN workload that uses sampling to improve GNN learning efficiency. Profiling the GraphSAGE using PyG library reveals that the sampling stage on the CPU is the bottleneck. Hence, we propose a heterogeneous system architecture solution with the sampling algorithm accelerated on customizable accelerators (FPGA), and feed sampled data into GPU training through a PCIe Peer-to-Peer (P2P) communication flow. With FPGA acceleration, for the sampling stage alone, we achieve a speed-up of 2.38× to 8.55× compared with sampling on CPU. For end-to-end latency, compared with the traditional flow, we achieve a speed-up of 1.24× to 1.99 ×. © 2024 IEEE.

关键词： Field Programmable Gate Array (FPGA) Graph Neural Network (GNN) Graphics Processing Unit (GPU) high-Level Synthesis (HLS) Peer-to-Peer (P2P)

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Exploring the Serverless First Strategy in Cloud Application Development 35

Exploring the Serverless First Strategy in Cloud Application...

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35th IEEE international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Cavalheiro, Adriano Prado Schepke, Claudio Fed Univ Pampa Alegrete PPGES Grad Program Software Engn Alegrete Brazil

ISBN: (纸本)9798350381603

This paper explores the Serverless First strategy in cloud application development. Serverless computing has gained popularity due to its flexibility and scalability. In our work, we provide a systematic review of the literature about the Serverless paradigm in cloud computing and an evaluation of the advantages of this approach by performing a comparative analysis among three ways for the implementation of an application: AWS Lambda, AWS Lambda with Chalice framework, and the traditional form using the Flask framework. The literature review results show the gains in scaling, cost reduction, and ease of maintenance achieved with the Serverless First strategy. However, some limitations and challenges were also highlighted, such as the greater complexity of the environment, less control over resources, resource limitations imposed by the cloud provider, and difficulties in debugging and managing the infrastructure. The case study demonstrates in practice that the Chalice framework provided the most straightforward and rapid implementation, the AWS Lambda without Chalice offered greater flexibility and control, and the Flask version allowed local testing and total control but required more manual setup and lacked automatic scalability.

关键词： Serverless First Function as a Service Serverless computing Serverless architecture Serverless Applications Software Development Cloud computing Cloud Services

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Predicting Protein Folding on Intel's Data Center GPU Max Series architecture (PVC)

Predicting Protein Folding on Intel's Data Center GPU Max Se...

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2024 workshops of the international Conference for high performance computing, Networking, Storage and Analysis, SC workshops 2024

作者： Ruhela, Dhani Prasanna, Madhavan Saxena, Aaditya Westwood High School AustinTX United States Purdue University College of Science West LafayetteIN United States Bob Jones High School MadisonAL United States

ISBN: (纸本)9798350355543

Predicting the structure and interactions of proteins and other life molecules has been a grand challenge for over 60 years. Google's DeepMind AI team leveraged Artificial intelligence (AI) in 2020 to develop AlphaFold and achieved an accuracy above 90 for two-thirds of the proteins in CASP's global distance test (GDT). AlphaFold has been very successful in biology and medicine. However, a lack of training code and expansive computational requirements created an open-source implementation named OpenFold. OpenFold is fast, memory-efficient, and provides an OpenProtein dataset with five million MSAs. MLCommons added OpenFold to their HPC benchmarks suite in 2023 and was evaluated by four institutions on NVIDIA GPU architectures. This work presents our endeavours to port, run and tune OpenFold on Intel's GPU Max Series Ponte Vecchio (PVC). To the best of our knowledge, this is the first large-scale study of the distributed implementation of OpenFold application with Intel PVC GPU, presenting the challenges, opportunities and performance of the application on Intel's Max series architecture. © 2024 IEEE.

关键词： HPC Intel OneAPI OpenFold Petascale PyTorch

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