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AFS: Accurate, Fast, and Scalable Error-Decoding for Fault-Tolerant Quantum computers 28

AFS: Accurate, Fast, and Scalable Error-Decoding for Fault-T...

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28th Annual IEEE international symposium on high-performance computer architecture (HPCA)

作者： Das, Poulami Pattison, Christopher A. Manne, Srilatha Carmean, Douglas M. Svore, Krysta M. Qureshi, Moinuddin Delfosse, Nicolas Georgia Inst Technol Atlanta GA 30332 USA CALTECH Pasadena CA 91125 USA Microsoft Quantum Redmond WA USA Microsoft Res Redmond WA USA

ISBN: (纸本)9781665420273

Quantum computers promise computational advantages for many important problems across various application domains. Unfortunately, physical quantum devices are highly susceptible to errors that limit us from running most of these quantum applications. Quantum Error Correction (QEC) codes are required to implement Fault-Tolerant Quantum computers (FTQC) on which computations can be performed without encountering errors. Error decoding is a critical component of quantum error correction and is responsible for transforming a set of qubit measurements generated by the QEC code, called the syndrome, into error locations and error types. For the feasibility of implementation, error decoders must not only identify errors with high accuracy, but also be fast and scalable to a large number of qubits. Unfortunately, most of the prior works on error decoding have focused primarily only on the accuracy and have relied on software implementations that are too slow to be of practical use. Furthermore, these studies only look at designing a single decoder and do not analyze the challenges involved in scaling the storage and bandwidth requirements when performing error correction in large systems with thousands of qubits. In this paper, we present AFS, an accurate, fast, and scalable decoder architecture that is designed to operate in the context of systems with hundreds of logical qubits. We present the hardware implementation of AFS, which is based on the Union Find decoding algorithm and employs a three-stage pipelined design. AFS provides orders of magnitude higher accuracy compared to recent SFQ-based hardware decoders (logical error rate of 6 x 10(-10) for physical error rate of 10(-3)) and low decoding latency (42ns on average), while being robust to measurement errors introduced while extracting syndromes during the QEC cycles. We also reduce the amount of decoding hardware required to perform QEC simultaneously on all the logical qubits by co-designing the micro-architectur

关键词： Quantum computing Quantum error correction Fault-tolerant quantum computing Decoding Union-Find decoding Surface codes

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EMPI: Enhanced Message Passing Interface in Modern C++ 23

EMPI: Enhanced Message Passing Interface in Modern C++

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23rd IEEE/ACM international symposium on Cluster, Cloud and Internet computing, CCGrid 2023

作者： Beni, Majid Salimi Crisci, Luigi Cosenza, Biagio University of Salerno Department of Computer Science Salerno Italy

ISBN: (纸本)9798350301199

Message Passing Interface (MPI) is a well-known standard for programming distributed and HPC systems. While the community has been continuously improving MPI to address the requirements of next-generation architectures and applications, its interface has not substantially evolved. In fact, MPI only provides an interface to C and Fortran and does not support recent features of modern C++. Moreover, MPI programs are error-prone and subject to different syntactic and semantic errors. This paper introduces EMPI, an Enhanced Message Passing Interface based on modern C++, which is directly mapped to the OpenMPI implementation and exploits modern C++ for safe and efficient distributed programming. EMPI proposes novel C++RAII-based semantics and constant specialization to prevent error-prone code patterns such as parameter mismatch, and reduce the overhead of handling multiple objects and perinvocation time. Consequently, EMPI programs are safer: six out of nine well-known MPI error patterns do not occur while correctly using EMPI semantics. Experimental results on five microbenchmarks and two applications on a large-scale cluster using up to 1024 processes show that EMPI's performance is very similar to native MPI and considerably faster than the MPL C++ interface. © 2023 IEEE.

关键词： Message passing

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DCT Implementation on a Custom FPGA RISC-V Processor 65

DCT Implementation on a Custom FPGA RISC-V Processor

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65th international symposium ELMAR, ELMAR 2023

作者： Harmina, Tomislav Hofman, Daniel Benjak, Jakov University of Zagreb Faculty of Electrical Engineering and Computing Zagreb Croatia

ISBN: (纸本)9798350325126

This paper presents our implementation of an Out-of-Order RISC-V core design. The increasing relevance of open-standard computer architectures and corresponding tools makes the development of custom hardware an increasingly attractive alternative to off-the-shelf components. RISC-V is such an open Instruction Set architecture (ISA) that has become widely used in recent years, especially in low-cost microcontrollers, but also in high-performance computing in recent years. Here we showcase a custom-developed core capable of executing the Discrete Cosine Transform algorithm which gives the core potential uses in image and video processing. Problems with developing such a core are presented and future possibilities and improvements are discussed. © 2023 IEEE.

关键词： computer architecture

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Poster: Fine-Grained CUDA Call Interception for GPU Virtualization 25

Poster: Fine-Grained CUDA Call Interception for GPU Virtuali...

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25th ACM international Middleware Conference Demos, Posters and Doctoral symposium, MIDDLEWARE 2024

作者： Pavlidakis, Manos Argyros, Anargyros Mavridis, Stelios Vasiliadis, Giorgos Bilas, Angelos Greece Computer Science Department University of Crete Greece Department of Management Science & Technology Hellenic Mediterranean University Greece

ISBN: (纸本)9798400713545

GPUs are often underutilized due to applications’ inability to fully exploit resources. Existing API remoting techniques for GPU virtualization are fragile, requiring interception of over 2,000 complex, rapidly evolving CUDA calls. This paper introduces CUInterposer, a streamlined mechanism operating at the CUDA runtime and driver level, reducing interception complexity to 400 simple calls, enhancing robustness and maintainability in GPU virtualization. © 2024 Copyright held by the owner/author(s).

关键词： Program processors

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OpenMDS: An Open-Source Shell Generation Framework for high-performance Design on Multi-Die FPGAs 30

OpenMDS: An Open-Source Shell Generation Framework for High-...

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IEEE 30th international symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Shin, Gyeongcheol Kim, Junsoo Kim, Joo-Young Korea Adv Inst Sci & Technol Sch Elect Engn Daegeon South Korea

ISBN: (纸本)9781665483322

FPGA is a promising platform in designing a hardware accelerator due to its design flexibility and fast development cycle, despite the device's limited hardware resources. To address this, latest FPGAs have adopted a multi-die architecture providing abundant hardware resources with high yield and cost-benefit. However, the multi-die architecture causes critical timing issues when signal paths cross the die-to-die boundaries, adding another design challenge in using FPGA. We propose OpenMDS, an open-source shell generation framework for high-performance design on multi-die FPGAs. Based on the user's design requirements, it generates an optimized shell for the target FPGA via automated bus pipelining, customized floorplanning, and scalable clocking scheme.

关键词： computer architecture Timing Field programmable gate arrays Open source software Hardware acceleration Pipeline processing

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Leveraging Packet Cloning to Achieve Fast Flow-Transmission for Data Center Load Balancing 22

Leveraging Packet Cloning to Achieve Fast Flow-Transmission ...

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22nd IEEE international symposium on Parallel and Distributed Processing with Applications, ISPA 2024

作者： Wang, Yuchen Li, Zhenbo Jing, Haotian Zhang, Tao Zou, Shaojun Luan, Xidao Yin, Hui Li, Fangmin Changsha University School of Computer Science and Engineering ChangSha410022 China Hunan Province Key Laboratory of Industrial Internet Technology and Security ChangSha410022 China Hainan University School of Computer Science and Technology Haikou570228 China

ISBN: (纸本)9798331509712

Modern data center network often possesses multiple end-to-end parallel paths, which undertake the crucial task of transmitting vast heterogeneous data traffic generated by a wide variety of applications. To fully utilize the offered super high bisection network bandwidth thus benefiting application performance, many data center load balancing schemes are proposed to improve path utilization for avoiding network congestion hot-spot. However, these schemes are naturally agnostic to data center traffic pattern and the diverse requirements on flow-transmission, leading to the sub-optimal network transmission performance. To address this issue, this paper presents a new data center load balancing scheme, called PCLB, which selectively generates Clone Packets by considering both flow-transmission phases and path states, thereby helping different types of flows choose more appropriate paths for speeding up their data transmission. Experimental results of numerous NS2 simulations show that PCLB significantly reduces the average and tail flow completion time for delay-sensitive flows, while the performance of throughput-oriented flows can be always maintained at high level. © 2024 IEEE.

关键词： Traffic congestion

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2023 IEEE 35th international symposium on computer architecture and high performance computing (SBAC-PAD)

2023 IEEE 35th International Symposium on Computer Architect...

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international symposium on computer architecture and high performance computing (SBAC-PAD)

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PIMCloud: QoS-Aware Resource Management of Latency-Critical Applications in Clouds with Processing-in-Memory 28

PIMCloud: QoS-Aware Resource Management of Latency-Critical ...

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28th Annual IEEE international symposium on high-performance computer architecture (HPCA)

作者： Chen, Shuang Jiang, Yi Delimitrou, Christina Martinez, Jose F. Cornell Univ Comp Syst Lab Ithaca NY 14850 USA

ISBN: (纸本)9781665420273

The slowdown of Moore's Law, combined with advances in 3D stacking of logic and memory, have pushed architects to revisit the concept of processing-in-memory (PIM) to overcome the memory wall bottleneck. This PIM renaissance finds itself in a very different computing landscape from the one twenty years ago, as more and more computation shifts to the cloud. Most PIM architecture papers still focus on best-effort applications, while PIM's impact on latency-critical cloud applications is not well understood. This paper explores how datacenters can exploit PIM architectures in the context of latency-critical applications. We adopt a general-purpose cloud server with HBM-based, 3D stacked logic+memory modules, and study the impact of PIM on six diverse interactive cloud applications. We reveal the previously neglected opportunity that PIM presents to these services, and show the importance of properly managing PIM-related resources to meet the QoS targets of interactive services and maximize resource efficiency. Then, we present PIMCloud, a QoS-aware resource manager designed for cloud systems with PIM allowing colocation of multiple latency-critical and best-effort applications. We show that PIMCloud efficiently manages PIM resources: it (1) improves effective machine utilization by up to 70% and 85% (average 24% and 33%) under 2-app and 3-app mixes, compared to the best state-of-the-art manager;(2) helps latency-critical applications meet QoS;and (3) adapts to varying load patterns.

关键词： Three-dimensional displays Stacking Quality of service computer architecture Resource management Servers

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Robust Malicious Domain Detection Based on Spatio-Temporal Hypergraph Networks 22

Robust Malicious Domain Detection Based on Spatio-Temporal H...

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22nd IEEE international symposium on Parallel and Distributed Processing with Applications, ISPA 2024

作者： Gong, Liangyi Lv, Kunxian Long, Chun Fu, Hao Wang, Huanran Wan, Wei Yang, Wu Chinese Academy of Sciences Computer Network Information Center Beijing China University of Chinese Academy of Sciences Beijing China Harbin Engineering University School of Computer Science and Technology Heilongjiang China

ISBN: (纸本)9798331509712

Malicious domains serve as significant resources for adversaries to execute cyber attacks and are crucial indicators for detecting network intrusions. In practical scenarios, malicious domains associated with various attacks are intermingled within DNS traffic, leading to variability in the performance of machine learning-based detection methods. To address this challenge, we have collected extensive DNS traffic data spanning 12 months from a real-world large-scale network with 1 million users. From this dataset, we have extracted numerous requested domains, encompassing 267 attacks that exploit malicious domain names. Furthermore, we have observed that the distinct properties of malicious domains associated with different attacks contribute to the fluctuating performance of machine learning-based detection models. Consequently, we have introduced a spatiotemporal hypergraph network model, which establishes high-order relationships among domain properties to enhance the generalization capability and robustness of the detection model. The results of extensive testing experiments demonstrate that our model achieves remarkable performance, with an average precision of 97% and recall of 98%. © 2024 IEEE.

关键词： Network intrusion

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performance and Power: Systematic Evaluation of AI Workloads on Accelerators with CARAML

Performance and Power: Systematic Evaluation of AI Workloads...

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high performance computing, Networking, Storage and Analysis, SC-W: workshops of the international Conference for

作者： Chelsea Maria John Stepan Nassyr Carolin Penke Andreas Herten Jülich Supercomputing Centre Forschungszentrum Jülich Jülich Germany

ISBN: (数字)9798350355543

ISBN: (纸本)9798350355550

The rapid advancement of machine learning (ML) technologies has driven the development of specialized hardware accelerators designed to facilitate more efficient model training. This paper introduces the CARAML benchmark suite, which is employed to assess performance and energy consumption during the training of transformer-based large language models and computer vision models on a range of hardware accelerators, including systems from NVIDIA, AMD, and Graphcore. CARAML provides a compact, automated, extensible, and reproducible framework for assessing the performance and energy of ML workloads across various novel hardware architectures. The design and implementation of CARAML, along with a custom power measurement tool called jpwr, are discussed in detail.

关键词： Training Energy consumption computer vision Computational modeling Energy measurement computer architecture Benchmark testing Energy efficiency Usability Hardware acceleration

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