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Evaluation of QAOA for black-box serializability problem

Evaluation of QAOA for black-box serializability problem

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international symposium on computing and Networking workshops (CANDARW)

作者： Shuma Ohara Kazuhiro Saito Hideyuki Kawashima Keio University Fujisawa Japan KDDI Research Inc Fujimino Saitama Japan

ISBN: (数字)9798331505349

ISBN: (纸本)9798331505356

A database transaction is considered serializable if it can be executed concurrently while maintaining the correctness of the results. A problem known as the black-box serializability problem involves verifying serializability in an environment where the execution context is not visible. Previous research has applied quantum annealing to address this problem. However, this study addresses it using gate-based quantum computers, enabling future applications for large-scale data. In this study, we employ the Quantum Approximate Optimization Algorithm (QAOA), a quantum algorithm that can be implemented on a quantum computer, to address this problem. Our performance evaluation involves using IBM quantum computer to compare the efficiency of QAOA with that of quantum annealing and classical methods.

关键词： computers performance evaluation Quantum computing Annealing Quantum algorithm Closed box Simulated annealing Logic gates Quantum annealing Optimization

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A Hyperdimensional computing architecture with 4.4x Energy Efficiency in 65nm CMOS

A Hyperdimensional Computing Architecture with 4.4x Energy E...

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IEEE international symposium on Circuits and Systems (ISCAS)

作者： Fredrick Angelo R. Galapon Anastacia B. Alvarez Electrical and Electronics Engineering Institute University of the Philippines Diliman

ISBN: (数字)9798350330991

ISBN: (纸本)9798350331004

Hyperdimensional computing (HDC), a brain-inspired computing defined on high-dimensional vectors (or hypervectors), has emerged as a promising energy-efficient approach for solving classifications tasks. Current HDC architectures typically rely on binary dense hypervectors with approximately equal number of 1 and 0 elements. While these provide good classification performance, they may suffer from high energy consumption due to high switching activity, especially with hypervectors whose dimensionality is in the thousands. In this work, we explore the use of binary sparse representations, in which most of the elements are 0s, for a highly energy-efficient HDC architecture. We consider a language classification task as a case study, targeting 65nm CMOS process. Our results show a remarkable 4.4x reduction in energy and 3.68% reduction in area at iso-performance as compared to when using dense representations. Furthermore, increasing the sparsity in the architecture leads to increased classification accuracy and energy efficiency.

关键词： Energy consumption Codes Sparse approximation Circuits and systems Energy conservation computer architecture Switches

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A NUMA-aware Graph Database for Hybrid Memory System 21

A NUMA-aware Graph Database for Hybrid Memory System

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21st IEEE international symposium on Parallel and Distributed Processing with Applications, 13th IEEE international Conference on Big Data and Cloud computing, 16th IEEE international Conference on Social computing and Networking and 13th international Conference on Sustainable computing and Communications, ISPA/BDCloud/SocialCom/SustainCom 2023

作者： Tan, Shaoheng Liu, Chang Li, Dingding Tang, Yong Zeng, Deze South China Normal University School of Computer Science Guangdong Guangzhou510631 China China University of Geosciences School of Computer Science Hubei Wuhan430074 China

ISBN: (纸本)9798350329223

Compared to traditional relational databases (RDBMS), specialized graph databases (GDBs) can efficiently store and process graph data in both time and space. Hence, domains like social networks often use GDBs for data management, such as representing friendships. Optane DC Persistent Memory Module (DCPMM) is a novel memory device combining byte-addressability, non-volatility, high density and superior performance. Intuitively, applying GDB on DCPMM with the Non-Uniform Memory Access (NUMA) architecture may improve I/O performance, yet the real performance may be unstable due to stacked hardware characteristics. Specifically, DCPMM exhibits serious NUMA effects and unexpected read/write asymmetry compared to DRAM. To tackle these issues, we propose a NUMA-aware graph database called NAPGDB. NAPGDB employs delegated thread pools to improve the latency of accessing remote nodes. Additionally, it categorizes read/write requests into short-running and long-running tasks, with the former being served synchronously instead of using delegated threads to improve CPU utilization. We implement NAPGDB and the experimental results show that NAPGDB can improve the remote throughput by 1.3x-1.7x compared with the multithreaded Redis with RedisGraph. © 2023 IEEE.

关键词： Graph Databases

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Modeling Clinical Symptoms of Cognitive Decline in Neurodegenerative Disease as Faulty computing

Modeling Clinical Symptoms of Cognitive Decline in Neurodege...

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Information Theory workshops (ISIT-W), IEEE international symposium on

作者： Anant Naik Paul M. Arnold Lav R. Varshney University of Illinois Urbana-Champaign

ISBN: (数字)9798350348446

ISBN: (纸本)9798350348453

Neurodegenerative diseases can be classified into three broad categories. Demyelinating diseases (including MS or ADEM), diseases of neuronal dysfunction (including early-stage Alzheimer's and mild cognitive impairment), and diseases of neuronal death (including Alzheimer's disease, Huntington's Disease, and many others). In each of these conditions, cognitive decline is a key feature of the progression of the illness. In this study, we present a novel method to model cognitive decline as the performance of an arbitrary neural network designed to execute a classification task, tested for robustness in a node and edge deletion trial. Edge deletion modeled demyelination, node deletion modeled the death of the neuron, and general neuronal dysfunction was modeled with additive noise. Network performance rapidly declined by the deletion of more nodes and edges, with more robustness to edge deletion than node deletion. Networks with larger hidden nodes and edges in the predefined architecture were found to be more resistant to performance decline than smaller networks. The addition of noise also precipitated a decline in performance but this decline was more gradual than with node and edge deletion. These experiments were compared to models of cognitive dysfunction from clinical data in the literature and found to contain similar profiles.

关键词： Resistance Computational modeling Conferences Neurons computer architecture Robustness Data models

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Characterizing the Impact of Job Execution on the Occurrence of Memory Failures on a Petascale HPC System

Characterizing the Impact of Job Execution on the Occurrence...

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international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Scott Levy Josh Hemmert Kurt B. Ferreira Kevin Pedretti Center for Computing Research Sandia National Laboratories Albuquerque NM USA

ISBN: (数字)9798350356168

ISBN: (纸本)9798350356175

Characterizing the reliability of current and recent high performance (HPC) systems is critical for forecasting how future systems may behave and informing the design of fault tolerance mechanisms. Although research has been conducted to understand memory failures, there are few examples where the occurrence of memory failures is considered in the broader context of system power, temperature, and the execution of user jobs. In this paper, we combine job data with existing power, temperature, and memory failure data collected on a petascale HPC system. By focusing on periods when jobs were running on the system, we identified trends that were not evident in earlier studies of this same data. The inclusion of job data also demonstrated how user behavior can affect the occurrence of memory failures. In conjunction with this paper, we have publicly released the job data used in this paper to complement existing publicly-available data from Astra regarding power, temperature, and the occurrence of correctable memory failures.

关键词： Temperature distribution high performance computing Random access memory Graphics processing units Focusing Reliability engineering Market research Hardware Object recognition Forecasting

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Proceedings - 2022 IEEE international symposium on high-performance computer architecture, HPCA 2022

Proceedings - 2022 IEEE International Symposium on High-Perf...

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28th Annual IEEE international symposium on high-performance computer architecture, HPCA 2022

ISBN: (纸本)9781665420273

The proceedings contain 85 papers. The topics discussed include: direct spatial implementation of sparse matrix multipliers for reservoir computing;CAMA: energy and memory efficient automata processing in content-addressable memories;leaky frontends: security vulnerabilities in processor frontends;abusing cache line dirty states to leak information in commercial processors;cottage: coordinated time budget assignment for latency, quality and power optimization in web search;enabling efficient large-scale deep learning training with cache coherent disaggregated memory systems;Hercules: heterogeneity-aware inference serving for at-scale personalized recommendation;ANNA: specialized architecture for approximate nearest neighbor search;and hardware-accelerated hypergraph processing with chain-driven scheduling.

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LearnedFTL: A Learning-Based Page-Level FTL for Reducing Double Reads in Flash-Based SSDs

LearnedFTL: A Learning-Based Page-Level FTL for Reducing Dou...

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IEEE symposium on high-performance computer architecture

作者： Shengzhe Wang Zihang Lin Suzhen Wu Hong Jiang Jie Zhang Bo Mao Xiamen Key Laboratory of Intelligent Storage and Computing School of Informatics Xiamen University Xiamen Fujian China Computer Science and Engineering Department University of Texas at Arlington Arlington TX USA School of Computer Science Peking University Beijing China

We present LearnedFTL, a new on-demand pagelevel flash translation layer (FTL) design, which employs learned indexes to improve the address translation efficiency of flashbased SSDs. The first of its kind, it reduces the number of double reads induced by address translation in random read accesses. LearnedFTL proposes three key techniques: an in-place-update linear model to build learned indexes efficiently, a virtual PPN representation to obtain contiguous PPNs for sorted LPNs, and a group-based allocation and model training via GC/rewrite strategy to reduce the training overhead. By tightly integrating the aforementioned key techniques, LearnedFTL considerably speeds up address translation while reducing the number of flash read accesses caused by the address translation. Our extensive experiments on a FEMU-based prototype show that LearnedFTL can reduce up to 55.5% address translation-induced double reads. As a result, LearnedFTL reduces the P99 tail latency by 2.9× ∼ 12.2× with an average of 5.5× and 8.2× compared to the state-of-the-art TPFTL and LeaFTL schemes, respectively.

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Predicting Protein Folding on Intel’s Data Center GPU Max Series architecture (PVC)

Predicting Protein Folding on Intel’s Data Center GPU Max S...

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high performance computing, Networking, Storage and Analysis, SC-W: workshops of the international Conference for

作者： Dhani Ruhela Madhavan Prasanna Aaditya Saxena Westwood High School Austin Texas College of Science Purdue University West Lafayette IN Bob Jones High School Madison AL

ISBN: (数字)9798350355543

ISBN: (纸本)9798350355550

Predicting the structure and interactions of proteins and other life molecules has been a grand challenge for over 60 years. Google’s DeepMind AI team leveraged Artificial intelligence (AI) in 2020 to develop AlphaFold and achieved an accuracy above 90 for two-thirds of the proteins in CASP’s global distance test (GDT). AlphaFold has been very successful in biology and medicine. However, a lack of training code and expansive computational requirements created an open-source implementation named OpenFold. OpenFold is fast, memory-efficient, and provides an OpenProtein dataset with five million MSAs. MLCommons added OpenFold to their HPC benchmarks suite in 2023 and was evaluated by four institutions on NVIDIA GPU architectures. This work presents our endeavours to port, run and tune OpenFold on Intel’s GPU Max Series Ponte Vecchio (PVC). To the best of our knowledge, this is the first large-scale study of the distributed implementation of OpenFold application with Intel PVC GPU, presenting the challenges, opportunities and performance of the application on Intel’s Max series architecture.

关键词： Proteins Training performance evaluation Codes Accuracy Graphics processing units computer architecture Biology Artificial intelligence Tuning

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RAW 2024 Invited Talk-8: Practical Reconfigurable computing for Next-Generation Edge Applications

RAW 2024 Invited Talk-8: Practical Reconfigurable Computing ...

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IEEE international symposium on Parallel and Distributed Processing workshops and Phd Forum (IPDPSW)

作者： Hayden Kwok-Hay So University of Hong Kong

ISBN: (数字)9798350364606

ISBN: (纸本)9798350364613

Reconfigurable computing technologies using FPGA have long been an indispensable part of the product development cycles. They have been a staple for prototyping a system design during early development and have served as the main computing fabric for a large segment of products that demand high performance and fast time-tomarket. Yet in many recent edge sensing AIoT applications, the demand for extreme low power consumption, high performance, low cost and high volume are driving the industry to invest in ASIC solutions instead. In this talk, I will briefly explore the landscape of processing in the era of edge AIoT applications and argue for the need of reconfigurability in many practical scenarios. I will illustrate how spatially reconfigurable systems are desirable to provide low-latency near-sensor computing with spiking neural network (SNN). Finally, I will conclude with a few thoughts on where FPGA can be useful to address the imminent challenges with large language model inference and training in the edge.

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Advanced eHealth with Explainable AI: Secured by Blockchain with AI-Empowered Block Sensitivity for Adaptive Authentication 35

Advanced eHealth with Explainable AI: Secured by Blockchain ...

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35th IEEE international symposium on Personal, Indoor and Mobile Radio Communications, PIMRC 2024

作者： Dutta, Joy Eldeeb, Hossien B. Ho, Tu Dac Khalifa University C2PS Research Center Department of Computer Science Abu Dhabi United Arab Emirates University of Cambridge Electrical Engineering Division CambridgeCB3 0FA United Kingdom Faculty of Information Technology and Electrical Engineering Trondheim Norway

ISBN: (纸本)9798350362244

This paper presents an innovative, yet secure, eHealth framework that leverages Explainable Artificial Intelligence (XAI) and blockchain technology to enhance transparency and security in the IoT-edge-cloud continuum. The framework incorporates SHapley Additive exPlanations (SHAP) to provide real-time, model-agnostic explanations for AI predictions, enabling personalized health monitoring and informed decisionmaking in healthcare. To strengthen data security, a consortium blockchain is employed, and AI is utilized to identify block data sensitivity at the edge within blockchain-integrated IoT architectures using Random Forest (RF) algorithm. This approach achieves high accuracy in validating block sensitivity, enabling efficient selection of authentication mechanisms in the proof of authentication (PoAh) consensus within the consortium blockchain. This ensures heightened protection for sensitive data and contributes to improved overall blockchain performance. The proposed framework is evaluated in an edge computing environment and demonstrates significant potential for advancing security and authentication in eHealth, representing a substantial advancement in healthcare technology. © 2024 IEEE.

关键词： Electronic health record

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