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检索条件"任意字段=2024 International Symposium on Computer Architecture and High Performance Computing Workshops"

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Exploitation of Security Vulnerability on Retirement

Exploitation of Security Vulnerability on Retirement

引用

IEEE symposium on high-performance computer architecture

作者： Ke Xu Ming Tang Quancheng Wang Han Wang Key Laboratory of Aerospace Information Security and Trusted Computing Ministry of Education School of Cyber Science and Engineering Wuhan University Wuhan China

The backend of the processor executes the μops decoded from the frontend out of order, while the retirement is responsible for retiring completed μops in the Reorder Buffer in order. Consequently, the retirement may stall differently depending on the execution time of the first instruction in the Reorder Buffer. Moreover, since retirement is shared between two logical cores on the same physical core, an attacker can deduce the instructions executed on the other logical core by observing the availability of its own retirement. Based on this finding, we introduce two novel covert channels: the Different Instructions covert channel and the Same Instructions covert channel, which can transmit information across logical cores and possess the ability to bypass the existing protection strategies. Furthermore, this paper explores additional applications of retirement. On the one hand, we propose a new variant of Spectre v1 by applying the retirement to the Spectre attack using the principle that the fallback penalty of misprediction is related to the instructions speculated to be executed. On the other hand, based on the principle that different programs result in varied usage patterns of retirement, we propose an attack method that leverages the retirement to infer the program run by the victim. Finally, we discuss possible mitigations against new covert channels.

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Interference Reduction Design for Improved Multitarget Detection in ISAC Systems 35

Interference Reduction Design for Improved Multitarget Detec...

引用

35th IEEE international symposium on Personal, Indoor and Mobile Radio Communications, PIMRC 2024

作者： Delamou, Mamady Amhoud, El Mehdi College of Computing Mohammed Vi Polytechnic University Ben Guerir43150 Morocco

ISBN: (纸本)9798350362244

The advancement of wireless communication systems toward 5G and beyond is spurred by the demand for high data rates, exceedingly dependable low-latency communication, and extensive connectivity that aligns with sensing requisites such as advanced high-resolution sensing and target detection. Consequently, embedding sensing into communication has gained considerable attention. In this work, we propose an alternative approach for optimizing integrated sensing and communication (ISAC) waveform for target detection by concurrently maximizing the power of the communication signal at an intended user and minimizing the multi-user and sensing interference. We formulate the problem asa non-disciplined convex programming (NDCP) optimization and we use a distribution-based approach for interference cancellation. Precisely, we establish the distribution of the communication signal and the multi-user communication interference received by the intended user. After that, we establish that the sensing interference can be distributed as a centralized Chi-squared if the sensing covariance matrix is idempotent. We design such a matrix based on the symmetrical idempotent property. Additionally, we propose a disciplined convex programming (DCP) form of the problem, and using successive convex approximation (SCA), we show that the solutions can reach a stable waveform for efficient target detection. Furthermore, we compare the proposed waveform with state of the art radar-communication waveform designs and demonstrate its superior performance by computer simulations. © 2024 IEEE.

关键词： Radar interference

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Efficient Distributed Sequence Parallelism for Transformer-based Image Segmentation

Efficient Distributed Sequence Parallelism for Transformer-b...

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IS and T international symposium on Electronic Imaging 2024: high performance computing for Imaging 2024

作者： Lyngaas, Isaac Meena, Murali Gopalakrishnan Calabrese, Evan Wahib, Mohamed Chen, Peng Igarashi, Jun Huo, Yuankai Wang, Xiao National Center for Computational Sciences Oak Ridge National Laboratory Oak RidgeTN United States Computational Sciences and Engineering Division Oak Ridge National Laboratory Oak RidgeTN United States Department of Radiology Duke University DurhamNC United States Riken Center for Computational Science Tokyo Japan National Institute of Advanced Industrial Science and Technology Tokyo Japan Department of Computer Science Vanderbilt University NashvilleTN United States

We introduce an efficient distributed sequence parallel approach for training transformer-based deep learning image segmentation models. The neural network models are comprised of a combination of a Vision Transformer encoder with a convolutional decoder to provide image segmentation mappings. The utility of the distributed sequence parallel approach is especially useful in cases where the tokenized embedding representation of image data are too large to fit into standard computing hardware memory. To demonstrate the performance and characteristics of our models trained in sequence parallel fashion compared to standard models, we evaluate our approach using a 3D MRI brain tumor segmentation dataset. We show that training with a sequence parallel approach can match standard sequential model training in terms of convergence. Furthermore, we show that our sequence parallel approach has the capability to support training of models that would not be possible on standard computing resources. © 2024, Society for Imaging Science and Technology.

关键词： Image segmentation

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TailorFS: An Adaptive File System to Support Dynamic I/O requirements of HPC Workloads

TailorFS: An Adaptive File System to Support Dynamic I/O req...

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international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Hariharan Devarajan Kathryn Mohror Lawrence Livermore National Laboratory

ISBN: (数字)9798350356168

ISBN: (纸本)9798350356175

high-performance computing (HPC) systems typically provide a global storage system to support large-scale workload’s I/O requirements. However, these workloads have diversified from traditional simulation to include big data analytics and AI workloads. HPC systems include hardware accelerators and storage software with configurations to support this workload diversification. However, selecting the correct combination of these configurations for each workload is a complex task even for I/O experts. To address this problem, we designed TailorFS, a software abstraction using FSView that transparently selects the appropriate file system characteristics including software abstractions, hardware accelerators, and optimizations to accelerate I/O for a given workload. Given a workload’s behavior, TailorFS chooses an appropriate software existing in the system and a corresponding configuration to dynamically optimize the workload. With TailorFS, users can utilize any interface to perform I/O on the file system and get the correct software selected for them based on the described behavior. Finally, TailorFS can accelerate I/O for different workload types by up to 46 × by utilizing workload characteristics. In conclusion, TailorFS can accelerate complex HPC workflows by up to 6.5 × better I/O performance on the Lassen supercomputer by using dynamically created workload-aware FSViews.

关键词： File systems high performance computing Memory management Throughput Software Supercomputers Libraries Middleware Optimization Hardware acceleration

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Charged Particle Reconstruction for Future high Energy Colliders with Quantum Approximate Optimization Algorithm 3rd

Charged Particle Reconstruction for Future High Energy Coll...

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3rd BenchCouncil international symposium on Intelligent computers, Algorithms, and Applications, IC 2023

作者： Okawa, Hideki Institute of High Energy Physics Chinese Academy of Sciences Beijing Shijingshan100049 China

ISBN: (纸本)9789819700646

Usage of cutting-edge artificial intelligence will be the baseline at future high energy colliders such as the high-Luminosity Large Hadron Collider, to cope with the enormously increasing demand of the computing resources. The rapid development of quantum machine learning could bring in further paradigm-shifting improvement to this challenge. One of the two highest CPU-consuming components, the charged particle reconstruction, the so-called track reconstruction, can be considered as a quadratic unconstrained binary optimization (QUBO) problem. The Quantum Approximate Optimization Algorithm (QAOA) is one of the most promising algorithms to solve such combinatorial problems and to seek for a quantum advantage in the era of the Noisy Intermediate-Scale Quantum computers. It is found that the QAOA shows promising performance and demonstrated itself as one of the candidates for the track reconstruction using quantum computers. © 2024, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.

关键词： Charged particles

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Cascading Structured Pruning: Enabling high Data Reuse for Sparse DNN Accelerators 22

Cascading Structured Pruning: Enabling High Data Reuse for S...

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49th IEEE/ACM Annual international symposium on computer architecture (ISCA)

作者： Hanson, Edward Li, Shiyu Li, Hai 'Helen' Chen, Yiran Duke Univ Durham NC 27706 USA

ISBN: (纸本)9781450386104

performance and efficiency of running modern Deep Neural Networks (DNNs) are heavily bounded by data movement. To mitigate the data movement bottlenecks, recent DNN inference accelerator designs widely adopt aggressive compression techniques and sparse-skipping mechanisms. These mechanisms avoid transferring or computing with zero-valued weights or activations to save time and energy. However, such sparse-skipping logic involves large input buffers and irregular data access patterns, thus precluding many energy-efficient data reuse opportunities and dataflows. In this work, we propose Cascading Structured Pruning (CSP), a technique that preserves significantly more data reuse opportunities for higher energy efficiency while maintaining comparable performance relative to recent sparse architectures such as SparTen. CSP includes the following two components: At algorithm level, CSP-A induces a predictable sparsity pattern that allows for low-overhead compression of weight data and sequential access to both activation and weight data. At architecture level, CSP-H leverages CSP-A's induced sparsity pattern with a novel dataflow to access unique activation data only once, thus removing the demand for large input buffers. Each CSP-H processing element (PE) employs a novel accumulation buffer design and a counter-based sparse-skipping mechanism to support the dataflow with minimum controller overhead. We verify our approach on several representative models. Our simulated results show that CSP achieves on average 15x energy efficiency improvement over SparTen with comparable or superior speedup under most evaluations.

关键词： MLAcceleration Model Compression Hardware/software co-design Low Power Microarchitecture

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Microservice Deployment for Satellite Edge AI Inference via Deep Reinforcement Learning 35

Microservice Deployment for Satellite Edge AI Inference via ...

引用

35th IEEE international symposium on Personal, Indoor and Mobile Radio Communications, PIMRC 2024

作者： Yu, Zhiyong Cheng, Hei Victor Yang, Zhanpeng Liu, Xin Jiang, Yuning Zhou, Yong Shi, Yuanming ShanghaiTech University School of Information Science and Technology Shanghai201210 China Aarhus University Department of Electrical and Computer Engineering Denmark Automatic Control Laboratory Switzerland

ISBN: (纸本)9798350362244

Artificial intelligence (AI) is critical in evolving 5G and developing 6G networks, running on edge devices, and solving resource management challenges. The burgeoning number of edge devices draws attention to the potential of low-earth orbit (LEO) satellite networks with their onboard computing capabilities for edge inference. This paper explores LEO scenarios where multiple remote sensing edge AI inference tasks concurrently process data from a single source. However, due to there being parts with the same functions between different AI applications, traditional monolithic edge AI architecture must be deployed repeatedly and falls short in efficiently harnessing the heterogeneous resources of LEO satellite networks. To solve this problem, we utilize the microservice architecture to decouple a single AI application into several independent microservices to reuse these same functions. However, due to the high latency caused by multiple microservices' communication, we need to design a deployment strategy to fully utilize resources to reduce the service latency. We present a microservice deployment model to minimize the total service latency across all AI applications and meet resource constraints with the constraints of hardware, energy, and memory limitations. This latency optimization problem is rewritten as a Markov decision process (MDP) to effectively deal with the challenge posed by the time-varying transmission rate caused by satellite mobility. To increase the training data utilization, we employ a Proximal Policy Optimization (PPO) based reinforcement learning algorithm to meet the dynamic environment challenge. Finally, we obtain a sub-optimal solution with minimal accuracy loss and an acceptable solution time. © 2024 IEEE.

关键词： Markov processes

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S-Clflush: Securing Against Flush-based Cache Timing Side-Channel Attacks

S-Clflush: Securing Against Flush-based Cache Timing Side-Ch...

引用

international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Tejeshwar Bhagatsing Thorawade Prajakta Yeola Varun Venkitaraman Virendra Singh Indian Institute of Technology Bombay India

ISBN: (数字)9798350356168

ISBN: (纸本)9798350356175

Micro-architectural attacks exploit intrinsic vulnerabilities within computing systems, circumventing advanced security techniques such as cryptographic algorithms, access control policies, and secure enclaves. These attacks encompass a range of methodologies, including cache timing side-channel attacks like Flush+Reload, Flush+Flush, and Prime+Probe, as well as speculative execution attacks such as Spectre and Meltdown. These exploits leverage specific characteristics of micro-architecture to infer sensitive data, posing a significant threat to system security. Cache timing side-channel attacks exploit the inclusive nature of the last-level cache (LLC) to deduce the memory access patterns of victim processes. By observing the timing variations associated with cache hits and misses, attackers can extract confidential information, such as cryptographic keys. Although existing mitigation strategies provide a level of security, they typically do so at the expense of system performance and increased hardware. These trade-offs limit the practical applicability of such defences in performance-critical environments. This paper proposes S-Clflush: Secure Clflush, an innovative defence mechanism specifically designed to counter flush-based cache timing side-channel attacks. S-Clflush achieves this by modifying the existing clflush instruction to prevent attackers from inferring memory access patterns based on cache access latency. Unlike traditional mitigation techniques, S-Clflush enhances security without incurring performance degradation or additional area overhead. The proposed mechanism is formally verified to ensure its security guarantees. Our evaluation against the state-of-the-art mitigation technique TimeCache shows a 0.5% improvement in performance and a 58% reduction in MPKI on average without adding area overhead.

关键词： Degradation Prevention and mitigation System performance high performance computing Side-channel attacks computer architecture Hardware Timing Security Data mining

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Evaluating HPC Kernels for Processing in Memory

Evaluating HPC Kernels for Processing in Memory

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international symposium on Memory Systems (MEMSYS)

作者： Asifuzzaman, Kazi Monil, Mohammad Alaul Haque Liu, Frank Vetter, Jeffrey S. Oak Ridge Natl Lab Oak Ridge TN 37830 USA

ISBN: (纸本)9781450398008

Memory subsystems contribute significantly to the performance and energy efficiency of high-performance computing (HPC) applications. Traditional memory technologies with conventional organization (e.g., DRAM) are struggling to keep up with the increasing memory requirements of modern applications. Techniques such as multilayer cache hierarchy and out-of-order execution are still falling short of mitigating the penalty incurred by memory accesses. Processing-in-memory (PIM), which involves moving memory-intensive kernels to memory for execution instead of bringing the data to the processing unit, is emerging as a promising technique. PIM has recently received traction among computer architecture researchers, and the increasing research activity surrounding this technique indicates its potential to alleviate main memory performance bottlenecks. In this paper, we characterize and identify memory-intensive HPC kernels, perform a first-order evaluation of the PIM technique for selected HPC kernels, quantify performance deviation, and analyze the key factors that affect PIM efficiency.

关键词： Processing in Memory high-performance computing

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Extending the Mochi Methodology to Enable Dynamic HPC Data Services

Extending the Mochi Methodology to Enable Dynamic HPC Data S...

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IEEE international symposium on Parallel and Distributed Processing workshops and Phd Forum (IPDPSW)

作者： Matthieu Dorier Philip Carns Robert Ross Shane Snyder Rob Latham Amal Gueroudji George Amvrosiadis Chuck Cranor Jerome Soumagne Argonne National Laboratory Carnegie Mellon University Intel Corporation

ISBN: (数字)9798350364606

ISBN: (纸本)9798350364613

high-performance computing (HPC) applications and workflows are increasingly making use of custom data services to complement traditional parallel file systems with fast transient data management capabilities tailored to application-specific needs. In the Mochi project we provide methodologies and tools that enable rapid development of custom HPC data services, including a collection of composable software components that can be combined to build complex distributed data services. Our initial version of Mochi targeted data services deployed with static configurations with a fixed number of nodes and minimal fault tolerance. However, there is a growing need for dynamic services that can adapt while running in response to changing workloads and system conditions. In this paper we present our work to extend the Mochi architecture to support the development of dynamic data services. We achieve this by providing new Mochi components that support unified bootstrapping and online reconfiguration, fault detection, monitoring, and consensus. We also provide a methodology for deriving service-wide resilience from the resilience of each of the service's components.

关键词： Productivity high performance computing Distributed databases Authentication Software Encryption Security

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