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检索条件"任意字段=2024 International Symposium on Computer Architecture and High Performance Computing Workshops"

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Message from the Quantum computing Workshop Chairs;ISVLSI 2024

Message from the Quantum Computing Workshop Chairs;ISVLSI 20...

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IEEE computer Society Annual symposium on VLSI

作者： Travis S. Humble Himanshu Thapliyal Oak Ridge National Laboratory USA University of Tennessee Knoxville USA

ISBN: (数字)9798350354119

ISBN: (纸本)9798350354126

It is with great pleasure that we welcome you to the 2024 international Workshop on Quantum computing: Circuits Systems Automation and Applications (QC-CSAA) in conjunction with the ISVLSI 2024. The previous editions (2020, 2021 and 2022) of QC-CSAA have occurred as successful workshops in the past. The QC-CSAA workshop will provide a comprehensive review on fundamentals as well as the current state of the art in research and technology. The purpose of this is to explore design paradigms of quantum computing including developing a full stack from quantum algorithms to quantum chips. Advances in quantum computing hardware, software, and algorithms as well as contributions on the transformative research needed to guide quantum computing performance toward practical and sustainable operations are aligned with the goal of this symposium. Further, circuits and systems targeting novel and existing applications of quantum computing to fields such as quantum chemistry, linear algebra, scientific applications, aerospace, material science, machine learning, etc. were of special interest.

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Trapezoid: A Versatile Accelerator for Dense and Sparse Matrix Multiplications

Trapezoid: A Versatile Accelerator for Dense and Sparse Matr...

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Annual international symposium on computer architecture, ISCA

作者： Yifan Yang Joel S. Emer Daniel Sanchez MIT CSAIL MIT CSAIL/NVIDIA

ISBN: (数字)9798350326581

ISBN: (纸本)9798350326598

Accelerating matrix multiplication is crucial to achieve high performance in many application domains, including neural networks, graph analytics, and scientific computing. These applications process matrices with a wide range of sparsities, from completely dense to highly sparse. Ideally, a single accelerator should handle matrices of all sparsity levels well. However, prior matrix multiplication accelerators each target a limited range of sparsity levels. We present Trapezoid, a versatile accelerator that performs matrix multiplication across all sparsity levels effectively. Trapezoid builds on a 2D spatial array design, which excels at dense matrix multiplication, and extends it with new hardware mechanisms that let it handle sparse inputs. We present a novel innerproduct-based dataflow with a multi-fiber intersection unit that handles mildly sparse matrices. Furthermore, novel Gustavsonbased dataflows and a multi-level memory hierarchy enable high performance on highly sparse matrices. Trapezoid’s hardware extensions are reused across dataflows to minimize area overheads. We evaluate Trapezoid on a broad range of dense and sparse matrix multiplication workloads. Trapezoid has gmean $19.7 \times$, $4.3 \times$, and $2.9 \times$ better performance/area than TPU, SIGMA, and Flexagon, prior state-of-the-art accelerators that target dense, mildly sparse, and highly sparse matrices, respectively.

关键词： Costs Scientific computing Neural networks computer architecture Throughput Hardware Sparse matrices

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HardCilk: Cilk-like Task Parallelism for FPGAs 32

HardCilk: Cilk-like Task Parallelism for FPGAs

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32nd IEEE Annual international symposium on Field-Programmable Custom computing Machines, FCCM 2024

作者： Shahawy, Mohamed Sönmez, Canberk Belentepe, Cemalettin Ienne, Paolo School of Computer and Communication Sciences Lausanne Switzerland

ISBN: (纸本)9798350372434

high-level synthesis (HLS) helps to develop hard-ware accelerators for field-programmable gate arrays (FPGAs) using C/C++ descriptions. HLS is tailored to exploit instruction-level parallelism and, where available, data-level parallelism in applications. Yet, some applications mostly display another type of parallelism known as task-level parallelism (TLP): they may have massive amounts of available parallelism but paralleliz-able execution threads follow starkly different control paths or make completely independent memory accesses. Alas, there is very limited support for TLP in HLS tools (with much of the support being for statically scheduled coarse-grained tasks) whereas TLP is widely supported on conventional CPU platforms via libraries like OpenCilk, Intel Threading Building Blocks, and OpenMP. In this paper, we introduce a framework for supporting software-like TLP on FPGAs. The framework provides a parameterized architectural template that implements all hardware modules needed to support TLP primitives and task management. The emphasis is on providing programmers with a software-like experience: limited hardware resource constraints should only impact performance and never functionality. For this, all queues in the limited BRAMs are virtually extended to larger HBM/DDR FPGA memory and potentially beyond. We provide an open-source Chisel hardware generator that creates a dedicated task management system from a given Cilk-like application description. It is then straightforward to integrate it with HLS-based processing elements to realize full TLP-enabled applications on FPGAs. In the evaluation, we focus on the efficiency and scalability of our hardware task management system and compare it with OpenCilk, a recent software TLP framework. The results show that the architectural building blocks consume a small percentage of resources on modern FPGAs designed for data centres and achieve linear hardware scalability. For a reasonable range of parameters, the sys

关键词： Efficiency

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Ponte Vecchio Across the Atlantic: Single-Node Benchmarking of Two Intel GPU Systems 24

Ponte Vecchio Across the Atlantic: Single-Node Benchmarking ...

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Proceedings of the SC '24 workshops of the international Conference on high performance computing, Network, Storage, and Analysis

作者： Thomas Applencourt Aditya Sadawarte Servesh Muralidharan Colleen Bertoni JaeHyuk Kwack Ye Luo Esteban Rangel John Tramm Yasaman Ghadar Arjen Tamerus Chris Edsall Tom Deakin Argonne Leadership Computing Facility Argonne National Laboratory Lemont IL USA School of Computer Science University of Bristol Bristol UK University of Cambridge Cambridge UK

ISBN: (纸本)9798350355543

Intel Data Center GPU Max 1550, known as Ponte Vecchio (PVC), is a new Intel GPU architecture for high-performance computing. It is the basis of two systems on the June 2024 Top 500 list, Dawn (#51) and Aurora (#2).This work provides micro-benchmarking data on PVCs from which application developers may benefit, shows how the micro-benchmarking results are indicative of mini-app performance on PVC, and demonstrates real applications on large-scale Intel GPU *** quantify the obtainable performance from PVC systems through micro-benchmarking fundamental architectural properties. We evaluate the performance of four mini-apps with known performance characteristics, and two full applications, comparing performance on a node of Aurora and Dawn with a node of NVIDIA H100 GPUs and a node of AMD MI250 GPUs. We show the figure-of-merit of the mini-apps on a single PVC ranges from 0.6-1.8X the performance of an H100, and 0.8-7.5X of a MI250.

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FPGA ORIENTED LIGHTWEIGHT DEEP LEARNING INFERENCE FOR LIVER CANCER SEGMENTATION 21

FPGA ORIENTED LIGHTWEIGHT DEEP LEARNING INFERENCE FOR LIVER ...

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21st IEEE international symposium on Biomedical Imaging (ISBI)

作者： Xu, Yingying Wang, Yinjie Chen, Qingqing Hu, Hongjie Huang, Huimin Lin, Lanfen Chen, Yen-Wei Li, Jingsong Lin, Hongxiang Zhejiang Lab Hangzhou Peoples R China Zhejiang Univ Sir Run Run Shaw Hosp Hangzhou Peoples R China Zhejiang Univ Coll Comp Sci & Technol Hangzhou Peoples R China Ritsumeikan Univ Coll Informat Sci & Engn Shiga Japan

ISBN: (纸本)9798350313345;9798350313338

Field-programmable gate arrays (FPGAs) have succeeded in deep learning (DL) inference due to their high parallelism and low power consumption, potentially enabling the miniaturization of DL-based computer aided diagnosis (CAD) system using liver cancer segmentation. However, state-of-the-art deep learning backbone models tend to enlarge their model capacity or design complex unfolding architectures, which may hinder the implementation on FPGA with relatively slow updates of specs and computational resources. This paper proposes a new method for lightweight inference on FPGAs that combines lightweight modeling and FPGA-based model compression. Firstly, our proposed split-attention-shuffle bottleneck (SASB) is the module that could provide fast adaptation of light weighting to a standard network simply through layer substitution. Secondly, we employ the model compression techniques by means of standard quantization and compilation methods on an in-house prototyping edge device named HIDE, significantly reducing precision of inference model weights but preserving the model accuracy. Experiments show that our method saves budgets of computational resources while preserving comparable performance compared to other heavy-weight models. Our approach is not limited to specialized edge computing devices and can be extended to other deep learning methods and medical imaging modalities, enhancing the potential and impact of portable CAD systems.

关键词： FPGA lightweight network computer-aided diagnosis tumor segmentation

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An Optimizing Framework on MLIR for Efficient FPGA-based Accelerator Generation

An Optimizing Framework on MLIR for Efficient FPGA-based Acc...

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IEEE symposium on high-performance computer architecture

作者： Weichuang Zhang Jieru Zhao Guan Shen Quan Chen Chen Chen Minyi Guo Department of Computer Science and Engineering Shanghai Jiao Tong University

With the increasing demand for computing capability given limited resource and power budgets, it is prominent to deploy applications to customized accelerators like FPGAs. However, FPGA programming is non-trivial. Although existing high-level synthesis (HLS) tools improve productivity to a certain extent, they are limited in scope and capability to support sufficient FPGA-oriented transformations and optimizations. This paper focuses on FPGA-based accelerators and proposes POM, an end-to-end optimizing framework built on multi-level intermediate representation (MLIR). POM has several features which demonstrate its scope and capability of performance optimization. First, most HLS tools depend exclusively on a single-level IR like LLVM IR to perform all the optimizations, introducing excessive information into the IR and making debugging an arduous task. In contrast, POM explicitly introduces three layers of IR to perform operations at suitable abstraction levels, streamlining the implementation and debugging process and exhibiting better flexibility, extensibility, and systematicness. Second, POM integrates the polyhedral model into MLIR and hence enables advanced dependence analysis and a wide range of FPGA-oriented loop transformations. By representing nested loops with integer sets and maps at suitable IR, loop transformations can be conducted conveniently through a series of manipulations on polyhedral semantics. Finally, to further relieve design effort, POM is equipped with a user-friendly programming interface (DSL) that allows a concise description of computation and includes a rich collection of scheduling primitives. An automatic design space exploration (DSE) engine is also provided to search for high-performance optimization schemes efficiently and generate optimized accelerators automatically. Experimental results show that POM achieves a 6.46× average speedup on typical benchmark suites and a 6.06 ×average speedup on real-world applications compared to

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Rapper: A Parameter-Aware Repair-in-Memory Accelerator for Blockchain Storage Platform

Rapper: A Parameter-Aware Repair-in-Memory Accelerator for B...

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IEEE symposium on high-performance computer architecture

作者： Chenlin Ma Yingping Wang Fuwen Chen Jing Liao Yi Wang Rui Mao College of Computer Science and Software Engineering Shenzhen University

Blockchain storage platforms reward storage nodes for keeping user-uploaded data for a certain amount of time. These storage nodes are unstable and can go online or offline unpredictably at any time, leading to potential data loss. To prevent data loss, blockchain storage platforms adopt erasure codes on user-uploaded encrypted data. Data repair processes will be performed to recover the lost data. However, the data repair processes heavily rely on time-consuming erasure coding algorithms, mainly consisting of vector-matrix multiplications. The emerging processing-in-memory technique can efficiently speed up the processing of vector-matrix multiplications. It can be integrated into blockchain storage platforms to solve the data repair issue. This paper presents Rapper, a parameter-aware repair-inmemory accelerator for blockchain storage platforms. Rapper utilizes the computing power of emerging processing-in-memory architecture so that data repair processes can be processed in a parallel manner and the overall efficiency can be improved significantly. Specifically, at the hardware level, the ReRAM memory is reorganized into our proposed double bank, XRU, XGroup, and ReRAM crossbars structure. At the software level, a parallel decoding/encoding strategy is proposed to fully exploit the internal parallelism of ReRAM. We also propose an adaptive parameter-aware mapping to handle various sizes of stripes. To demonstrate the viability of the proposed technique, a representative blockchain storage project Storj is adopted as the default storage infrastructure. Experimental results show that Rapper can achieve a 1.96 × speedup on average compared to the representative scheme.

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VAQEM: A Variational Approach to Quantum Error Mitigation 28

VAQEM: A Variational Approach to Quantum Error Mitigation

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28th Annual IEEE international symposium on high-performance computer architecture (HPCA)

作者： Ravi, Gokul Subramanian Smith, Kaitlin N. Gokhale, Pranav Mari, Andrea Earnest, Nathan Javadi-Abhari, Ali Chong, Frederic T. Univ Chicago Chicago IL 60637 USA Supertech Washington DC USA Unitary Fund Washington DC USA IBM TJ Watson Res Ctr IBM Quantum Yorktown Hts NY USA

ISBN: (纸本)9781665420273

Variational Quantum Algorithms (VQA) are one of the most promising candidates for near-term quantum advantage. Traditionally, these algorithms are parameterized by rotational gate angles whose values are tuned over iterative execution on quantum machines. The iterative tuning of these gate angle parameters make VQAs more robust to a quantum machine's noise profile. However, the effect of noise is still a significant detriment to VQA's target estimations on real quantum machines - they are far from ideal. Thus, it is imperative to employ effective error mitigation strategies to improve the fidelity of these quantum algorithms on near-term machines. While existing error mitigation techniques built from theory do provide substantial gains, the disconnect between theory and real machine execution characteristics limit the scope of these improvements. Thus, it is critical to optimize mitigation techniques to explicitly suit the target application as well as the noise characteristics of the target machine. We propose VAQEM, which dynamically tailors existing error mitigation techniques to the actual, dynamic noisy execution characteristics of VQAs on a target quantum machine. We do so by tuning specific features of these mitigation techniques similar to the traditional rotation angle parameters by targeting improvements towards a specific objective function which represents the VQA problem at hand. In this paper, we target two types of error mitigation techniques which are suited to idle times in quantum circuits: single qubit gate scheduling and the insertion of dynamical decoupling sequences. We gain substantial improvements to VQA objective measurements a mean of over 3x across a variety of VQA applications, run on IBM Quantum machines. More importantly, while we study two specific error mitigation techniques, the proposed variational approach is general and can be extended to many other error mitigation techniques whose specific configurations are hard to select a pri

关键词： quantum computing noisy intermediate-scale quantum variational quantum algorithms variational quantum eigensolver error mitigation dynamic decoupling gate scheduling

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Effect of Integrating Variational Autoencoder with SENet on Dimensionality Reduction in Driving Behavior Learning

Effect of Integrating Variational Autoencoder with SENet on ...

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international symposium on computing and Networking workshops (CANDARW)

作者： Yuta Uehara Susumu Matumae Department of Information Science Saga University Saga Japan

ISBN: (数字)9798331505349

ISBN: (纸本)9798331505356

Dimensionality reduction using Variational Autoencoder (VAE) is widely employed in learning diverse state representations, such as in autonomous driving tasks. Conventional VAE-based dimensionality reduction is a commonly used method for reducing the computational cost associated with learning from high-dimensional data, particularly image data, while achieving high performance. In this paper, we investigate the impact of integrating VAE with Squeeze-and-Excitation Networks (SENet), referred to as SENet-VAE, on the accuracy of learning driving behaviors in deep reinforcement learning. We conduct a series of experiments comparing three setups: raw image data, conventional VAE, and SENet-VAE. Additionally, we explore the effect of applying hyperparameters to the Kullback-Leibler (KL) divergence term in the objective function of the SENet-VAE to further optimize performance. Our results demonstrate that SENet-VAE outperforms the conventional VAE in terms of learning accuracy, with hyperparameter tuning leading to performance gains.

关键词： Dimensionality reduction Training Accuracy high dimensional data Autoencoders performance gain Linear programming Deep reinforcement learning Driver behavior Tuning

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An AI Driven Pipeline for 6G Enabled Digital Creatives Identification, performance Monitoring and Attribution

An AI Driven Pipeline for 6G Enabled Digital Creatives Ident...

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Cluster, Cloud and Internet computing workshops (CCGridW), IEEE/ACM international symposium on

作者： Varun Dutt Lucas Galan Faiyaz Doctor Lina Barakat Kate Isaacs Demetris Hadjigeorgiou Aldo Fumagalli Rapp Limited London UK School of Computer Science and Electronic Engineering University of Essex UK

ISBN: (数字)9798350377514

ISBN: (纸本)9798350377521

In the growing creative marketing sector, a high volume of digital assets in the form of images and videos are often generated for various forms of advertising. It is critical to be able to track these assets back to the original high value photo and video shoots they are derived from as well as understanding in real-time how well they are performing and how they can be augmented to perform better in response to the needs and preferences of dynamic audiences. In this paper we propose a framework that leverages deep learning approaches that learns to match local features across images to tie master images to various derived digital assets. The proposed pipeline is further able to use audience responses to predict performances of assets with attribution mechanisms for analysing how the modification of asset features enhance or degrade performance. We finally discuss how 6G infrastructures would be used with the pipeline to facilitate real-time and dynamically responsive content intelligence.

关键词： 6G mobile communication Solid modeling Target tracking Pipelines Predictive models Feature extraction Real-time systems Artificial intelligence Advertising Videos

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