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Classification Of Hookah Images With Deep Learning 8

Classification Of Hookah Images With Deep Learning

引用

8th international Artificial Intelligence and Data Processing symposium, IDAP 2024

作者： Arslan, Mustafa Tahir Ozkaynak, Emrah Karabuk University Institute of Postgraduate Education Department of Computer Engineering Karabük Turkey Karabuk University Software Engineering Department Karabük Turkey

ISBN: (纸本)9798331531492

With the proliferation of social media usage, there has been a notable increase in posts related to hookah consumption, driven by its visually appealing presentation and distinctive consumption method. Such posts, especially in the context of the decreasing age of social media users, have the potential to exert an enticing influence. The potential impact of social media content on tobacco product consumption underscores the importance of identifying whether these posts contain tobacco-related imagery. Deep learning techniques have become increasingly prevalent in the detection of tobacco products within images and videos. However, existing studies have predominantly focused on cigarette detection due to its relatively higher consumption rates, leaving the area of hookah detection underexplored. In this study, the detection of hookah images in social media content was undertaken using the YOLO v5 algorithm, a version of convolutional neural networks, for the classification of hookah as an object in digital images. To achieve this, a dataset comprising 7200 hookah images of varying shapes, colors, and sizes was compiled from social media platforms and various e-commerce websites. The dataset was trained using the YOLO v5 xl model, and the experimental results indicated a detection accuracy of 98.88%. The findings of this experimental study indicate that the developed application could be employed to generate alerts or obscure hookah images in social media content. Consequently, this approach could contribute to raising awareness regarding the risks associated with hookah use and mitigating its potentially alluring effects. © 2024 IEEE.

关键词： Convolutional neural networks

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BeamCount: Indoor Crowd Counting Using Wi-Fi Beamforming Feedback Information 24

BeamCount: Indoor Crowd Counting Using Wi-Fi Beamforming Fee...

引用

2024 international symposium on Theory, Algorithmic Foundations, and Protocol Design for Mobile Networks and Mobile computing, MobiHoc 2024

作者： Chen, Siyu Jiang, Hongbo Xiong, Jie Hu, Jingyang Wang, Penghao Liu, Chao Xiao, Zhu Li, Bo College of Computer Science and Electronic Engineering Hunan University China Microsoft Research Asia University of Massachusetts Amherst United States Department of Computer Science and Technology Ocean University of China China Department of Computer Science and Engineering The Hong Kong University of Science and Technology Hong Kong Hong Kong

ISBN: (纸本)9798400705212

Real-time indoor crowd counting plays an important role in many applications such as crowd control, resource allocation and advertisement. Current research predominantly relies on camera-based methods. However, computer vision-based solutions raise severe privacy and ethical concerns. In this paper, we propose a privacy-preserving counting solution called BeamCount based on Wi-Fi sensing. Instead of using conventional Wi-Fi Channel State Information (CSI) readings, we utilize Wi-Fi Beamforming Feedback Information (BFI) for crowd counting estimation. Compared to CSI which can only be extracted from few commodity Wi-Fi cards (e.g., Intel 5300), BFI readings can be obtained from a large range of commodity Wi-Fi devices. We establish a mapping relationship between BFI and headcount and extract headcounts from BFI inputs through a carefully designed adversarial network. Owing to the adversarial network’s cross-domain capability, the proposed counting system can achieve high accuracy across different environments, demonstrating its generalization capability. To mitigate the effect of BFI compression on sensing performance, we adopt a novel time series prediction model. Extensive real-world experiments validate the effectiveness of BeamCount in various environments, achieving an average counting accuracy of 93.6%. © 2024 Copyright held by the owner/author(s).

关键词： Resource allocation

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Ascend: a Scalable and Unified architecture for Ubiquitous Deep Neural Network computing 27

Ascend: a Scalable and Unified Architecture for Ubiquitous D...

引用

27th IEEE international symposium on high-performance computer architecture (HPCA)

作者： Liao, Heng Tu, Jiajin Xia, Jing Liu, Hu Zhou, Xiping Yuan, Honghui Hu, Yuxing Huawei Shenzhen Peoples R China

ISBN: (纸本)9781665422352

Deep neural networks (DNNs) have been successfully applied to a great variety of applications, ranging from small IoT devices to large scale services in a data center. In order to improve the efficiency of processing these DNN models, dedicated hardware accelerators are required for all these scenarios. Theoretically, there exists an optimized acceleration architecture for each application. However, considering the cost of chip design and corresponding tool-chain development, researchers need to trade off between efficiency and generality. In this work, we demonstrate that it is practical to use a unified architecture, called Ascend, to support those applications, ranging from IoT devices to data-center services. We provide a lot of design details to explain that the success of Ascend relies on contributions from different levels. First, heterogeneous computing units are employed to support various DNN models. And the datapath is adapted according to the requirement of computing and data access. Second, when scaling the Ascend architecture from a single core to a cluster containing thousands of cores, it involves design efforts, such as memory hierarchy and system level integration. Third, a multi-tier compiler, which provides flexible choices for developers, is the last critical piece. Experimental results show that using accelerators based on the Ascend architecture can achieve comparable or even better performance in different applications. In addition, various chips based on the Ascend architecture have been successfully commercialized. More than 100 million chips have been used in real products.

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Towards performance Portability of an Oil and Gas Application on Heterogeneous architectures

Towards Performance Portability of an Oil and Gas Applicatio...

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international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Arthur F. Lorenzon Phillipe O. A. Navaux Alexandre Sardinha Bronson Messer Institute of Informatics - UFRGS Porto Alegre Brazil Petróleo Brasileiro S.A. Rio de Janeiro Brazil Oak Ridge National Laboratory Oak Ridge USA

ISBN: (数字)9798350356168

ISBN: (纸本)9798350356175

With the widespread use of graphic processing units (GPUs) from different vendors in oil and gas companies, it has become increasingly important to achieve code portability. This allows for evaluating performance across diverse GPU vendors, enabling informed decisions. This capability enables companies to assess hardware solutions based on cost, performance, or energy efficiency, promoting competition and potentially driving innovation and cost reduction in GPU technologies. With that in mind, we address the challenge of achieving performance portability for Fletcher, an anisotropic wave propagation modeling application across various GPU architectures from NVIDIA and AMD. Hence, our first contribution is the parallel implementation of Fletcher on GPUs using eleven variations of portable programming models, including HIP, CUDA, Kokkos, RAJA, and OpenMP Target. Our second contribution is a comprehensive evaluation of these implementations across five generations of GPU from NVIDIA and AMD, assessing performance, performance-portability, and power-performance efficiency. Through an extensive set of experiments, we demonstrate that HIP outperforms the assessed programming models in terms of performance portability across all evaluated GPUs. Specifically, it performs 7.9% better than Kokkos, 8.8% better than RAJA, and 67.8% better than OpenMP Target. We also show that while the automatic translation of CUDA to HIP code allows for execution on AMD GPUs, optimizing for high performance is necessary. Additionally, we show that the programming models’ impact on Fletcher’s performance is heavily influenced by the size of the GPU’s L2 cache, especially given that this is a memory-intensive application.

关键词： Technological innovation Costs Codes Oils Propagation Graphics processing units computer architecture Companies Programming Hip

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HPC Data Storage at a Glance: The Santos Dumont Experience 33

HPC Data Storage at a Glance: The Santos Dumont Experience

引用

33rd IEEE international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Carneiro, Andre Ramos Bez, Jean Luca Osthoff, Carla Schnorr, Lucas Mello Navaux, Philippe O. A. Fed Univ Rio Grande do Sul UFRGS Inst Informat Porto Alegre RS Brazil Natl Lab Sci Comp LNCC Petropolis RJ Brazil

ISBN: (纸本)9781665443012

high-performance computing (HPC) platforms are used to solve the most diverse scientific problems in research areas, such as biology, chemistry, physics, and health sciences. Researchers use a multitude of scientific software, which have different requirements. These requirements include input and output operations, which directly impact performance due to the existing difference in processing and data access speeds. Thus, supercomputers must efficiently handle a mixed workload scenario when storing data from the applications. Knowledge of the application set and its performance running in a supercomputer is needed to understand the storage system's usage, pinpoint possible bottlenecks, and guide optimization techniques. This research proposes a methodology and visualization tool to evaluate a supercomputer's data storage infrastructure's performance, taking into account the diverse workload and demands of the system over a long period of operation. As a study case, we focus on the Santos Dumont supercomputer, where we were able to identify inefficient usage and problematic factors of performance.

关键词： Lustre Parallel File System high-performance Storage I/O Workload I/O Characterization Visualization

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MRHS multigrid solver for Wilson-clover fermions 39

MRHS multigrid solver for Wilson-clover fermions

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39th international symposium on Lattice Field Theory, LATTICE 2022

作者： Richtmann, Daniel Meyer, Nils Wettig, Tilo Department of Physics University of Regensburg Regensburg93040 Germany

We describe our implementation of a multigrid solver for Wilson-clover fermions, which increases parallelism by solving for multiple right-hand sides (MRHS) simultaneously. The solver is based on Grid and thus runs on all computing architectures supported by the Grid framework. We present detailed benchmarks of the relevant kernels, such as hopping and clover term on the various multigrid levels, intergrid operators, and reductions. The benchmarks were performed on the JUWELS Booster system at Jülich Supercomputing Centre, which is based on Nvidia A100 GPUs. For example, solving a 243 × 128 lattice on 16 GPUs, the overall speedup obtained solely from MRHS is about 10x. © Copyright owned by the author(s) under the terms of the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 international License (CC BY-NC-ND 4.0).

关键词： computer architecture

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GEYSER: A Compilation Framework for Quantum computing with Neutral Atoms 22

GEYSER: A Compilation Framework for Quantum Computing with N...

引用

49th IEEE/ACM Annual international symposium on computer architecture (ISCA)

作者： Patel, Tirthak Silver, Daniel Tiwari, Devesh Northeastern Univ Boston MA 02115 USA

ISBN: (纸本)9781450386104

Compared to widely-used superconducting qubits, neutral-atom quantum computing technology promises potentially better scalability and flexible arrangement of qubits to allow higher operation parallelism and more relaxed cooling requirements. The high performance computing (HPC) and architecture community is beginning to design new solutions to take advantage of neutral-atom quantum architectures and overcome its unique challenges. We propose GEYSER, the first work to take advantage of the multi-qubit gates natively supported by neutral-atom quantum computers by appropriately mapping quantum circuits to three-qubit-friendly physical arrangement of qubits. Then, GEYSER creates multiple logical blocks in the quantum circuit to exploit quantum parallelism and reduce the number of pulses needed to realize physical gates. These circuit blocks elegantly enable GEYSER to compose equivalent circuits with three-qubit gates, even when the original program does not have any multi-qubit gates. Our evaluation results show GEYSER reduces the number of operation pulses by 25%-90% and improves the algorithm's output fidelity by 25%-60% points across different algorithms.

关键词： Quantum computing NISQ computing Neutral Atoms Rydberg Atoms Quantum Compiling Quantum Software

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A GPU-based Method for Finding Optimal Solution to the Set Covering Problem

A GPU-based Method for Finding Optimal Solution to the Set C...

引用

IEEE international Conference on high performance computing workshops (HiPCW)

作者： Girish Biswas Nandini Mukherjee Department of Computer Science and Engineering Jadavpur University Kolkata West Bengal India

ISBN: (数字)9798331509118

ISBN: (纸本)9798331509125

The computation time of the exact and optimal solution to the set covering problem increases exponentially concerning the problem size due to an exhaustive search for the solution. We propose a novel GPU-based parallel method that is successful enough to accelerate the computation of the optimal solution via the exact exhaustive algorithm. This method shows significant SpeedUp in the computation of the optimal solution of the set covering problem with respect to the sequential method.

关键词： Scalability high performance computing Conferences Graphics processing units Programming Search problems Indexes Approximation methods

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Understanding the Power of Evolutionary Computation for GPU Code Optimization

Understanding the Power of Evolutionary Computation for GPU ...

引用

IEEE international symposium on Workload Characterization (IISWC)

作者： Liou, Jhe-Yu Awan, Muaaz Hofmeyr, Steven Forrest, Stephanie Wu, Carole-Jean Arizona State Univ Tempe AZ 85287 USA Lawrence Berkeley Natl Lab Berkeley CA USA

ISBN: (数字)9781665487986

ISBN: (纸本)9781665487986

Achieving high performance for GPU codes requires developers to have significant knowledge in parallel programming and GPU architectures, and in-depth understanding of the application. This combination makes it challenging to find performance optimizations for GPU-based applications, especially in scientific computing. This paper shows that significant speedups can be achieved on two quite different scientific workloads using the tool, GEVO, to improve performance over human-optimized GPU code. GEVO uses evolutionary computation to find code edits that improve the runtime of a multiple sequence alignment kernel and a SARS-CoV-2 simulation by 28.9% and 29% respectively. Further, when GEVO begins with an early, unoptimized version of the sequence alignment program, it finds an impressive 30 times speedupa performance improvement similar to that of the handtuned version. This work presents an in-depth analysis of the discovered optimizations, revealing that the primary sources of improvement vary across applications;that most of the optimizations generalize across GPU architectures;and that several of the most important optimizations involve significant code interdependencies. The results showcase the potential of automated program optimization tools to help reduce the optimization burden for scientific computing developers and enhance performance portability for domain-specific accelerators.

关键词： Codes Runtime Scientific computing Computational modeling Search methods Graphics processing units computer architecture

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ECO-CHIP: Estimation of Carbon Footprint of Chiplet-based architectures for Sustainable VLSI

ECO-CHIP: Estimation of Carbon Footprint of Chiplet-based Ar...

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IEEE symposium on high-performance computer architecture

作者： Chetan Choppali Sudarshan Nikhil Matkar Sarma Vrudhula Sachin S. Sapatnekar Vidya A. Chhabria Arizona State University University of Minnesota

ISBN: (数字)9798350393132

ISBN: (纸本)9798350393149

Decades of progress in energy-efficient and low-power design have successfully reduced the operational carbon footprint in the semiconductor industry. However, this has led to increased embodied emissions, arising from design, manufacturing, and packaging. While existing research has developed tools to analyze embodied carbon for traditional monolithic systems, these tools do not apply to near-mainstream heterogeneous integration (HI) technologies. HI systems offer significant potential for sustainable computing by minimizing carbon emissions through two key strategies: “reducing” computation by “reusing” pre-designed chiplet IP blocks and adopting hierarchical approaches to system design. The reuse of chiplets across multiple designs, even spanning multiple generations of ICs, can substantially reduce carbon emissions throughout the lifespan. This paper introduces ECO-CHIP, a carbon analysis tool designed to assess the potential of HI systems toward sustainable computing by considering scaling, chip let, and packaging yields, design complexity, and even overheads associated with advanced packaging techniques. Experimental results from ECO-CHIP demonstrate that HI can reduce embodied carbon emissions by up to 30% compared to traditional monolithic systems. ECO-CHIP is integrated with other chiplet simulators and is applied to chiplet disaggregation considering other metrics such as power, area, and cost. ECO-CHIP suggests that HI can pave the way for sustainable computing practices.

关键词： Costs Estimation Carbon dioxide computer architecture Green computing Very large scale integration Manufacturing

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