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HXNOR-PBNN: A Scalable and Parallel Spintronics Synaptic architecture for Probabilistic Binary Neural Networks

HXNOR-PBNN: A Scalable and Parallel Spintronics Synaptic Arc...

引用

IEEE international symposium on Circuits and Systems (ISCAS)

作者： Cancheng Xiao Yuxuan Ma Dingsong Jiang Jianle Liu Bingqian Song Jianshi Tang Huaqiang Wu Tianxiang Nan School of Integrated Circuits Tsinghua University Beijing China

ISBN: (数字)9798350330991

ISBN: (纸本)9798350331004

The combination of computing-in-memory (CIM) architecture and emerging non-volatile memory (NVM) is considered as a promising alternative for low-power electronics. Among different emerging NVMs, the insufficient conductance level of magnetoresistive random-access memory (MRAM) is a serious limitation to introduce its high performance into analogue CIM architecture. In this paper, we propose a probabilistic binary neural networks(PBNN) hardware based on voltage-controlled spin-orbit torque MRAM (VC-SOT-MRAM), which employs 2T2MTJ sub-tracks integrated of the probabilistic switching MTJs to achieve the bit-wise weights sampling and activation. Selective writing is discussed to co-optimized. A pipeline readout circuit with hybrid dynamic reference was suggested to improve the precision and throughput. In addition, a weight mapping method is applied for multi-tracks computing in parallel and kernel duplicating to improve the efficiency. Our proposal, simulated in 28 nm technology, achievean energy efficiency of 312.5 bTOPS/W, throughput of 527.3 bGOPS, accuracies of >90% on MNIST with more acceleration (58×), less resource requirement (32×) and high robust row-parallel computing.

关键词： Nonvolatile memory Pipelines Neural networks computer architecture In-memory computing Throughput Probabilistic logic

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GPU-Accelerated Tree-Search in Chapel Versus CUDA and HIP

GPU-Accelerated Tree-Search in Chapel Versus CUDA and HIP

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IEEE international symposium on Parallel and Distributed Processing workshops and Phd Forum (IPDPSW)

作者： Guillaume Helbecque Ezhilmathi Krishnasamy Nouredine Melab Pascal Bouvry DCS-FSTM/SnT University of Luxembourg Luxembourg Université de Lille CNRS/CRIStAL UMR 9189 Centre Inria de l'Université de Lille France

ISBN: (数字)9798350364606

ISBN: (纸本)9798350364613

In the context of exascale programming, the PGAS-based Chapel is among the rare languages targeting the holistic handling of high-performance computing issues including the productivity-aware harnessing of Nvidia and AMD GPUs. In this paper, we propose a pioneering proof-of-concept dealing with this latter issue in the context of tree-based exact optimization. Actually, we revisit the design and implementation of a generic multi-pool GPU-accelerated tree-search algorithm using Chapel. This algorithm is instantiated on the backtracking method and experimented on the N-Queens problem. For performance evaluation, the Chapel-based approach is compared to Nvidia CUDA and AMD HIP low-level counterparts. The reported results show that in a single-GPU setting, the high GPU abstraction of Chapel results in a loss of only 8% (resp. 16%) compared to CUDA (resp. HIP). In a multi-GPU setting, up to 80% (resp. 71%) of the baseline speedup is achieved for coarse-grained problem instances on Nvidia (resp. AMD) GPUs.

关键词： performance evaluation Distributed processing Backtracking high performance computing Conferences Graphics processing units Programming

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high Reliable and Accurate Stochastic computing-based Artificial Neural Network architecture Design

High Reliable and Accurate Stochastic Computing-based Artifi...

引用

IEEE international symposium on Circuits and Systems (ISCAS)

作者： Kun-Chih Jimmy Chen Wei-Ren Syu Institute of Electronics National Yang Ming Chiao Tung University Taiwan Department of Computer Science and Engineering National Sun Yat-Sen University Taiwan

ISBN: (数字)9798350330991

ISBN: (纸本)9798350331004

Hardware reliability has emerged as a paramount consideration in the modern Artificial Neural Network (ANN) design in recent years. The un-reliable ANN leads to un-trustable inference results and disasters (e.g., finance system or transportation system crash). To ensure hardware reliability, the common way is to insert some error correctness blocks or fault-tolerant computing blocks, which bring considerable hardware overhead and are improper to the resource-limited edge AI designs. To design hardware-friendly and highly reliable hardware, the Stochastic computing (SC) method has been proven to be an efficient way to achieve fault-tolerant computing goals. Consequently, many SC-based computing architectures have been introduced recently. However, because of the stochastic number representation, the computing accuracy issue is the design challenge to implement the SC-based computing architecture. To solve this problem, we propose a novel scaling-free adder and input data pre-processing method to achieve a reliable SC-based computing architecture and improve the accuracy of conventional SC-based ANN design. Compared with the traditional ANN design, the proposed SC-based ANN design maintains computing accuracy and enhances the performance by 32% to 55% while facing serious fault injection. In addition, the proposed SC-based ANN architecture reduces 48% to 81% power consumption and 51% to 92% area cost compared with the conventional ANN architecture.

关键词： Fault tolerance Accuracy Power demand Fault tolerant systems Stochastic processes Artificial neural networks computer architecture

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Towards the Acceleration of the Sparse Blossom Algorithm for Quantum Error Correction

Towards the Acceleration of the Sparse Blossom Algorithm for...

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IEEE international symposium on Parallel and Distributed Processing workshops and Phd Forum (IPDPSW)

作者： Marco Venere Valentino Guerrini Beatrice Branchini Davide Conficconi Donatella Sciuto Marco D. Santambrogio Dipartimento di Elettronica Informazione e Bioingegneria Politecnico di Milano Milan Italy

ISBN: (数字)9798350364606

ISBN: (纸本)9798350364613

Quantum computing is a new computing paradigm that exploits laws of quantum mechanics to achieve an exponential speedup compared to classical logic. However, noise strongly limits current quantum hardware, reducing achievable performance. Quantum Error Correction (QEC) techniques are a valuable approach to reduce the effects of noise. Nevertheless, the high computational complexity of QEC algorithms is incompatible with the tight time constraints of quantum devices. Thus, hardware acceleration is paramount to achieving real-time QEC. This work represents the first step in the FPGA acceleration of the Sparse Blossom Algorithm (SBA), a state-of-the-art decoding algorithm for QEC. We provide a performance profiling and a design methodology for the hardware development of the SBA. We evaluate the execution time, and energy efficiency of our solution, attaining up to 2.75× speedup and 9.59× improvement in energy efficiency compared to the software baseline.

关键词： performance evaluation Quantum computing Software algorithms Noise Quantum mechanics Energy efficiency Error correction

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DYAD: Locality-aware Data Management for accelerating Deep Learning Training

DYAD: Locality-aware Data Management for accelerating Deep L...

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international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Hariharan Devarajan Ian Lumsden Chen Wang Konstantia Georgouli Tom Scogland Jae-Seung Yeom Michela Taufer Lawrence Livermore National Laboratory University of Tennessee Knoxville

ISBN: (数字)9798350356168

ISBN: (纸本)9798350356175

Deep Learning (DL) is increasingly applied across various fields to solve complex scientific challenges in modern high-performance computing (HPC) systems that are beyond the reach of traditional algorithms. Training DL models for scientific applications involves processing multi-terabyte datasets in each epoch. The data access behavior during DL training exposes optimization opportunities to cache these datasets in near-compute storage accelerators in HPC systems, enhancing I/O throughput. However, current middleware solutions employ near-compute storage accelerators primarily as exclusive caches, which limits the effectiveness of cache access locality. To address this problem, we introduce DYAD, a system designed to maximize sample locality in the cache, thereby significantly increasing I/O throughput in HPC *** optimizes I/O for DL training based on three key features. First, DYAD boosts inter-node access speeds by using a novel streaming RPC with RDMA protocol, achieving a 1.25x performance gain over state-of-the-art solutions. Second, DYAD further enhances inter-node access by coordinating data movement, which mitigates network congestion and increases throughput for inter-node accesses by up to 8.78x. Last, DYAD uses smart metadata caching that outperforms traditional global metadata access methods by several orders of magnitude in terms of lookup throughput. We demonstrate how DYAD accelerates large-scale DL training on a high-end HPC cluster with 512 GPUs by up to 10.82x faster epochs compared to UnifyFS by performing locality-aware caching on near-compute storage accelerators.

关键词： Training Deep learning Protocols high performance computing Redundancy Termination of employment Metadata performance gain Throughput Resource management

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Testing the Unknown: A Framework for OpenMP Testing via Random Program Generation

Testing the Unknown: A Framework for OpenMP Testing via Rand...

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high performance computing, Networking, Storage and Analysis, SC-W: workshops of the international Conference for

作者： Ignacio Laguna Patrick Chapman Konstantinos Parasyris Giorgis Georgakoudis Cindy Rubio-González Center for Applied Scientific Computing Lawrence Livermore National Laboratory Department of Computer Science University of California Davis

ISBN: (数字)9798350355543

ISBN: (纸本)9798350355550

We present a randomized differential testing approach to test OpenMP implementations. In contrast to previous work that manually creates dozens of verification and validation tests, our approach is able to randomly generate thousands of tests, exposing OpenMP implementations to a wide range of program behaviors. We represent the space of possible random OpenMP tests using a grammar and implement our method as an extension of the Varity program generator. By generating 1,800 OpenMP tests, we find various performance anomalies and correctness issues when we apply them to three OpenMP implementations: GCC, Clang, and Intel. We also present several case studies that analyze the anomalies and give more details about the classes of tests that our approach creates.

关键词： Automatic programming high performance computing Conferences computer bugs Production Encoding Grammar Testing

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Graph computing on Long Vector architectures (Yes, It Works!)

Graph Computing on Long Vector Architectures (Yes, It Works!...

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IEEE international symposium on Parallel and Distributed Processing workshops and Phd Forum (IPDPSW)

作者： Pablo Vizcaino Jesus Labarta Filippo Mantovani Barcelona Supercomputing Center Barcelona Spain

ISBN: (数字)9798350364606

ISBN: (纸本)9798350364613

The HPC market is witnessing the appearance of emerging architectures exploiting long and variable vector lengths, like the NEC SX-Aurora or the RISC-V vector extension. These new architectures often require rethinking scientific algorithms to leverage their potential, and sparse computations can be the most challenging codes to adapt. Specifically, we showcase the obstacles of vectorizing graph algorithms and propose a graph representation suited for long vector architectures. We evaluate our work implementing three graph algorithms, Breadth-First-Search (BFS), Connected Components (CC), and Page Rank (PR), for a prototype RISC-V core with a long Vector Unit, presenting optimizations that benefit long vector architectures. We also run our implementations on the NEC SX-Aurora and compare our results with other graph libraries for CPUs and vector acceleration. Our BFS and CC implementations outperform CPU approaches by a factor around 4× depending on the algorithm and graph, with PR having a speedup closer to 20×. We also match or outperform the single-core performance of other vector implementations in the NEC SX-Aurora by 2× on average. We exhibit the efficiency of the RISC-V prototype, obtaining more performance out of its available bandwidth than the other evaluated single-core architectures. More generally, we show that adapting data structures and algorithms unleashes the potential of long vector architectures for sparse computations, demonstrating that these emerging technologies strive against traditional accelerated computing.

关键词： Sockets Platinum Prototypes computer architecture Bandwidth Vectors Libraries

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Towards Sustainable Post-Exascale Leadership computing

Towards Sustainable Post-Exascale Leadership Computing

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high performance computing, Networking, Storage and Analysis, SC-W: workshops of the international Conference for

作者： Woong Shin James B. White Wael Elwasif Rafael Ferreira Da Silva Christopher Zimmer Bronson Messer Reuben Budiardja Antigoni Georgiadou Verónica Melesse Vergara Jack Lange Matthias Maiterth Tim Osborne Leah Huk John Holmen Nick Hagerty Ahmad Maroof Karimi Thomas Naughton Ryan Adamson Ryan Prout Feiyi Wang Scott Atchley Kevin G. Thach Thomas Beck Sarp Oral Oak Ridge National Laboratory Oak Ridge TN USA

ISBN: (数字)9798350355543

ISBN: (纸本)9798350355550

As computing systems approach the limits of traditional silicon technology, the diminishing returns in performance per watt present a significant barrier to sustaining growth in HPC. From a large-scale scientific supercomputing facility point of view, we propose a multifaceted strategy toward specialized hardware and architectures that are optimized for energy efficiency in specific applications. We also emphasize the need for integrating energy-aware practices across all levels of HPC, from system design and software development to operational policies. We discuss strategic opportunities such as the adoption of application-specific accelerators, the development of energy-efficient algorithms, and the implementation of data-driven operational analytics. Our goal is to develop a comprehensive roadmap ensuring that future leadership systems at OLCF can meet scientific demands while operating within stringent energy budgets, thereby supporting sustainable computing growth.

关键词： Leadership Software design Software algorithms computer architecture Energy efficiency Hardware Silicon System software System analysis and design Software development management

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OpenMP Offload Features and Strategies for high performance across architectures and Compilers

OpenMP Offload Features and Strategies for High Performance ...

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IEEE international symposium on Parallel and Distributed Processing workshops and Phd Forum (IPDPSW)

作者： Arijit Bhattacharjee Christopher S. Daley Ali Jannesari Iowa State University Ames IA USA LBNL Berkeley CA USA

high performance accelerated computing has dawned in a new era of highly specialized code that depends on the target architecture. All the latest pre-exascale and exascale class supercomputers are accelerated systems. Efficient exploitation of the target architecture requires programming approaches that can take advantage of the characteristics of the hardware. OpenMP 4 introduced directives designed with the parallel architecture of GPUs in mind, but these directives are often different from those required for highest performance on CPUs. We demonstrate that by using newer OpenMP 5.0 offload features such as the loop directive and metadirective as well as profile guided strategies, we can achieve performance benefits with productivity gains. In this paper we experiment with HPGMG, a benchmark in the SPEChpc 2021 suite, to evaluate these newer directives versus OpenMP 4.5 directives, comparing performance, productivity and portability across architectural targets and production compilers on NERSC-9 Perlmutter. Our implementation gives up to a $2.74\times$ speedup compared to the baseline performance on GPUs and a $4.4\times$ speedup while running in host fallback mode. In addition, our implementation requires 66% fewer lines of code in the key kernels.

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Splash-4: A Modern Benchmark Suite with Lock-Free Constructs

Splash-4: A Modern Benchmark Suite with Lock-Free Constructs

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IEEE international symposium on Workload Characterization (IISWC)

作者： Gomez-Hernandez, Eduardo Jose Cebrian, Juan M. Kaxiras, Stefanos Ros, Alberto Univ Murcia Murcia Spain Uppsala Univ Uppsala Sweden

ISBN: (数字)9781665487986

ISBN: (纸本)9781665487986

The cornerstone for the performance evaluation of computer systems is the benchmark suite. Among the many benchmark suites used in high-performance computing and multicore research, Splash-2 has been instrumental in advancing knowledge for both academia and industry. Published in 1995 and with over 5276 citations and counting, this benchmark suite is still in use to evaluate novel architectural proposals. Recently, the Splash-3 suite eliminates important performance bugs, data races, and improper synchronization that plagued Splash-2 benchmarks after the formal definition of the C memory model. However, keeping up with architectural changes while maintaining the same workloads and algorithms (for comparative purposes) is a real challenge. Benchmark suites can misrepresent the performance characteristics of a computer system if they do not reflect the available features of the hardware and architects may end up overestimating the impact of proposed techniques or underestimating others. In this work we introduce a revised version of Splash-3, designated Splash-4, that introduces modern programming techniques to improve scalability on contemporary hardware. We then characterize Splash-3 and Splash-4 in a state-ofthe-art simulated architecture, Intel's Ice Lake with gem5-20 simulator, as well as a real contemporary hardware processor (AMD's EPYC 7002 series). Our evaluation shows that for a 64-thread execution Splash-4 reduces the normalized execution time by an average of 52% and 34% for AMD's EPYC and Intel's Ice Lake, respectively.

关键词： performance evaluation Scalability computer architecture Benchmark testing Lakes Hardware Ice

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