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Pragma driven shared memory parallelism in Zig by supporting OpenMP loop directives

Pragma driven shared memory parallelism in Zig by supporting...

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high performance computing, Networking, Storage and Analysis, SC-W: workshops of the international Conference for

作者： David Kacs Joseph Lee Justs Zarins Nick Brown EPCC University of Edinburgh Edinburgh UK

ISBN: (数字)9798350355543

ISBN: (纸本)9798350355550

The Zig programming language, which is designed to provide performance and safety as first class concerns, has become popular in recent years. Given that Zig is built upon LLVM, and-so enjoys many of the benefits provided by the ecosystem, including access to a rich set of backends, Zig has significant potential for high performance workloads. However, it is yet to gain acceptance in HPC and one of the reasons for this is that support for the pragma driven shared memory parallelism is *** this paper we describe enhancing the Zig compiler to add support for OpenMP loop directives. Then exploring performance using NASA’s NAS Parallel Benchmark (NPB) suite. We demonstrate that not only does our integration of OpenMP with Zig scale comparatively to Fortran and C reference implementations of NPB, but furthermore Zig provides up to a 1.25 times performance increase compared to Fortran.

关键词： computer languages high performance computing Conferences Ecosystems Parallel processing Benchmark testing Safety

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Fire detection method based on improved DETR 4

Fire detection method based on improved DETR

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4th international symposium on AI, ISAI 2024

作者： Ge, Ruize Hu, Xiaoyin Xiao, Duo Zhejiang University College of Contral Science and Engineering China Hangzhou City University School of Information and Electrical Engineering Hangzhou China Hangzhou City University Hangzhou School of Computer and Computing Science China

ISBN: (纸本)9798350342482

Fire, as a type of disaster, poses a significant threat to both life and property safety. Therefore, timely and accurate detection of fire occurrences is of utmost importance. However, current fire detection methods that rely on traditional sensors suffer from limitations such as a high false alarm rate and extended response time. In this manuscript, we propose a novel fire detection method based on an enhanced version of DETR that leverages flame detection. Our approach entails several key modifications. Firstly, we replace the bounding box loss function of the original DETR with the alpha-CIoU loss function. This substitution enhances the accuracy and efficiency of our fire detection method. Secondly, we introduce relative position encoding to replace the sine-cosine position encoding in the transformer module. This adjustment aims to improve the model's ability to capture spatial relationships between flame instances, resulting in more precise detection outcomes. Furthermore, we incorporate multiscale features by modifying the backbone of DETR. This addition enables our algorithm to effectively handle variations in flame sizes and appearances, contributing to improved detection performance across different fire scenarios. Finally, we apply gradient clipping to the DETR optimizer to stabilize the training process and mitigate the potential issue of exploding gradients. To evaluate our proposed method, we train and test the model using a self-generated dataset specifically tailored for flame detection. Experimental results indicate that our improved DETR algorithm achieves an average accuracy of 92.27%, which represents a substantial 3.81% enhancement over the original DETR. Moreover, through ablation experiments, we demonstrate the effectiveness of each individual improvement in our approach. © 2024 IEEE.

关键词： Premixed flames

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Functional Approximation and Approximate Parallelization with the ACCEPT compiler 33

Functional Approximation and Approximate Parallelization wit...

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33rd IEEE international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Reis, Lucas Wanner, Lucas Univ Estadual Campinas Inst Comp Campinas Brazil

ISBN: (纸本)9781665443012

Approximate computing can aid in the use of energy on cloud and mobile systems by exchanging result accuracy for faster processing times and energy efficiency. One fundamental challenge in applying approximate techniques arises when trying to identify which parts of the application are resilient to approximations, since resilience is not fixed and is dependent on the sensibility of the code. ACCEPT [1] is an approximate computing framework that applies multiple approximation techniques at the compiling level, and that presents suggestions of sections of code that could be annotated to enforce such techniques. The original ACCEPT framework applies a variety of approximation techniques, including hardware acceleration and loop perforation. This work extends ACCEPT in order to attack a broader range of applications and approximation techniques. We extend the framework to support function approximation and approximate loop parallelization. We evaluate the extended framework with seven benchmarks, showing the resulting speedup and quality degradation for each technique when applied in isolation and in combination with other approximation targets. We introduce these approximations without requiring application-level annotations. Our experiments with set benchmarks showed maximum speedups ranging from 1.22x up to 634x for the combined techniques, with quality degradation between 0% and 29%.

关键词： approximate computing energy efficiency LLVM

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Fast Hybrid Transactional Index with Scalable Phantom Avoidance

Fast Hybrid Transactional Index with Scalable Phantom Avoida...

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international symposium on computing and Networking workshops (CANDARW)

作者： Yutaro Bessho Hideyuki Kawashima Computer and Data Science Laboratories NTT Tokyo Japan Faculty of Environment and Information Studies Keio University Fujisawa Japan

ISBN: (数字)9798331505349

ISBN: (纸本)9798331505356

Griffin is a hybrid transactional index structure that combines a hash table and B+-tree. The key benefit of Griffin is that it processes single-key operations fast using the hash table. For serializable transactions, Griffin avoids phantoms with precision locking, a technique that protects updates and predicate reads with a lock. Although Griffin performs well under infrequent updates, under update-heavy workloads, the lists of locks kept by precision locking significantly grow in size, causing severe performance degradation. We identify this is because locks are released by only one thread called sync manager, which is also responsible for the heavy task of synchronizing the hash table and B+-tree. As a result, sync manager often fails to release locks as fast as they are acquired, causing the lock lists to grow. We propose a new design for Griffin, Griffin-PPL (Parallel Precision Locking), which prevents the lock lists from growing. Griffin-PPL removes sync manager, the bottlenecking thread, and parallelizes the work of releasing locks and synchronization among all transaction worker threads. To allow for parallelization, we adopt a decentralized data structure for the lock lists. Our evaluation in a microbenchmark shows that under an update-heavy workload (50% inserts, 50% scans), Griffin-PPL exhibits a throughput 6.5x the conventional Griffin architecture, at 64 threads.

关键词： Degradation Databases Conferences Phantoms Parallel processing Data structures Throughput Synchronization Indexes

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AIO: Automating I/O Optimization Pipeline for Data-Intensive Applications in HPC

AIO: Automating I/O Optimization Pipeline for Data-Intensive...

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international symposium on Parallel and Distributed Processing with Applications, ISPA

作者： Wanxin Wang Huijun Wu Lihua Yang Zhangyu Liu Bin Zheng School of Computer and Communication Engineering Changsha University of Science and Technology College of Computer Science and Technology National University of Defense Technology

ISBN: (数字)9798331509712

ISBN: (纸本)9798331509729

high-performance computing (HPC) systems has entered the exascale era, but I/O performance has lagged behind due to storage hardware limitations, creating a "storage wall effect" that hinders HPC systems full potential. Modern HPC storage systems employ a layered storage architecture with local node storage, burst buffers, and global parallel file systems to improve I/O performance. However, application workloads vary, and fast storage layers may not always outperform global parallel file systems, while a static storage software stack configuration may not achieve optimal performance across different applications. Traditional I/O optimization is time-consuming, laborintensive, and prone to human error. To address this issue, this paper proposes AIO, a data-driven I/O optimization method. AIO automatically selects the optimal storage hierarchy and software stack based on the task's I/O patterns, and further enhances performance by identifying and applying the most efficient configuration settings. We evaluated AIO with eight applications in a cluster that features shared burst buffers, local burst buffers, and a global shared file system. The experiments demonstrate that AIO effectively optimizes I/O performance, achieving an overall speedup of 2.74.

关键词： Distributed processing File systems high performance computing Pipelines Full stack Optimization methods computer architecture Hardware

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Cavity in the Loop

Cavity in the Loop

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high performance computing, Networking, Storage and Analysis, SC-W: workshops of the international Conference for

作者： David Scheunert Jonas Gehrunger Christian Hochberger Dieter Lens Harald Klingbeil Computer Systems Group Technische Universität Darmstadt Darmstadt Germany GSI Helmholtzzentrum für Schwerionenforschung GmbH Darmstadt Germany Accelerator Technology Group Technische Universität Darmstadt Darmstadt Germany

ISBN: (数字)9798350355543

ISBN: (纸本)9798350355550

Particle accelerators are physically and technically complex systems. Their operation requires demanding beam control systems. To support the development of new components in a beam phase control system for a synchrotron, we present a CGRA-based hardware/software environment that is capable of simulating the fundamental beam behaviour, leading to a hardware-in-the-loop setup. We show that this setup is able to emulate the longitudinal phase oscillations of the particle bunches in real-time.

关键词： Radio frequency high performance computing Conferences Synchrotrons Phase control Control systems Linear particle accelerator Real-time systems Oscillators Field programmable gate arrays

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Self-Aware Reliable and Reconfigurable computing Systems - An Overview

Self-Aware Reliable and Reconfigurable Computing Systems - A...

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IEEE international symposium on Parallel and Distributed Processing workshops and Phd Forum (IPDPSW)

作者： Diana Göhringer Ariel Podlubne Fabian Vargas Milos Krstic Chair of Adaptive Dynamic Systems Technische Universität Dresden Germany IHP - Leibniz Institut für innovative Mikroelektronik Frankfurt (Oder) Germany University of Potsdam Germany

ISBN: (数字)9798350364606

ISBN: (纸本)9798350364613

In demanding environments like space, avionics or robotics, computing systems face challenges affecting their life-time and reliability. Traditional approaches like static hardware redundancy prove ineffective for modern, complex systems. This work presents an overview of self-aware, reliable, and reconfig-urable computing systems leveraging Field Programmable Gate Arrays (FPGAs). Despite increasing application demands, FPGA resources remain limited, posing challenges in implementing static redundancy alongside high performance and energy efficiency. Addressing these challenges requires innovative resilience concepts, emphasizing adaptability, reliability, and energy optimization. This paper surveys existing literature and identifies open challenges in achieving resilient computing systems for demanding applications.

关键词： Surveys Redundancy Aerospace electronics Logic gates Reliability engineering Field programmable gate arrays Robots

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Leveraging Hybrid Classical-Quantum Methods for Efficient Load Rebalancing in HPC

Leveraging Hybrid Classical-Quantum Methods for Efficient Lo...

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high performance computing, Networking, Storage and Analysis, SC-W: workshops of the international Conference for

作者： Justyna Zawalska Minh Chung Katarzyna Rycerz Laura Schulz Martin Schulz Dieter Kranzlmüller Institute of Computer Science AGH University of Krakow Krakow Poland Academic Computer Center CYFRONET AGH Krakow Poland Leibniz Supercomputing Centre (LRZ) Garching bei München Germany MNM-Team Ludwig-Maximilians-Universität München (LMU) Germany Chair for Computer Architecture and Parallel Systems Technical University of Munich (TUM) Germany

ISBN: (数字)9798350355543

ISBN: (纸本)9798350355550

Load imbalance is a challenge for parallel applications in high performance computing (HPC). It is caused by processes having different execution times or load values, leading to idle or wait times at synchronization points, where faster processes must wait for the slowest process to catch up. To mitigate this issue, applications can employ load balancing (LB) strategies, which migrate load between processes to even out load. This is often referred to as the Load Rebalancing Problem (LRP). While many approaches solving the LRP exist, they can only be heuristics and hence further optimization potential exists. In our work, we turn to a novel approach by using hybrid classical-quantum approaches and present two versions of the constrained quadratic model for solving the LRP; the two differ in how they balance the number of qubits required with the types of applied constraints. We compare the quantum-based methods with classical methods using heuristic algorithms Greedy, Karmarkar–Karp, and ProactLB. We evaluate our approaches using imbalance ratio and speedup as metrics, as well as the number of migrated tasks to indicate overhead caused by migrations. Our results show that the quantum-based methods outperform the classic methods. For example, we need only 1/4 of the number of migrated tasks in a realistic use case compared with classical methods, particularly Greedy and KK, to balance the load.

关键词： Measurement Upper bound NP-hard problem high performance computing Heuristic algorithms Qubit Load management Synchronization Optimization Load modeling

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CLMS: Configurable and Lightweight Metadata Service for Parallel File Systems on NVMe SSDs 15th

CLMS: Configurable and Lightweight Metadata Service for Para...

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15th international symposium on Advanced Parallel Processing Technologies, APPT 2023

作者： Li, Qiong Lv, Shuaizhe Xie, Xuchao Song, Zhenlong College of Computer National University of Defense Technology Changsha China Defense Innovation Institute Academy of Military Sciences Beijing China

ISBN: (纸本)9789819978717

With the tendency of running large-scale data-intensive applications on high-performance computing (HPC) systems, the I/O workloads of HPC storage systems are becoming more complex, such as the increasing metadata-intensive I/O operations in Exascale computing and high-performance Data Analytics (HPDA). To meet the increasing performance requirements of the metadata service in HPC parallel file systems, this paper proposes a Configurable and Lightweight Metadata Service (CLMS) design for the parallel file systems on NVMe SSDs. CLMS introduces a configurable metadata distribution policy that simultaneously enables the directory-based and hash-based metadata distribution strategies and can be activated according to the application I/O access pattern, thus improving the processing efficiency of metadata accesses from different kinds of data-intensive applications. CLMS further reduces the memory copy and serialization processing overhead in the I/O path through the full-user metadata service design. We implemented the CLMS prototype and evaluated it under the MDTest benchmarks. Our experimental results demonstrate that CLMS can significantly improve the performance of metadata services. Besides, CMLS achieves a linear growth trend as the number of metadata servers increases for the unique-directory file distribution pattern. © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2024.

关键词： Metadata

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JANUS: A Simple and Efficient Speculative Defense using Reinforcement Learning

JANUS: A Simple and Efficient Speculative Defense using Rein...

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international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Pavlos Aimoniotis Stefanos Kaxiras Uppsala University Uppsala Sweden

ISBN: (数字)9798350356168

ISBN: (纸本)9798350356175

Speculative execution and the emergence of Spectre attacks have forced architects to rethink how microprocessors are designed. Several approaches aim to close this security vulnerability while trying to minimize performance degradation, often involving complex and sophisticated mechanisms. These strategies typically entail substantial modifications to the processor core and memory hierarchy, which ultimately inhibit their adoption in real *** this work, we leverage two of the simplest speculative defense ideas, NDA and DoM, that can co-exist in the same core, and we apply a simple form of Reinforcement Learning (RL) to select the most effective mechanism, as the underlying processor defense, for a window of execution. NDA forbids the propagation of a potential secret to subsequent instructions while DoM prohibits the creation of observable timing differences in the cache. We observe that their impact on different applications can vary significantly, but, often, they can complement each other within the same application. However, our investigation also reveals vulnerabilities in previous proposals that try to combine these secure speculation schemes into one. We demonstrate an attack scenario that violates the security of the combined scheme and we present the conditions that must hold to safely combine them. Lastly, while the cost and complexity of reinforcement learning may seem inordinately high for microarchitectural implementations, we build on recent research that demonstrates remarkably lightweight solutions, provided that the action space is *** present JANUS, a lightweight architecture leveraging an RL agent based on a two-armed bandit algorithm. JANUS selects the optimal, performance-wise, defense mechanism that protects the processor within a specific time window. We evaluate JANUS on SPEC2017 benchmark suite and find that it outperforms NDA by +4.9%, STT (a more sophisticated and complex scheme that uses taint tracking) by +1%, and DoM by +2.6

关键词： Threat modeling Reinforcement learning computer architecture Side-channel attacks Benchmark testing Timing Security Proposals Protection Optimization

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