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检索条件"任意字段=2024 International Symposium on Computer Architecture and High Performance Computing Workshops"

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Comm-bot: Generative AI for Optimising Supply Chains integrating LSTM with LLMs

Comm-bot: Generative AI for Optimising Supply Chains integra...

引用

IEEE international Conference on high performance computing workshops (HiPCW)

作者： Murugappan Venkatachalam Vijaya Dhaarshini V Chitra P Priya Thiagarajan Computer Science and Business Systems Thiagarajar College of Engineering Madurai India

ISBN: (数字)9798331509118

ISBN: (纸本)9798331509125

The objective of this paper is to improve the efficiency of supply chains in a small commerce environment. It optimises inventory management by increasing the accuracy of demand prediction and recommends suggestions in natural language. Small businesses face challenges such as budget constraints, unaffordable solutions, and a lack of forecasting expertise, which can result in stock shortages or excess inventory, impacting profitability.

关键词： Profitability Generative AI high performance computing Conferences Supply chains Natural languages Inventory management Forecasting Long short term memory Faces

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Enabling microservices management for Deep Learning applications across the Edge-Cloud Continuum 33

Enabling microservices management for Deep Learning applicat...

引用

33rd IEEE international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Houmani, Zeina Balouek-Thomert, Daniel Caron, Eddy Parashar, Manish Univ Lyon Inria Avalon Team LIP Lab UMR CNRS ENS Lyon Lyon France Univ Utah Sci Comp Imaging SCI Inst Salt Lake City UT 84112 USA

ISBN: (纸本)9781665443012

Deep Learning has shifted the focus of traditional batch workflows to data-driven feature engineering on streaming data. In particular, the execution of Deep Learning workflows presents expectations of near-real-time results with user-defined acceptable accuracy. Meeting the objectives of such applications across heterogeneous resources located at the edge of the network, the core, and in-between requires managing trade-offs between the accuracy and the urgency of the results. However, current data analysis rarely manages the entire Deep Learning pipeline along the data path, making it complex for developers to implement strategies in real-world deployments. Driven by an object detection use case, this paper presents an architecture for time-critical Deep Learning workflows by providing a data-driven scheduling approach to distribute the pipeline across Edge to Cloud resources. Furthermore, it adopts a data management strategy that reduces the resolution of incoming data when potential trade-off optimizations are available. We illustrate the system's viability through a performance evaluation of the object detection use case on the Grid'5000 testbed. We demonstrate that in a multi-user scenario, with a standard frame rate of 25 frames per second, the system speed-up data analysis up to 54.4% compared to a Cloud-only-based scenario with an analysis accuracy higher than a fixed threshold.

关键词： Cloud computing Edge computing Microservices Task allocation Real-time processing computing Continuum Deep Learning

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Laminar 2.0: Serverless Stream Processing with Enhanced Code Search and Recommendations

Laminar 2.0: Serverless Stream Processing with Enhanced Code...

引用

high performance computing, Networking, Storage and Analysis, SC-W: workshops of the international Conference for

作者： Daniel Rotchford Samuel Evans Rosa Filgueira School of Computer Science University of St Andrews EPCC University of Edinburgh

ISBN: (数字)9798350355543

ISBN: (纸本)9798350355550

This paper presents Laminar 2.0, an enhanced serverless framework for running dispel4py streaming work-flows. Building on Laminar 1.0, this version introduces improved dependency management, client-server functionality, and advanced deep learning models for semantic search. Key innovations include a structural code-to-code search using simplified parse syntax trees (SPTs) for detecting similar Processing Elements (PEs) or workflows, even from incomplete code. Additionally, Laminar 2.0 optimizes text-to-code search through better preprocessing of PEs. Our evaluation shows significant performance improvements over the previous version.

关键词： Deep learning Technological innovation Codes Semantic search high performance computing Conferences Buildings Syntactics

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Hello SME! Generating Fast Matrix Multiplication Kernels Using the Scalable Matrix Extension

Hello SME! Generating Fast Matrix Multiplication Kernels Usi...

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high performance computing, Networking, Storage and Analysis, SC-W: workshops of the international Conference for

作者： Stefan Remke Alexander Breuer Faculty of Mathematics and Computer Science Friedrich Schiller University Jena Jena Germany

ISBN: (数字)9798350355543

ISBN: (纸本)9798350355550

Modern central processing units (CPUs) feature single-instruction, multiple-data pipelines to accelerate compute-intensive floating-point and fixed-point workloads. Traditionally, these pipelines and corresponding instruction set architectures (ISAs) were designed for vector parallelism. In recent years, major hardware vendors have further increased the throughput of their CPUs by introducing matrix units with corresponding ISA extensions. The Scalable Matrix Extension (SME) has been announced for the Arm architecture in 2021 and Apple’s M4 chip is the first to support *** paper presents an in-depth study of SME on M4. Our microbenchmarks determine the maximum floating-point and fixed-point throughput of M4’s SME acceleration and study the achievable bandwidth for transfers to and from the matrix registers. Furthermore, we used the insights gained to design a just-in-time code generator for SME-based small matrix *** results presented show that M4’s SME support is FP32-centric, with an achievable throughput of over 2.3 FP32 TFLOPS. To maximize read and write bandwidth, loading and storing to and from the matrix registers must be done in two steps. Our just-in-time generated small matrix multiplication kernels outperform the vendor-optimized BLAS implementation in almost all tested configurations.

关键词： Instruction sets Pipelines Loading computer architecture Bandwidth Parallel processing Throughput Vectors Registers Kernel

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Circular Reconfigurable Parallel Processor for Edge computing : Industrial Product ✶

Circular Reconfigurable Parallel Processor for Edge Computin...

引用

Annual international symposium on computer architecture, ISCA

作者： Yuan Li Jianbin Zhu Yao Fu Yu Lei Toshio Nagata Ryan Braidwood Haohuan Fu Juepeng Zheng Wayne Luk Hongxiang Fan AzurEngine Technologies Tsinghua University Sun Yat-Sen University Imperial College London University of Cambridge

ISBN: (数字)9798350326581

ISBN: (纸本)9798350326598

Graphics Processing Units (GPUs) have emerged as the predominant hardware platforms for massively parallel computing. However, their inherent von-Neumann architecture still suffers performance inefficiency stemming from the sequential instruction execution and frequent data transfer overheads within the memory system. These intrinsic architectural flaws lead to heavy overhead on the latency, area, and energy efficiency, rendering GPUs suboptimal for edge computing applications. To tackle these challenges, this paper introduces a novel circular Reconfigurable Parallel Processor (RPP) to enable massively parallel applications in edge computing with high efficiency. RPP features a novel circular array of reconfigurable compute engines, enabling efficient streaming dataflow processing. In contrast to traditional Coarse Grained Reconfigurable architecture (CGRA), the circular network topology of RPP is formed by linear switch networks with an innovative gasket memory, which reduces complicated network routing overheads while allowing versatile datapath mapping and optimized data reuse. A dedicated hierarchical memory system is proposed to support different memory access patterns and address mapping strategies, enabling flexible data access with high memory efficiency. Several hardware optimizations are further introduced to improve hardware utilization and performance such as concurrent kernel execution, register split&refill and heterogeneous scalar&vector computing. To fully utilize the hardware capability of RPP, we develop an end-to-end software stack consisting of a compiler, runtime environment, and different RPP libraries. This software stack is designed to be compatible with the GPGPU computing paradigm, enhancing its potential for broader adoption. Fabricated in a 14nm process, RPP occupies an area of 119 mm 2 and operates at a maximum power of 15W with a 1GHz clock frequency. From the runtime measurement of various workloads, RPP achieves up to 27.5 × higher

关键词： Runtime environment Memory management Gaskets Full stack Switches Linear algebra Hardware

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Shelf schedules for independent moldable tasks to minimize the energy consumption 33

Shelf schedules for independent moldable tasks to minimize t...

引用

33rd IEEE international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Benoit, Anne Canon, Louis-Claude Elghazi, Redouane Heam, Pierre-Cyrille ENS Lyon LIP Lyon France Univ Bourgogne Franche Comte FEMTO ST Inst CNRS Besancon France

ISBN: (纸本)9781665443012

Scheduling independent tasks on a parallel platform is a widely-studied problem, in particular when the goal is to minimize the total execution time, or makespan (P parallel to C-max problem in Graham's notations). Also, many applications do not consist of sequential tasks, but rather parallel moldable tasks that can decide their degree of parallelism at execution (i.e., on how many processors they are executed). Furthermore, since the energy consumption of data centers is a growing concern, both from an environmental and economical point of view, minimizing the energy consumption of a schedule is a main challenge to be addressed. One can then decide, for each task, on how many processors it is executed, and at which speed the processors are operated, with the goal to minimize the total energy consumption. We further focus on co-schedules, where tasks are partitioned into shelves, and we prove that the problem of minimizing the energy consumption remains NP-complete when static energy is consumed during the whole duration of the application. We are however able to provide an optimal algorithm for the schedule within one shelf, i.e., for a set of tasks that start at the same time. Several approximation results are derived, and simulations are performed to show the performance of the proposed algorithms.

关键词： Energy consumption Schedules Program processors Costs high performance computing Parallel processing Approximation algorithms

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Edge Rendering architecture for multiuser XR Experiences and E2E performance Assessment

Edge Rendering Architecture for multiuser XR Experiences and...

引用

IEEE international symposium on Broadband Multimedia Systems and Broadcasting (BMSB)

作者： Inhar Yeregui Daniel Mejías Guillermo Pacho Roberto Viola Jasone Astorga Mario Montagud Fundaci´on Vicomtech Basque Research and Technology Alliance San Sebastián Spain Department of Communications Engineering University of the Basque Country Bilbao Spain i2CAT Foundation and Universitat de València Barcelona Spain

ISBN: (数字)9798350364262

ISBN: (纸本)9798350364279

Holographic communications are gaining ground among emerging eXtended-Reality (XR) applications due to their potential to revolutionize human communication. However, these technologies are characterized by higher requirements in terms of Quality of Service (QoS), such as high transmission data rates, very low latency, and high computation capacity, challenging current achievable capabilities. In this context, computation offloading techniques are being investigated, where resource-intensive computational tasks, like rendering XR experiences, are shifted from user devices to a separate processor, specifically an Edge computing instance. This paper introduces an Edge Rendering architecture for multiuser XR experiences, implements it on top of widely employed XR and Web technologies, and proposes a method based on image and audio processing to evaluate its performance in terms of end-to-end media streaming latency, inter-device, and intra-media synchronization when employing different access networks.

关键词： performance evaluation Extended reality Image edge detection Quality of service computer architecture Streaming media Rendering (computer graphics)

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Parallel Katz Centrality On Evolving Graphs

Parallel Katz Centrality On Evolving Graphs

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IEEE international Conference on high performance computing workshops (HiPCW)

作者： Dishit Sharma Prajjwal Nijhara Dip Sankar Banerjee Department of Computer Science and Engineering Indian Institute of Technology Jodhpur India

ISBN: (数字)9798331509118

ISBN: (纸本)9798331509125

Katz centrality measures a node’s influence within a network, considering the total number of walks between pairs of nodes rather than solely the shortest paths. This paper presents an algorithm for dynamically updating Katz centrality scores as the underlying graph evolves. Our method employs a frontier-based breadth-first search (BFS) to efficiently derive updated Katz scores in dynamic graphs. Notably, our algorithm accommodates node insertions and deletions, addressing a significant limitation of current state-of-the-art methods.

关键词： Heuristic algorithms high performance computing Conferences

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Realizing the AMD Exascale Heterogeneous Processor Vision : Industry Product

Realizing the AMD Exascale Heterogeneous Processor Vision : ...

引用

Annual international symposium on computer architecture, ISCA

作者： Alan Smith Gabriel H. Loh Michael J. Schulte Mike Ignatowski Samuel Naffziger Mike Mantor Mark Fowler Nathan Kalyanasundharam Vamsi Alla Nicholas Malaya Joseph L. Greathouse Eric Chapman Raja Swaminathan Advanced Micro Devices Inc.

ISBN: (数字)9798350326581

ISBN: (纸本)9798350326598

AMD had previously detailed its exascale research journey from initial targets and requirements to the development and evolution of its vision of a high-performance computing (HPC) accelerated processing unit (APU), dubbed the Exascale Heterogeneous Processor or EHP. At the conclusion of that work, the learnings were integrated into the design of the node architecture that went into the Frontier supercomputer, the world’s first exascale machine. However, while the Frontier node architecture embodied many of the attributes of the EHP concept, advanced heterogeneous integration capabilities at the time were not yet sufficiently mature to realize our vision of a fully-integrated APU for HPC and AI. In this paper, we finish the EHP’s story by digging deeper into why an APU was not the right solution at the time of our first exascale architecture, what the shortcomings were of previous EHP concepts, and how AMD further evolved the concept into the AMD Instinct™ MI300A APU. MI300A is the culmination of years of AMD developments in advanced packaging technologies, its APU hardware and software, and the next step in our highly effective chiplet strategy to not only deliver a groundbreaking design for exascale computing, but to also meet the demands of new large-language model and generative AI applications.

关键词： Reviews Generative AI Linux Multichip modules computer architecture Production Trademarks

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An FPGA-based Ultra-high performance and Scalable Optical Flow Hardware Accelerator for Autonomous Driving

An FPGA-based Ultra-High Performance and Scalable Optical Fl...

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IEEE international symposium on Circuits and Systems (ISCAS)

作者： Ye Liu Shuang Hao Kun Huang Minghui Yang Zili Huang Xiuyuan Qi Yiting Li Liang Zhou Yu Long Jun Zhou University of Electronic Science and Technology of China Chengdu China

ISBN: (数字)9798350330991

ISBN: (纸本)9798350331004

Optical flow plays an extremely important role in the field of computer vision and extremely high real-time performance is required especially in autonomous driving. Traditional optical flow methods generally improve the accuracy of optical flow through the image pyramid technique. However, the introduction of the image pyramid increases the computational complexity. Additionally, the data relationships between pyramid layers result in strong data dependencies, making it difficult to accelerate using parallel processing, and it is challenging to meet real-time requirements in practical scenarios. To address this issue, in this paper, we propose an FPGA-based ultra-high performance and scalable optical flow hardware accelerator with several techniques, including an adaptive optical flow computation technique based on dynamic direction prediction to reduce computation without accuracy degradation, a highly scalable computing architecture with configurable numbers of PEs to improve the flexibility and hardware utilization under different hardware resource constraints, and a reconfigurable pyramid-layer pipeline technique to improve performance and reduce memory size. The proposed hardware accelerator was implemented and evaluated on a Xilinx FPGA ZCU104 achieving ultra-high performance (405 FPS) while maintaining high accuracy (AEE 0.64).

关键词： Degradation Accuracy Ultraviolet sources Pipelines computer architecture Dynamic scheduling Real-time systems

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