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检索条件"任意字段=2024 International Symposium on Computer Architecture and High Performance Computing Workshops"

共 5212 条记录，以下是71-80 订阅

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Efficient Tree-based Parallel Algorithms for N-Body Simulations Using C++ Standard Parallelism 24

Efficient Tree-based Parallel Algorithms for N-Body Simulati...

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Proceedings of the SC '24 workshops of the international Conference on high performance computing, Network, Storage, and Analysis

作者： Thomas Lane Cassell Tom Deakin Aksel Alpay Vincent Heuveline Gonzalo Brito Gadeschi School of Computer Science University of Bristol Bristol UK Engineering Mathematics and Computing Lab Interdisciplinary Center for Scientific Computing Heidelberg University Heidelberg Germany GPU Architecture NVIDIA Munich Germany

ISBN: (纸本)9798350355543

The Barnes-Hut approximation for N-body simulations reduces the time complexity of the naive all-pairs approach from O(N2) to O(N log N) by hierarchically aggregating nearby particles into single entities using a tree data structure. This inherently irregular algorithm poses substantial challenges for performance portable implementations on multi-core CPUs and GPUs. We introduce two portable fully-parallel Barnes-Hut implementation strategies that trade-off different levels of GPU support for performance: an unbalanced concurrent octree, and a balanced bounding volume hierarchy sorted by a Hilbert spacefilling curve. We implement these algorithms in portable ISO C++ using parallel algorithms and concurrency primitives like atomics. The results demonstrate competitive performance on a range of CPUs and GPUs. Additionally, they highlight the effectiveness of the par execution policy for highly concurrent irregular algorithms, outperforming par_unseq on CPUs and GPUs with Independent Thread Scheduling.

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BOSS: Blocking algorithm for optimizing shuttling scheduling in Ion Trap

BOSS: Blocking algorithm for optimizing shuttling scheduling...

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IEEE symposium on high-performance computer architecture

作者： Xian Wu Chenghong Zhu Jingbo Wang Xin Wang The Hong Kong University of Science and Technology (Guangzhou) Beijing Academy of Quantum Information Sciences

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Ion traps stand at the forefront of quantum hardware technology, presenting unparalleled benefits for quantum computing, such as high-fidelity gates, extensive connectivity, and prolonged coherence times. In this context, we explore the critical role of shuttling operations within these systems, especially their influence on the fidelity loss and elongated execution times. To address these challenges, we have developed BOSS, an efficient blocking algorithm tailored to enhance shuttling efficiency. This optimization not only bolsters the shuttling process but also elevates the overall efficacy of ion trap devices. We experimented on multiple applications using two qubit gates up to 4000+ and qubits ranging from 64 to 78. Our method significantly reduces the number of shuttles on most applications, with a maximum reduction of $96.1 \%$. Additionally, our investigation includes simulations of realistic experimental parameters that incorporate sympathetic cooling, offering a higher fidelity and a refined estimate of execution times that align more closely with practical scenarios.

关键词： Superconducting devices Fault tolerance Processor scheduling Qubit Fault tolerant systems computer architecture Logic gates Ions Scheduling Optimization

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AccelES: Accelerating Top-K SpMV for Embedding Similarity via Low-bit Pruning

AccelES: Accelerating Top-K SpMV for Embedding Similarity vi...

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IEEE symposium on high-performance computer architecture

作者： Jiaqi Zhai Xuanhua Shi Kaiyi Huang Chencheng Ye Weifang Hu Bingsheng He Hai Jin National Engineering Research Center for Big Data Technology and System/Services Computing Technology and System Lab/Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China School of Computing National University of Singapore Singapore

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

In the realm of recommendation systems, achieving real-time performance in embedding similarity tasks is often hindered by the limitations of traditional Top-K sparse matrix-vector multiplication (SpMV) methods, which suffer from high latency due to inefficient memory access patterns. This paper identifies these critical gaps and introduces AccelES, a novel approach that significantly enhances the efficiency of Top-K SpMV. Our method employs a two-stage calculation scheme: the first stage utilizes a compact, low-bit dataset to quickly identify the most relevant entries, while the second stage performs full-precision calculations solely on this pruned subset, thereby minimizing computational overhead. Furthermore, AccelES incorporates innovative matrix representations, Ultra-CSR and Random-CSR, which optimize memory bandwidth utilization. Experimental results demonstrate that AccelES accelerates performance, surpassing state-of-the-art FPGA, GPU, and CPU solutions by factors of 3.4×, 2.5×, and 153.3×, respectively, under controlled conditions. These advancements not only enhance processing speed but also significantly improve real-time performance in recommendation systems, establishing AccelES as a pivotal contribution to the field of Top-K sparse matrix-vector multiplication.

关键词： Quantization (signal) high dimensional data Memory management Graphics processing units Bandwidth Real-time systems Sparse matrices Recommender systems Field programmable gate arrays Optimization

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BrokenSleep: Remote Power Timing Attack Exploiting Processor Idle States

BrokenSleep: Remote Power Timing Attack Exploiting Processor...

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IEEE symposium on high-performance computer architecture

作者： Hyosang Kim Ki-Dong Kang Gyeongseo Park Seungkyu Lee Daehoon Kim DGIST ETRI Yonsei University

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Power and energy consumption emerge as critical aspects in computing systems, spanning from mobile devices to data-center servers. Modern processors typically support idle states (i.e., C-states), which deactivate specific hardware components, in addition to offering multiple voltage and frequency states (i.e., P-states). While C-states can significantly reduce static power when processor cores are idle, a notable security vulnerability arises due to differences in wake-up latency among various C-states when the processor cores become active again. This paper proposes a security vulnerability arising from processor idle state management, called BrokenSleep, which exploits the aforementioned wake-up latency differences to create covert and side-channel between computing nodes connected via an external network. This study presents the first remote timing attack based on power management, overcoming the limitations of previous research that required the co-location of attacker and victim applications on the same local machine. This advancement significantly extends the range of existing remote timing attacks by integrating power-related factors. Regardless of the computing system types, our experiments demonstrate that an attacker can transfer data to remote machines without direct network access and deduce the keystroke timing. This vulnerability is not confined to a single processor architecture; it affects processors designed by both Intel and ARM, indicating a widespread potential risk across different hardware platforms.

关键词： Program processors Power system management computer architecture Voltage Hardware Mobile handsets Energy efficiency Timing Servers Security

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Multi-Dimensional Vector ISA Extension for Mobile In-Cache computing

Multi-Dimensional Vector ISA Extension for Mobile In-Cache C...

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IEEE symposium on high-performance computer architecture

作者： Alireza Khadem Daichi Fujiki Hilbert Chen Yufeng Gu Nishil Talati Scott Mahlke Reetuparna Das University of Michigan Institute of Science Tokyo

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

In-cache computing technology transforms existing caches into long-vector compute units and offers low-cost alternatives to building expensive vector engines for mobile CPUs. Unfortunately, existing long-vector Instruction Set architecture (ISA) extensions, such as RISC-V Vector Extension (RVV) and Arm Scalable Vector Extension (SVE), provide only onedimensional strided and random memory accesses. While this is sufficient for typical vector engines, it fails to effectively utilize the large Single Instruction, Multiple Data (SIMD) widths of incache vector engines. This is because mobile data-parallel kernels expose limited parallelism across a single dimension. Based on our analysis of mobile vector kernels, we introduce a long-vector Multi-dimensional Vector ISA Extension (MVE) for mobile in-cache computing. MVE achieves high SIMD resource utilization and enables flexible programming by abstracting cache geometry and data layout. The proposed ISA features multi-dimensional strided and random memory accesses and efficient dimension-level masked execution to encode parallelism across multiple dimensions. Using a wide range of data-parallel mobile workloads, we demonstrate that MVE offers significant performance and energy reduction benefits of $2.9 \times$ and $8.8 \times$, on average, compared to the SIMD units of a commercial mobile processor, at an area overhead of 3.6%.

关键词： Single instruction multiple data Instruction sets Memory management Layout Transforms Programming Vectors Resource management Kernel Engines

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Serverless computing for Dynamic HPC Workflows 24

Serverless Computing for Dynamic HPC Workflows

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Proceedings of the SC '24 workshops of the international Conference on high performance computing, Network, Storage, and Analysis

作者： Vijay Thurimella Philipp Raith Rolando P. Hong Enriquez Anderson Andrei Da Silva Gourav Rattihalli Ada Gavrilovska Dejan Milojicic School of Computer Science Georgia Institute of Technology Atlanta USA and Hewlett Packard Labs Hewlett Packard Enterprise Milpitas CA Hewlett Packard Labs Hewlett Packard Enterprise Milpitas CA School of Computer Science Georgia Institute of Technology Atlanta USA

ISBN: (纸本)9798350355543

Containers have become an important component for scientific workflows, enhancing reproducibility, portability, and isolation when coupled with workflow management systems. However, integrating containers with these systems can be complex, potentially hindering wider adoption. Serverless platforms offer a solution by providing a layer of abstraction over container orchestrators, simplifying management while introducing event-driven capabilities. This paper presents a novel integration of serverless with workflow management systems to optimize scientific workflow execution. Our approach leverages serverless functions to dynamically provision containers for workflow tasks, resulting in up to 30% faster execution. We found that performance can be further improved by reusing containers between multiple different tasks that were provisioned by the serverless platform. These findings demonstrate the utility of combining specialized container orchestration with established workflow management to streamline scientific computing, improve resource utilization, and accelerate time-to-results. Server-less' event-driven architecture enables efficient resource scaling, aligning with the dynamic nature of scientific workloads.

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Examining the Viability of Row-Scale Disaggregation for Production Applications 24

Examining the Viability of Row-Scale Disaggregation for Prod...

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Proceedings of the SC '24 workshops of the international Conference on high performance computing, Network, Storage, and Analysis

作者： Curtis Shorts Ryan E. Grant Electrical and Computer Engineering Department Queen's University Kingston Ontario Canada

ISBN: (纸本)9798350355543

Row-scale Composable Disaggregated Infrastructure (CDI) is a heterogeneous high performance computing (HPC) architecture that relocates the GPUs to a single chassis which CPU nodes can then request compute resources from. This is a distinctly different architecture from rack-scaled CDI as the GPUs are accessed over a network rather than existing in the same PCIe domain as the CPUs. Row-scale CDI expands the benefits and flexibility of rack-scaled CDI, while introducing new challenges. For example, with row-scale CDI, one must account for the effects of "slack", a latency in the CPU-to-GPU communication times due to network delays. This work seeks to assess potential challenges with row-scale CDI to determine which factors are most important to consider when deploying a CDI system. Our strong scaling application analyses reveal that there are two types of HPC workloads that may benefit from row-scale CDI; those that are CPU dominant and periodically call on the GPU to do highly parallel tasks and those that are GPU dominant and primarily rely on the CPU to coordinate work. We perform comparisons between the kernel and data transfer characteristics of each application to a slack proxy application which allowed for the development of a mathematical model to predict the performance penalty different applications can face as a result of slack. To illustrate this we profile two applications using our proposed method and find that they pessimistically would see a less than a 1% performance penalty above the effects of crossing the network in an environment which induced 100 of slack, or a distance of 20 km at the speed of light in a fibre optic network cable. This demonstrates that both row-scale and cluster-scale CDI are viable technologies from an application performance perspective.

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Hardware-Accelerated Event-Graph Neural Networks for Low-Latency Time-Series Classification on SoC FPGA 21st

Hardware-Accelerated Event-Graph Neural Networks for Low-La...

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21st international symposium on Applied Reconfigurable computing, ARC 2025

作者： Nakano, Hiroshi Blachut, Krzysztof Jeziorek, Kamil Wzorek, Piotr Dampfhoffer, Manon Mesquida, Thomas Nishi, Hiroaki Kryjak, Tomasz Dalgaty, Thomas Graduate School of Science and Technology Keio University Tokyo Japan Embedded Vision Systems Group Computer Vision Laboratory AGH University of Krakow Krakow Poland CEA-List Université Grenoble Alpes Grenoble France

ISBN: (纸本)9783031879944

As the quantities of data recorded by embedded edge sensors grow, so too does the need for intelligent local processing. Such data often comes in the form of time-series signals, based on which real-time predictions can be made locally using an AI model. However, a hardware-software approach capable of making low-latency predictions with low power consumption is required. In this paper, we present a hardware implementation of an event-graph neural network for time-series classification. We leverage an artificial cochlea model to convert the input time-series signals into a sparse event-data format that allows the event-graph to drastically reduce the number of calculations relative to other AI methods. We implemented the design on a SoC FPGA and applied it to the real-time processing of the Spiking Heidelberg Digits (SHD) dataset to benchmark our approach against competitive solutions. Our method achieves a floating-point accuracy of 92.7% on the SHD dataset for the base model, which is only 2.4% and 2% less than the state-of-the-art models with over 10× and 67× fewer model parameters, respectively. It also outperforms FPGA-based spiking neural network implementations by 19.3% and 4.5%, achieving 92.3% accuracy for the quantised model while using fewer computational resources and reducing latency. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2025.

关键词： event-based audio processing FPGA graph convolutional neural networks dynamic audio sensor artificial cochlea

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ER-DCIM: Error-Resilient Digital CIM architecture with Run-Time MAC-Cell Error Correction

ER-DCIM: Error-Resilient Digital CIM Architecture with Run-T...

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IEEE symposium on high-performance computer architecture

作者： Zhen He Yiqi Wang Zihan Wu Shaojun Wei Yang Hu Fengbin Tu Shouyi Yin School of Integrated Circuits BNRist Tsinghua University Beijing China The Hong Kong University of Science and Technology Hong Kong China

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Digital computing-in-memory (CIM) is an emerging solution to break through the limitations of memory wall by integrating digital logic into SRAM, which is able to achieve high area and energy efficiency with no accuracy loss. Digital CIM’s SRAM cells are still prone to errors like conventional SRAM due to noise and variation, especially under low-voltage operation for high energy efficiency. The SRAM cell errors cause multiplyaccumulation (MAC) result errors, which may seriously damage the neural network inference accuracy. However, traditional SRAM’s error correcting code (ECC) that corrects errors in one read-out row is incompatible with digital CIM, which reads out multiple rows simultaneously for computation. Detecting and correcting computational MAC errors and SRAM cell errors (i.e., MAC-cell errors) in digital CIM remain largely *** address digital CIM’s unique MAC-cell error resilience needs, we propose ER-DCIM, an error-resilient digital CIM with run-time MAC-cell error correction to guarantee computation correctness. The proposed residue code-based MAC error correction mechanism is the first to correct additive errors in the MAC result in real time during DCIM computation. Then, we propose a progressive cell error correction mechanism to correct underlying cell error in a timely manner, avoiding performance loss due to stalling computation. Further, we design a mode switcher to repurpose redundant error-resilient logic reserved for low-voltage mode to improve performance in high-voltage mode. Experimental results show that the proposed techniques enable digital CIM to maintain high throughput and energy efficiency without accuracy loss in both low-voltage and high-voltage modes.

关键词： Low voltage Accuracy Microprocessors high-voltage techniques In-memory computing SRAM cells Energy efficiency Common Information Model (computing) Error correction codes Resilience

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GoPIM: GCN-Oriented Pipeline Optimization for PIM Accelerators

GoPIM: GCN-Oriented Pipeline Optimization for PIM Accelerato...

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IEEE symposium on high-performance computer architecture

作者： Siling Yang Shuibing He Wenjiong Wang Yanlong Yin Tong Wu Weijian Chen Xuechen Zhang Xian-He Sun Dan Feng The State Key Laboratory of Blockchain and Data Security Zhejiang University Zhejiang Lab Hangzhou High-Tech Zone (Binjiang) Institute of Blockchain and Data Security Zhejiang Key Laboratory of Big Data Intelligent Computing Washington State University Vancouver Illinois Institute of Technology Huazhong University of Science and Technology Wuhan National Laboratory for Optoelectronics

ISBN: (数字)9798331506476

ISBN: (纸本)9798331506483

Graph convolutional networks (GCNs) are popular for a variety of graph learning tasks. ReRAM-based processing-in-memory (PIM) accelerators are promising to expedite GCN training owing to their in-situ computing capability. However, existing accelerators can be severely underutilized even with pipelines, due to the oversight of the skewed execution times of various GCN stages and the ignorance of skewed degrees of graph vertices. In this work, we propose GOPIM, a GCN-oriented pipeline optimization for PIM accelerators to expedite GCN training. First, GOPIM proposes an ML-based scheme that allocates crossbar resources to the most needed stages to streamline the overall pipeline. Second, GOPIM utilizes a selective vertex updating technique that evenly distributes vertices on crossbars by interleaved mapping. These techniques collectively reduce the overall execution time without losing much accuracy. We also provide a practical architecture design for GOPIM. Our experimental results show that, GoPIM achieves up to 191 × speedup and 16.1 × energy saving, compared to the state-of-the-art work.

关键词： Training Accuracy Graph convolutional networks Pipelines Energy conservation computer architecture Machine learning Parallel processing Optimization

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