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Selected papers from the 18^th international conference on field programmable logic and applications (fpl 2008)

IET COMPUTERS AND DIGITAL TECHNIQUES 2010年第3期4卷 157-158页

作者： Kebschull, Udo Platzner, Marco Teich, Juergen Univ Appl Sci Karlsruhe Germany Univ Leipzig Leipzig Germany Univ Heidelberg Dept Phys & Astron D-6900 Heidelberg Germany 2008 Int Conf Field Programmable Log Heidelberg Germany ETH Comp Engn & Networks Lab Zurich Switzerland UC Berkeley Dept Elect Engn & Comp Sci EECS DSP Design Grp Prof EA Lee & DG Messerschmitt Ptolemy Project PostDoc Berkeley CA USA ETH Commun Networks Lab TIK Zurich Switzerland ETH Inst Comp Engn Zurich Switzerland Univ Paderborn Elect Engn & Informat Technol Dept Paderborn Germany Univ Erlangen Nurnberg Dept Comp Sci D-8520 Erlangen Germany

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An FPGA-based transverse multibunch feedback system for diamond light source

An FPGA-based transverse multibunch feedback system for diam...

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20th international conference on field programmable logic and applications, fpl 2010

作者： Uzun, Isa Heron, Mark Morgan, Alun Rehm, Guenther Diamond Light Source Harwell Science and Innovation Campus Oxfordshire OX11 0DE United Kingdom

ISBN: (纸本)9780769541792

this paper describes the design and implementation of an FPGA-based transverse multibuch feedback system for Diamond Light Source. the system is designed to damp instabilities of the electron beam up to 250 MHz in both horizontal and vertical planes. the feedback algorithm and diagnostics features are implemented and verified using Sys-temVerilog HDL language on a Xilinx XCV2P30 FPGA. © 2010 IEEE.

关键词： field programmable gate arrays (FPGA)

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A compact transactional memory multiprocessor system on FPGA

A compact transactional memory multiprocessor system on FPGA

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20th international conference on field programmable logic and applications, fpl 2010

作者： Pusceddu, Matteo Ceccolini, Simone Palermo, Gianluca Sciuto, Donatella Tumeo, Antonino Politecnico di Milano Dipartimento di Elettronica e Informazione Milano Italy Pacific Northwest National Laboratory High Performance Computing Richland WA United States

ISBN: (纸本)9780769541792

In this paper we present a rapid prototyping platform on a single field programmable Gate Array (FPGA) with support for software transactional memory. the system is composed only by off-the-shelf cores and is useful for porting and early validation of programs to the transactional memory programming model. We discuss the implementation of the software layer of this platform, propose an analysis of the system and compare it to a hardware lock based multiprocessor architecture, showing the trade-offs in terms of performance and programming complexity. © 2010 IEEE.

关键词： field programmable gate arrays (FPGA)

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A cost-effective technique for mapping BLUTs to QLUTs in FPGAs

A cost-effective technique for mapping BLUTs to QLUTs in FPG...

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20th international conference on field programmable logic and applications, fpl 2010

作者： Ritt, Marcus Lisboa, Carlos Arthur Lang Carro, Luigi Lazzari, Cristiano Instituto de Informática PPGC - UFRGS Brazil ALGOS - INESC-ID Portugal

ISBN: (纸本)9780769541792

Quaternary logic has shown to be a promising alternative for implementing FPGAs, since voltage mode quaternary circuits can reduce the circuits' cost and at the same time reduce its power consumption. In this paper, we study the implementation of circuits in quaternary logic. To obtain cost-effective implementations of quaternary circuits, we propose a mapping from binary to quaternary circuits based on integer linear programming. Our results show that the expected improvements can be achieved, reducing, in average, the number of transistors by 27% and the number of nets by 19%, compared to a binary implementation. © 2010 IEEE.

关键词： field programmable gate arrays (FPGA)

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Degradation analysis and mitigation in FPGAs

Degradation analysis and mitigation in FPGAs

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20th international conference on field programmable logic and applications, fpl 2010

作者： Stott, Edward Wong, Justin S.J. Cheung, Peter Y.K. Department of Electrical and Electronic Engineering Imperial College London London United Kingdom

ISBN: (纸本)9780769541792

FPGAs are powerful platforms for investigating impending challenges associated with process scaling, such as variation and degradation. their versatility allows us to gather empirical data and evaluate novel solutions. We carried out accelerated-life tests on modern FPGA devices and obtained a useful characterisation of the ageing processes that afflict them. We also quantified the potential benefits of three degradation mitigation strategies based on exploiting spare logic and interconnect resources. the work helps cement the role of reconfigurable logic as a vitally-important technology in the face of the uncertainties of future process scaling. © 2010 IEEE.

关键词： field programmable gate arrays (FPGA)

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thermal gradient aware clock skew scheduling for FPGAs

Thermal gradient aware clock skew scheduling for FPGAs

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20th international conference on field programmable logic and applications, fpl 2010

作者： Bae, Sungmin Vijaykrishnan, N. Department of Computer Science and Engineering Pennsylvania State University University Park PA 16802 United States

ISBN: (纸本)9780769541792

FPGAs are gradually becoming an essential flexible-digital solution for automotive and military applications, where operating at extreme ambient temperature conditions reaching 125°C are not uncommon. Operating FPGAs under such high-temperature environments require adequate timing margin to compensate potential delay increase, which worsens the performance of FPGAs. To minimize the performance degradation, we propose a thermal gradient aware clock skew scheduling technique which allocates temperature-adaptive timing margins considering worst case thermal gradients and junction temperature ranges of logic-paths in the design, instead of assigning a worst case timing margin to the entire design. the experimental results shows that our technique extends the operating ambient temperature range with an average about 20% performance im-provement1. © 2010 IEEE.

关键词： field programmable gate arrays (FPGA)

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On the feasibility of TERO-based true random number generator on Xilinx FPGAs 30

On the feasibility of TERO-based true random number generato...

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30th international conference on field-programmable logic and applications (fpl)

作者： Fujieda, Naoki Aichi Inst Technol Dept Elect & Elect Engn Fac Engn Toyota Aichi Japan

ISBN: (纸本)9781728199023

A True Random Number Generator (TRNG) is an essential component for security applications of FPGAs. Its requirements include small logic area, high throughput, sufficient randomness backed with a mathematical model, and feasibility - ease of implementation. this paper focuses on TRNGs based on a Transition Effect Ring Oscillator (TERO) and presents a three-path configurable TERO (TC-TERO), an improved implementation of TERO that achieves high feasibility with a minimal amount of hardware. According to the evaluation with a Xilinx Artix-7 FPGA, a TC-TERO with a 20-bit configurable parameter only required 40 LUTs. By selecting one of the promising parameters, the proposed TRNG passed AIS-31 Procedure A without post-processing and NIST SP 800-22 with a simple debiasing.

关键词： Random number generation field programmable gate arrays Transition effect ring oscillator AIS-31

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Pipelined FPGA adders

Pipelined FPGA adders

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20th international conference on field programmable logic and applications, fpl 2010

作者： De Dinechin, Florent Nguyen, Hong Diep Pasca, Bogdan LIP Projet Arénaire ENS de Lyon 46 allée d'Italie 69364 Lyon Cedex 07 France

ISBN: (纸本)9780769541792

Integer addition is a universal building block, and applications such as quad-precision floating-point or elliptic curve cryptography now demand precisions well beyond 64 bits. this study explores the trade-offs between size, latency and frequency for pipelined large-precision adders on FPGA. It compares three pipelined adder architectures: the classical pipelined ripple-carry adder, a variation that reduces register count, and an FPGA-specific implementation of the carry-select adder capable of providing lower latency additions at a comparable price. For each of these architectures, resource estimation models are defined, and used in an adder generator that selects the best architecture considering the target FPGA, the target operating frequency, and the addition bit width. © 2010 IEEE.

关键词： field programmable gate arrays (FPGA)

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Flexible and modular support for timing functions in high performance networking acceleration

Flexible and modular support for timing functions in high pe...

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20th international conference on field programmable logic and applications, fpl 2010

作者： Neely, Christopher Brebner, Gordon Shang, Weijia Xilinx Research Labs Xilinx Inc. San Jose United States Computer Engineering Department Santa Clara University Santa Clara United States

ISBN: (纸本)9780769541792

field programmable logic is increasingly used to provide the high performance and flexible acceleration needed for network processing functions at multiple gigabit/second rates. Almost all such functions feature the use of clocks and timers in control and/or data roles, and these are typically implemented in an ad hoc manner. this paper introduces a set of three configurable timing modules that are based on abstractions of the prevalent timing paradigms observed in network protocols. the modules fit within the experimental ShapeUp methodology for modular FPGA-based system design, and so can be easily integrated with other modules that are tailored for specific networking functions. the use and benefits of the new modular approach are demonstrated by an example of a flexible FPGA reference design that has been made available for real-life use by telecommunication equipment providers. © 2010 IEEE.

关键词： field programmable gate arrays (FPGA)

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field programmable gate array implementation of parts-based object detection for real time video applications

Field programmable gate array implementation of parts-based ...

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20th international conference on field programmable logic and applications, fpl 2010

作者： Goshorn, Deborah Cho, Junguk Kastner, Ryan Mirzaei, Shahnam Department of Computer Science and Engineering University of California San Diego San Diego CA United States Department of Electrical and Computer Engineering University of California Santa Barbara Santa Barbara CA United States

ISBN: (纸本)9780769541792

the emergence of smart cameras has been fueled by increasingly advanced computing platforms that are capable of performing a variety of real-time computer vision algorithms. Smart cameras provide the ability to understand their environment. Object detection and behavior classification play an important role in making such observations. this paper presents a high-performance FPGA implementation of a generalized parts-based object detection and classifier that runs with capability of 266 frames/sec. the detection algorithm is easily reconfigured by simply loading a new representation into on-board memory, i.e., the FPGA can detect and classify a newly specified object and behavior without any changes to the hardware implementation. © 2010 IEEE.

关键词： field programmable gate arrays (FPGA)

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