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检索条件"任意字段=20th International Conference on Field Programmable Logic and Applications, FPL 2010"

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A scalable, high-performance motion estimation application for a weakly-programmable FPGA architecture

A scalable, high-performance motion estimation application f...

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20th international conference on field programmable logic and applications, fpl 2010

作者： Sahlbach, Henning Whitty, Sean Bende, Oliver Ernst, Rolf Institute of Computer and Network Engineering Technische Universität Braunschweig Braunschweig Germany

ISBN: (纸本)9780769541792

Computer architectures for advanced driver assistance systems have become increasingly important in the automotive industry. they target safety-critical applications, which process large amounts of incoming sensor data. this is especially the case for image processing applications, which must handle several uncompressed image streams from multiple cameras. As one possible target architecture, FPGAs provide sufficient processing power for complex applications such as lane or object detection. A particularly challenging application is the reliable detection of moving objects, which is the basis for several future driver assistance applications, such as a digital 3D reconstruction of a vehicle's surroundings. this paper presents an advanced Motion Estimation application, which achieves high performance processing of up to 449 FPS for an image resolution of 512×384 pixels. the implementation concept relies on weakly-programmable processing elements and a reconfigurable data path, which allows an efficient exploitation of the FPGA's chip area and clock frequencies, leading to a flexible solution that fits future application requirements. © 2010 IEEE.

关键词： Image resolution

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COGRE: A configuration memory reduced reconfigurable logic cell architecture for area minimization

COGRE: A configuration memory reduced reconfigurable logic c...

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20th international conference on field programmable logic and applications, fpl 2010

作者： Okamoto, Yasuhiro Ichinomiya, Yoshihiro Amagasaki, Motoki Iida, Masahiro Sueyoshi, Toshinori Graduate School of Science and Technology Kumamoto University 2-39-1 Kurokami Kumamoto 860-8555 Japan

ISBN: (纸本)9780769541792

Because of the redundancy factors of FPGAs, there is a performance gap between FPGAs and ASICs. In this paper, we propose a small-memory logic cell, COGRE, to minimize the FPGA area. Our approach is to investigate the appearance ratio of the logic functions in a circuit implementation. Moreover, we group the logic functions on the basis of the NPN-equivalence class. the results of our investigation show that only small portions of the NPN-equivalence class can cover large portions of the logic functions used to implement circuits. Further, we found that NPN-equivalence classes with a high appearance ratio can be implemented by using a small number of AND gates, OR gates, and NOT gates. On the basis of this observation, we develop 5-input and 6-input COGRE architectures composed of several NAND gates and programmable inverters. the experimental results show that the logic area in 6-COGRE is 46.3% smaller than that in 6-LUT. the logic area of 5-COGRE is 32.6% smaller than that of 5-LUT and 10.0% smaller than that of 4-LUT. Further, the total number of configuration memory bits in 6-COGRE is 32.1% smaller than the number of configuration memory bits in 6-LUT. © 2010 IEEE.

关键词： field programmable gate arrays (FPGA)

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Enhancing FPGA device capabilities by the automatic logic mapping to additive carry chains

Enhancing FPGA device capabilities by the automatic logic ma...

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20th international conference on field programmable logic and applications, fpl 2010

作者： Preußer, thomas B. Spallek, Rainer G. Institute of Computer Engineering Technische Universität Dresden Dresden Germany

ISBN: (纸本)9780769541792

this paper presents an approach to the automatic mapping of arbitrary combinational circuits to the arithmetic carry-chain structures widely available in modern FPGAs. this capability is highly valuable as it enables the utilization of these fast special-purpose structures for general-purpose logic. the described approach is both automatic and generally applicable to all carry-chain architectures designed for binary addition. It, thus, lifts severe constraints left by previous works. It helps to reduce the pressure on the general-purpose routing resources and accelerates critical logic paths. the proposed mapping is further shown to enhance the logic capability of a logic block containing a k-input lookup table (k-LUT) to implement many (k +1)-input functions on common FPGA architectures. this, in particular, also applies to all logic functions with a non-inverting path as introduced by Anderson and Wang [1]. this makes their envisioned gains in logic density achievable even on current devices without requiring their architectural extension. the benefits of the carry-chain mapping are experimentally evaluated on the basis of combinational MCNC benchmarks. It is shown how carry chains can be recovered within a functional standard mapping and that a device mapping aware of carry chains achieves a reduction of the combinational delay of about a 20 percent. © 2010 IEEE.

关键词： field programmable gate arrays (FPGA)

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Using hard macros to reduce FPGA compilation time

Using hard macros to reduce FPGA compilation time

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20th international conference on field programmable logic and applications, fpl 2010

作者： Lavin, Christopher Padilla, Marc Ghosh, Subhrashankha Nelson, Brent Hutchings, Brad Wirthlin, Michael Dept. of Electrical and Computer Engineering Brigham Young University Provo UT 84602 United States

ISBN: (纸本)9780769541792

the FPGA compilation process (synthesis, map, placement, routing) is a time-consuming process that limits designer productivity. Compilation time can be reduced by using pre-compiled circuit blocks (hard macros). Hard macros consist of previously synthesized, mapped, placed and routed circuitry that can be relatively placed with short tool runtimes and that make it possible to reuse previous computational effort. Two experiments were performed to demonstrate feasibility that hard macros can reduce compilation time. these experiments demonstrated that an augmented Xilinx flow designed specifically to support hard macros can reduce overall compilation time by 3×. though the process of incorporating hard macros in designs is currently manual and error-prone, it can be automated to create compilation flows with much lower compilation time. © 2010 IEEE.

关键词： field programmable gate arrays (FPGA)

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High density asynchronous LUT based on non-volatile MRAM technology

High density asynchronous LUT based on non-volatile MRAM tec...

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20th international conference on field programmable logic and applications, fpl 2010

作者： Chaudhuri, Sumanta Zhao, Weisheng Klein, Jacques-Oliver Chappert, Claude Mazoyer, Pascale IEF Univ. Paris-Sud Orsay F-91405 France CNRS Orsay F-91405 France STMicroelectronics 850 Rue Jean Monnet Crolles Grenoble 38026 France

ISBN: (纸本)9780769541792

In this article, we present the architecture design of high-performance Asynchronous Look Up Table (LUT) embedded with a non-volatile Magnetic RAM (MRAM) as the configuration memory, called MALUT. It promises a number of advantages over the traditional FPGA circuits such as "free" standby power, high operating frequency and instant on/off etc. thanks to the 3D integration and high density of MRAM, fine-grain run-time reconfiguration and multi-context configuration can be achieved. An automatic design flow has been developed for the design of complex hybrid CMOS/MRAM circuits. Based on CMOS 130nm and MRAM 120nm technology, mixed simulations and layout implementation have been done to demonstrate the expected operation and configuration performances. At last, we discuss and conclude. © 2010 IEEE.

关键词： field programmable gate arrays (FPGA)

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FPGA-optimised uniform Random Number Generators using LUTS and shift registers

FPGA-optimised uniform Random Number Generators using LUTS a...

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20th international conference on field programmable logic and applications, fpl 2010

作者： thomas, David B. Luk, Wayne Imperial College London United Kingdom

ISBN: (纸本)9780769541792

FPGA-optimised Random Number Generators (RNGs) are more resource efficient than software-optimised RNGs, as they can take advantage of bit-wise operations and FPGA-specific features. However, it is difficult to concisely describe FPGA-optimised RNGs, so they are not commonly used in real-world designs. this paper describes a new type of FPGA RNG called a LUT-SR RNG, which takes advantage of bit-wise XOR operations and the ability to turn LUTs into shift-registers of varying lengths. this provides a good resource-quality balance compared to previous FPGA-optimised generators, between the previous high-resource high-quality LUT-FIFO RNGs and low-resource low-quality LUT-OPT RNGs. the LUT-SR generators can also be expressed using a simple C++ algorithm contained within the paper, allowing 60 fully-specified LUT-SR RNGs with different characteristics to be embedded in the paper, backed up by an online set of VHDL generators and test-benches. © 2010 IEEE.

关键词： field programmable gate arrays (FPGA)

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Detecting patterns in various size and angle using FPGA

Detecting patterns in various size and angle using FPGA

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20th international conference on field programmable logic and applications, fpl 2010

作者： Suzuki, Masayuki Tanida, Yoshifumi Maruyama, Tsutomu Systems and Information Engineering University of Tsukuba 1-1-1 Ten-ou-dai Tsukuba Ibaraki 305-8573 Japan

ISBN: (纸本)9780769541792

In this paper, we describe an approach for detecting patterns in various size and angle using FPGA. In many approaches, features of a given pattern which are invariant to scaling and/or rotation are defined in advance, and those features are searched in a given image. these approaches make it possible to narrow down the candidate regions with less computational cost, but the sensitivity depends on how to define the features. In our approach, the image is downscaled by αk and αl along the x and y axes (k,l = 0,1,2,, n), and the regions in the downscaled images are compared with several sequences of the templates which are generated from the given pattern using direct cross-correlation. this approach requires high computational cost, but by calculating the cross-correlations incrementally starting from the non-rotated pattern, it becomes possible to detect the rotated patterns in various size and angle with one FPGA. © 2010 IEEE.

关键词： field programmable gate arrays (FPGA)

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Breaking elliptic curve cryptosystems using reconfigurable hardware

Breaking elliptic curve cryptosystems using reconfigurable h...

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20th international conference on field programmable logic and applications, fpl 2010

作者： Fan, Junfeng Bailey, Daniel V. Batina, Lejla Güneysu, Tim Paar, Christof Verbauwhede, Ingrid ESAT/SCD-COSIC Katholieke Universiteit Leuven IBBT Kasteelpark Arenberg 10 B-3001 Leuven-Heverlee Belgium Horst Görtz Institute for IT Security Ruhr University Bochum Germany RSA Security Division of EMC United States Radboud University Nijmegen Netherlands

ISBN: (纸本)9780769541792

this paper reports a new speed record for FPGAs in cracking Elliptic Curve Cryptosystems. We conduct a detailed analysis of different F2m multiplication approaches in this application. A novel architecture using optimized normal basis multipliers is proposed to solve the Certicom challenge ECC2K-130. We compare the FPGA performance against CPUs, GPUs, and the Sony PlayStation 3. Our implementations show low-cost FPGAs outperform even multicore desktop processors and graphics cards by a factor of 2. © 2010 IEEE.

关键词： field programmable gate arrays (FPGA)

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Customised Pearlmutter Propagation: A Hardware Architecture for Trust Region Policy Optimisation 27

Customised Pearlmutter Propagation: A Hardware Architecture ...

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27th international conference on field programmable logic and applications (fpl)

作者： Shao, Shengjia Luk, Wayne Imperial Coll London Dept Comp London England

ISBN: (纸本)9789090304281

Reinforcement Learning (RL) is an area of machine learning in which an agent interacts with the environment by making sequential decisions. the agent receives reward from the environment to find an optimal policy that maximises the reward. Trust Region Policy Optimisation (TRPO) is a recent policy optimisation algorithm that achieves superior results in various RL benchmarks, but is computationally expensive. this paper proposes Customised Pearlmutter Propagation (CPP), a novel hardware architecture that accelerates TRPO on FPGA. We use the Pearlmutter Algorithm to address the key computational bottleneck of TRPO in a hardware efficient manner, avoiding symbolic differentiation with change of variables. Experimental evaluation using robotic locomotion benchmarks demonstrates that the proposed CPP architecture implemented on Stratix-V FPGA can achieve up to 20 times speed-up against 6-threaded Keras deep learning library with theano backend running on a Core i7-5930K CPU.

关键词： Hardware field programmable gate arrays Optimization Machine learning Computer architecture Benchmark testing Acceleration

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Robust FPGA design under variations

Robust FPGA design under variations

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20th international conference on field programmable logic and applications, fpl 2010

作者： Kumar, Akhilesh Anis, Mohab Department of Electrical and Computer Engineering University of Waterloo 200 University Avenue West Waterloo ON N2L 3G1 Canada

ISBN: (纸本)9780769541792

this paper briefly describes the PhD research work on Robust FPGA Design Under Variations. the work proposes design techniques in three primary areas, viz., power yield enhancement, timing yield enhancement and IR-drop reduction. An architecture and CAD enhancement technique is proposed for improving the timing yield of FPGAs under process variations. Two different techniques are proposed for improving the power yield of FPGAs under process variations. the first technique reduces spatial correlation among leaking blocks to reduce leakage variability, whereas the second technique sizes the transistors of the buffers in the interconnects to reduce leakage variability. For IR-drop reduction, two different CAD techniques are proposed. the first design methodology is an IR-drop aware place and route technique which reduces local switching activities in a region to reduce IR-drops. the second approach is an IR-drop aware clustering methodology. this methodology reduces the clustering of high switching activity nets in a logic cluster to improve the supply voltage profile. © 2010 IEEE.

关键词： field programmable gate arrays (FPGA)

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