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检索条件"任意字段=20th International Conference on Field Programmable Logic and Applications, FPL 2010"

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HIGH-SPEED REGULAR EXPRESSION MATCHING ENGINE USING MULTI-CHARACTER NFA

HIGH-SPEED REGULAR EXPRESSION MATCHING ENGINE USING MULTI-CH...

引用

18th international conference on field programmable and logic applications

作者： Yamagaki, Norio Sidhu, Reetinder Kamiya, Satoshi NEC Corp Ltd Syst IP Core Res Labs Kawasaki Kanagawa Japan Satyam Comp Serv Ltd Appl Res Grp Bangalore Karnataka India

ISBN: (纸本)9781424419609

An approach is presented for high throughput matching of regular expressions (regexes) by first converting them into corresponding Non-deterministic Finite Automata (NFAs) which are then configured onto a FPGA. the key novel feature is a technique that, for any given regex, constructs an NFA that processes multiple characters per clock cycle. An efficient algorithm is proposed that outputs an NFA which processes twice the number of characters as the input one. A technique is also proposed that implements the range match operation (e.g. [a-z]) efficiently. A program has been written that implements above ideas to convert regexes into NFAs specified in a structural Hardware Design Language (HDL), which are then mapped onto a FPGA. Performance is evaluated using real world regexes (Snort ruleset). the results demonstrate the practical utility of the approach. For example, for a set of 2,691 regexes, while the standard 1-character NFA obtains a throughput of 1.25 Gbps, our 4-character NFA achieves a throughput of 3.63 Gbps, while requiring only 20% more LUTs and 6% less flip-flops.

关键词： field programmable gate arrays (FPGA)

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MetaWire: using FPGA configuration circuitry to emulate a network-on-chip

MetaWire: using FPGA configuration circuitry to emulate a ne...

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18th international conference on field programmable and logic applications

作者： Shelburne, M. Patterson, C. Athanas, P. Jones, M. Martin, B. Fong, R. Virginia Tech Bradley Dept Elect & Comp Engn Configurable Comp Lab Blacksburg VA 24061 USA

ISBN: (纸本)9781424419616

Although there have been many reported implementations of networks-on-chip (NoCs) on FPGAs, they have not seen the same acceptance as NoCs on ASICs. One reason is that communication on a field programmable gate array (FPGA) is already costly because of the die resources and time delays inherent in the reconfigurable structure. Layering another general-purpose network on top of the reconfigurable network simply incurs too many performance penalties. there is, however, already a largely unused, global network available in FPGAs. As a proof-of-concept, we demonstrate that the Xilinx FPGA configuration circuitry, which is normally idle during system operation, can function as a relatively high-performance NoC. MetaWire performs transfers through an overclocked Virtex-4 internal configuration access port and is shown to provide a bandwidth exceeding 200 MB/s.

关键词： field programmable gate arrays (FPGA)

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Exploring alternative 3D FPGA architectures: Design methodology and cad tool support

Exploring alternative 3D FPGA architectures: Design methodol...

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17th international conference on field programmable logic and applications

作者： Siozios, K. Sotiriadis, K. Pavlidis, V. F. Soudris, D. Democritus Univ Thrace Dept Elect & Comp Engn Thrace Greece Univ Rochester Dept Elect & Comp Engn Rochester NY 14627 USA

ISBN: (纸本)9781424410590

this paper introduces a software supported methodology for exploring/evaluating 3D FPGA architectures. Two new CAD tools are developed: (i) the 3DPRO for placement and routing on 3D FPGAs and (ii) the 3DPower for power/energy estimation on such architectures. We mainly focus our exploration on the total number of layers and the amount of vertical interconnects (or vias). the efficiency of the proposed architecture is evaluated by making an exhaustive exploration for via connections under the EnergyxDelay Product criterion. Experimental results demonstrate the effectiveness of our solution, considering the 20 largest MCNC benchmarks. Considering 3D architectures with 4 layers and two scenarios of fabricated via densities (30% and 70%), we achieve an average decrease in the delay, the wire length, and the energy consumption of 18%, 17%, and 31%, respectively, as compared to 2D FPGAs. We also achieved high utilization of vias links.

关键词： field programmable gate arrays (FPGA)

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Proceedings - 2010 international conference on field programmable logic and applications, fpl 2010: Message from the conference chairs

Proceedings - 2010 International Conference on Field Program...

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Proceedings - 2010 international conference on field programmable logic and applications, fpl 2010 2010年 xv页

作者： Ferrandi, Fabrizio Santambrogio, Marco D. Nurmi, Jari Politecnico di Milano Italy Tampere University of Technology Finland

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Proceedings - 2010 international conference on field programmable logic and applications, fpl 2010: Message from the steering committee

Proceedings - 2010 International Conference on Field Program...

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Proceedings - 2010 international conference on field programmable logic and applications, fpl 2010 2010年 xvi页

作者： Lysaght, Patrick Luk, Wayne Cheung, Peter Y.K. Xilinx Inc. United States Imperial College London United Kingdom

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GMS: Generic Memristive Structure for Non-Volatile FPGAs 20

GMS: Generic Memristive Structure for Non-Volatile FPGAs

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20th IFIP/IEEE international conference on Very Large Scale Integration (VLSI-SoC)

作者： Gaillardon, Pierre-Emmanuel Sacchetto, Davide Bobba, Shashikanth Leblebid, Yusuf De Micheli, Giovanni Ecole Polytech Fed Lausanne LSI Lausanne Switzerland Ecole Polytech Fed Lausanne LSM Lausanne Switzerland

ISBN: (纸本)9781467326582

the invention of the memristor enables new possibilities for computation and non-volatile memory storage. In this paper we propose a Generic Memristive Structure (GMS) for 3-D FPGA applications. the GMS cell is demonstrated to be utilized for steering logic useful for multiplexing signals, thus replacing the traditional pass-gates in FPGAs. Moreover, the same GMS cell can be utilized for programmable memories as a replacement for the SRAMs employed in the look-up tables of FPGAs. A fabricated GMS cell is presented and its use in FPGA architecture is demonstrated by the area and delay improvement for several architectural benchmarks.

关键词： field programmable gate arrays (FPGA)

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Dynamically optimizing FPGA applications by monitoring temperature and workloads

Dynamically optimizing FPGA applications by monitoring tempe...

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20th international conference on VLSI Design held jointly with the 6th international conference on Embedded Systems

作者： Jones, Phillip H. Cho, Young H. W. Lockwood, John Washington Univ Appl Res Lab St Louis MO 63130 USA

ISBN: (纸本)9780769527628

In the past, field programmable Gate Array (FPGA) circuits only contained a limited amount of logic and operated at a low frequency. Few applications running on FPGAs consumed excessive power Today, the temperature of FPGAs are a major concern due to increased logic density and speed. Large applications with highly pipelined datapaths can ultimately generate more heat than the package can dissipate. For FPGAs that operate in controlled environments, heat sinks and fans can be used to effectively dissipate heat from the device. However, FPGA devices operating under harsher thermal conditions in outdoor environments, or in systems with malfunctioning cooling systems need a thermal management control system. To address this issue, we had previously devised a reconfigurable temperature monitoring system that gives feedback to the FPGA circuit using the measured junction temperature of the device. Using this feedback, we designed a novel dual frequency switching system that allows the FPGA circuits to maintain the highest level of throughput performance for a given maximum junction temperature. this paper extends the previous work by additionally making this adaptive frequency mechanism workload aware and evaluating power and latency performance under bursty workload conditions. Our working system has been implemented on the field programmable Port Extender (FPX) platform developed at Washington University in St. Louis. Experimental results with a scalable image correlation circuit show up to a 30% saving in power for bursty workloads and up to a 2x factor improvement in latency performance as compared to a system without thermal or workload feedback. Our circuit provides power efficient high performance processing of bursty workloads, while ensuring the device always operates within a safe temperature range.

关键词： field programmable gate arrays (FPGA)

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A real-time stereo vision system with FPGA

A real-time stereo vision system with FPGA

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13th international conference on field-programmable logic and applications (fpl 2003)

作者： Miyajima, Y Maruyama, T Univ Tsukuba Inst Engn Mech & Syst Tsukuba Ibaraki 3058573 Japan

ISBN: (纸本)3540408223

In this paper, we describe a compact stereo vision system which consists of one off-the-shelf FPGA board with one FPGA. this system supports (1) camera calibration for easy use and for simplifying the circuit, and (2) left-right consistency check for reconstructing correct 3-D geometry from the images taken by the cameras. the performance of the system is limited by the calibration (which is, however, a must for practical use) because only one pixel data can be allowed to read in owing to the calibration. the performance is;however, 20 frame per second (when the size of images is 640 x 480, and 80 frames per second when the size of images is 320 x 240), which is fast enough for practical use such as vision systems for autonomous robots. this high performance can be realized by the recent progress of FPGAs and wide memory access to external RAMs (eight memory banks) on the FPGA board.

关键词： field programmable gate arrays (FPGA)

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FPGA-based emulation: Industrial and custom prototyping solutions 10th

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10th international conference on field-programmable logic and applications, fpl 2000

作者： Krupnova, Helena Saucier, Gabriele Institut National Polytechnique de Grenoble/CSI 46 Avenue Felix Viallet Grenoble cedex38031 France

ISBN: (纸本)3540678999

the given paper presents the state of the art in the FPGA based logic emulation. the analysis of the existing emulation solutions is performed according to the following classification: (1) large emulation systems (Quickturn [26], Ikos [16], MentorGraphics [21]);(2) semi-custom rapid prototyping boards (Aptix [3], Simutech [24]);(3) custom prototyping solutions (Transmogrifier2 [20], Weaver [6], Replica [18], FPGA vendors demonstration and prototyping boards [31], [2], microprocessor-based boards, etc.). Each system is exposed in terms of its capacity, architecture, used FPGAs and performance. © Springer-Verlag Berlin Heidelberg 2000.

关键词： field programmable gate arrays (FPGA)

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thE ROLE OF FPGA-BASED ARCHITECTURES IN thE CONTROL ROOM MODERNIZATION PROCESS: PRELIMINARY RESULTS OF A CASE-STUDY

THE ROLE OF FPGA-BASED ARCHITECTURES IN THE CONTROL ROOM MOD...

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20th international conference on Nuclear Engineering and the ASME 2012 Power conference (ICONE20-POWER2012)

作者： Cappelli, M. Memmi, F. Falconi, L. Palomba, M. Bove, R. Sepielli, M. ENEA Casaccia UTFISST Rome Italy

ISBN: (纸本)9780791844984

In the context of a plant modernization, developing digital I&C technology is a crucial challenge to improve nuclear plants safety and reliability. Digital technology is usually oriented to achieve functions such as plant control, monitoring, simulation and protection in a user-friendly way. On the other hand, the analogue instrumentation implemented in the so-called "old generation consoles" is often essential and not immediately or completely replaceable. As a consequence, the interaction between the analogue and digital data seems to be a necessary step before starting the digital I&C licensing process. the fundamental difference between analogue and digital technologies relies on the fact that digital logic is based on processors, hence it can be customized by programming its software. However, introducing new code can result in a new set of potential failure modes to be accounted for As a consequence, original analogue systems mostly assure a higher level of protection with respect to digital systems. In this scenario, a benefit could arise from the use of field-programmable Gate Arrays (FPGAs), based on a hardware architecture whose routing is made via software, thus resulting in a variety of possible tasks. FPGAs' employment ranges from automotive and industrial applications, ASIC prototyping, software defined radios, radar, image and DSP. In this work a critical analysis of FPGA fundamental features and potentialities in nuclear plant I&C design is achieved in conjunction with some practical applications. Troubles arising from coping with processor-based system are presented and compared to benefits and potentialities offered by FPGA real-time architectures: indeed, FPGAs comprise a higher number of logic blocks and functions able to manage parallel processes with self triggering, and provided into a "non-frozen" structure but easily reconfigurable. this characteristics of being in-system programmable (ISP), i.e. a device capable of being programmed while re

关键词： field programmable gate arrays (FPGA)

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