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Modelling Moral Reasoning and Ethical Responsibility with logic programming 20th

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20th international conference on logic for programming, Artificial Intelligence and Reasoning (LPAR)

作者： Berreby, Fiona Bourgne, Gauvain Ganascia, Jean-Gabriel Univ Paris 06 LIP6 4 Pl Jussieu F-75005 Paris France

ISBN: (纸本)9783662488997;9783662488980

In this paper, we investigate the use of high-level action languages for representing and reasoning about ethical responsibility in goal specification domains. First, we present a simplified Event Calculus formulated as a logic program under the stable model semantics in order to represent situations within Answer Set programming. Second, we introduce a model of causality that allows us to use an answer set solver to perform reasoning over the agent's ethical responsibility. We then extend and test this framework against the Trolley Problem and the Doctrine of Double Effect. the overarching aim of the paper is to propose a general and adaptable formal language that may be employed over a variety of ethical scenarios in which the agent's responsibility must be examined and their choices determined. Our fundamental ambition is to displace the burden of moral reasoning from the programmer to the program itself, moving away from current computational ethics that too easily embed moral reasoning within computational engines, thereby feeding atomic answers that fail to truly represent underlying dynamics.

关键词： logic programming

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Automatic Test Case Generation for PLC Programs using Coverage Metrics 20

Automatic Test Case Generation for PLC Programs using Covera...

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20th IEEE conference on Emerging Technologies and Factory Automation (ETFA)

作者： Simon, Hendrik Friedrich, Nico Biallas, Sebastian Hauck-Stattelmann, Stefan Schlich, Bastian Kowalewski, Stefan Rhein Westfal TH Aachen Embedded Software Lab Aachen Germany ABB Corp Res Germany Ladenburg Germany

ISBN: (纸本)9781467379298

this paper presents a method for automatic test case generation for PLC software following the IEC61131-3 standard. the core component is a model checker that iteratively creates program traces, each of them covering a part of the program in terms of a coverage metric. these test cases are translated into Structured Text, a programming languages defined in the IEC61131-3, to allow the execution on a soft-PLC or the actual hardware. Our approach is evaluated on a set of function blocks that are used in industry. We demonstrate that test cases can be automatically generated within few seconds in most cases.

关键词： CASING INSPECTION Automatic testing Programmable logic controllers Coverage Metronidazole Legal Executions

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Exploiting Multicore Processors in PLCs using Libraries for IEC 61131-3 20

Exploiting Multicore Processors in PLCs using Libraries for ...

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20th IEEE conference on Emerging Technologies and Factory Automation (ETFA)

作者： Specht, Felix Flatt, Holger Eickmeyer, Jens Niggemann, Oliver Fraunhofer IOSB INA Applicat Ctr Ind Automat Langenbruch 6 D-32657 Lemgo Germany

ISBN: (纸本)9781467379298

this paper presents an approach for exploiting multicore hardware architectures on coding level for the IEC 61131-3. An interface between the IEC 61131-3 code and software of a different programming language outsources the actual parallel workload. For validation purpose, an embedded multicore hardware is used as a controlling device, which executes software for the use case of model based condition monitoring. the case study results show an explicit benefit of the multicore exploiting software in comparison to its singlecore counterpart, which is reflected with a faster processing of up to a factor of 3. Overall, this approach can be used for developing high performance applications or for accelerating existing applications in industry.

关键词： Multi-core processors Programmable logic controllers international Electrotechnical Commission Outcome Studies Control apparatus computer software Libraries PROCESSOR

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Integrated supplier selection and order allocation under uncertainty in agile supply chains 20

Integrated supplier selection and order allocation under unc...

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20th IEEE conference on Emerging Technologies and Factory Automation (ETFA)

作者： Dotoli, Mariagrazia Epicoco, Nicola Falagario, Marco Politecn Bari Dept Elect & Informat Engn Bari Italy Politecn Bari Dept Math Mech & Management Bari Italy

ISBN: (纸本)9781467379298

this paper focuses on the supplier selection problem and the subsequent order allocation, extending an approach originally proposed by some of the authors for supplier ranking under uncertainty. the novel method integrates the cross-efficiency Data Envelopment Analysis and the fuzzy set theory to obtain a ranking of suppliers under nondeterministic evaluation criteria. Subsequently, a fuzzy integer linear programming model allows determining the quantities to require from each supplier as a compromise between the suppliers' efficiency, procurement costs, and time required to fulfill the order, while respecting the suppliers' capacity and satisfying the customers' demand. the case study of an SME manufacturer shows the technique effectiveness.

关键词： supplier selection order allocation agile supply chain manufacturing uncertainty data envelopment analysis fuzzy logic

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An Adequate Compositional Encoding of Bigraph Structure in Linear logic with Subexponentials 1

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20th international conference on logic for programming, Artificial Intelligence and Reasoning (LPAR)

作者： Chaudhuri, Kaustuv Reis, Giselle Ecole Polytech Inria Palaiseau France Ecole Polytech LIX Palaiseau France

ISBN: (数字)9783662488997

ISBN: (纸本)9783662488997;9783662488980

In linear logic, formulas can be split into two sets: classical (those that can be used as many times as necessary) or linear (those that are consumed and no longer available after being used). Subexponentials generalize this notion by allowing the formulas to be split into many sets, each of which can then be specified to be classical or linear. this flexibility increases its expressiveness: we already have adequate encodings of a number of other proof systems, and for computational models such as concurrent constraint programming, in linear logic with subexponentials (SEL). Bigraphs were proposed by Milner in 2001 as a model for ubiquitous computing, subsuming models of computation such as CCS and the pi-calculus and capable of modeling connectivity and locality at the same time. In this work we present an encoding of the bigraph structure in SEL, thus giving an indication of the expressive power of this logic, and at the same time providing a framework for reasoning and operating on bigraphs. Our encoding is adequate and therefore the operations of composition and juxtaposition can be performed on the logical level. Moreover, all the proof-theoretical tools of SEL become available for querying and proving properties of bigraph structures.

关键词： Encoding (symbols)

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A Labelled Sequent Calculus for Intuitionistic Public Announcement logic 1

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20th international conference on logic for programming, Artificial Intelligence and Reasoning (LPAR)

作者： Nomura, Shoshin Sano, Katsuhiko Tojo, Satoshi Japan Adv Inst Sci & Technol Sch Informat Sci Japan Advanced Institute Ishikawa Japan

ISBN: (数字)9783662488997

ISBN: (纸本)9783662488997;9783662488980

Intuitionistic Public Announcement logic (IntPAL) proposed by Ma et al. (2014) aims at formalizing changes of an agent's knowledge in a constructive manner. IntPAL can be regarded as an intuitionistic generalization of Public Announcement logic (PAL) whose modal basis is the intuitionistic modal logic IK by Fischer Servi (1984) and Simpson (1994). We also refer to IK for the basis of this paper. Meanwhile, Nomura et al. (2015) provided a cut-free labelled sequent calculus based on the study of Maffezioli et al. (2010). In this paper, we introduce a labelled sequent calculus for IntPAL (we call it GIntPAL) as both an intuitionistic variant of GPAL and a public announcement extension of Simpson's labelled calculus, and show that all theorems of the Hilbert axiomatization of IntPAL are also derivable in GIntPAL with the cut rule. then we prove the admissibility of the cut rule in GIntPAL and also the soundness result for birelational Kripke semantics. Finally, we derive the semantic completeness of GIntPAL as a corollary of these theorems.

关键词： Calculations

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Foundational Extensible Corecursion A Proof Assistant Perspective 2015

Foundational Extensible Corecursion A Proof Assistant Perspe...

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20th ACM SIGPLAN international conference on Functional programming (ICFP)

作者： Blanchette, Jasmin Christian Popescu, Andrei Traytel, Dmitriy Inria Nancy France LORIA Nancy France Max Planck Inst Informat D-66123 Saarbrucken Germany Middlesex Univ Sch Sci & Technol Dept Comp Sci London N17 8HR England Tech Univ Munich D-80290 Munich Germany

ISBN: (纸本)9781450336697

this paper presents a formalized framework for defining corecursive functions safely in a total setting, based on corecursion up-to and relational parametricity. the end product is a general corecursor that allows corecursive (and even recursive) calls under "friendly" operations, including constructors. Friendly corecursive functions can be registered as such, thereby increasing the corecursor's expressiveness. the metatheory is formalized in the Isabelle proof assistant and forms the core of a prototype tool. the corecursor is derived from first principles, without requiring new axioms or extensions of the logic.

关键词： theory Verification (Co)recursion parametricity proof assistants higher-order logic Isabelle

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20th international conference on Methods and Models in Automation and Robotics (MMAR)

作者： Chmiel, Miroslaw Hrynkiewicz, Edward Polok, Dariusz Mocha, Jan Silesian Tech Univ Inst Elect Gliwice Poland ITAM Inst Med Technol & Equipment Zabrze Poland

ISBN: (纸本)9781479987016

Over the recent decades a common approach seems to be taken for granted that only dedicated Central Processing Unit (CPU) offered as self-contained modules by various manufacturers are the only solution for implementation of Programmable logic Controllers (PLC). To demonstrate right the contrary authors of this study reveal various CPU solutions of PLCs developed on the basis of some typical microcontrollers, including the ones from the families MCS-51, AVR and ARM with the Cortex M3 core. these CPUs were then employed to run a control program developed in an Instruction List (IL) language that meets recommendations of the IEC-61131-3 standard. the paper demonstrates that the basic operators of the IL language can be used to simplify bodies of the standard defined function and function blocks. the rules are outlined that the authors adhered to at development of commands for the IL language with dedicated examples that explain how these commands can be used to define functionalities for operational modules of counters and timers and a combinational Boolean function - on the example of the LIMIT procedure. It is also suggested to define several new operators that additionally simplify the notation. the scope of investigations includes also comparison between the solutions suggested by stipulations of the standard in question and the own solutions proposed by the authors with presentation of the outcome from the comparison. the disclosed considerations served as the basis to suggest the new architecture for a CPU that is suitable for operation in line with rules imposed by the standard, but on the other hand it can be used for operation with some modifications suggested by the authors and intended to reduce processing time for some operators, Boolean functions and functional blocks.

关键词： Central Processing Unit Programmable logic Controller Language Operators Microprocessor Control programming Languages Microprogramming Control Program

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Focused Labeled Proof Systems for Modal logic 1

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20th international conference on logic for programming, Artificial Intelligence and Reasoning (LPAR)

作者： Miller, Dale Volpe, Marco Ecole Polytech Inria F-75230 Paris France Ecole Polytech LIX F-75230 Paris France

ISBN: (数字)9783662488997

ISBN: (纸本)9783662488997;9783662488980

Focused proofs are sequent calculus proofs that group inference rules into alternating positive and negative phases. these phases can then be used to define macro-level inference rules Gentzen's original and tiny introduction and structural rules. We show here that the inference rules of labeled proof systems for modal logics can similarly be described as pairs of such phases within the LKF focused proof system for first-order classical logic. We consider the system G3K of Negri for the modal logic K and define a translation from labeled modal formulas into first-order polarized formulas and show a strict correspondence between derivations in the two systems, i.e., each rule application in G3K corresponds to a bipole-a pair of a positive and a negative phases-in LKF. Since geometric axioms (when properly polarized) induce bipoles, this strong correspondence holds for all modal logics whose Kripke frames are characterized by geometric properties. We extend these results to present a focused labeled proof system for this same class of modal logics and show its soundness and completeness. the resulting proof system allows one to define a rich set of normal forms of modal logic proofs.

关键词： Calculations

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Fine Grained SMT Proofs for the theory of Fixed-Width Bit-Vectors 20th

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20th international conference on logic for programming, Artificial Intelligence and Reasoning (LPAR)

作者： Hadarean, Liana Barrett, Clark Reynolds, Andrew Tinelli, Cesare Deters, Morgan Univ Oxford Oxford England NYU New York NY USA Ecole Polytech Fed Lausanne CH-1015 Lausanne Switzerland Univ Iowa Iowa City IA USA

ISBN: (纸本)9783662488997;9783662488980

Many high-level verification tools rely on SMT solvers to efficiently discharge complex verification conditions. Some applications require more than just a yes/no answer from the solver. For satisfiable quantifier-free problems, a satisfying assignment is a natural artifact. In the unsatisfiable case, an externally checkable proof can serve as a certificate of correctness and can be mined to gain additional insight into the problem. We present a method of encoding and checking SMT-generated proofs for the quantifier-free theory of fixed-width bit-vectors. Proof generation and checking for this theory poses several challenges, especially for proofs based on reductions to propositional logic. Such reductions can result in large resolution subproofs in addition to requiring a proof that the reduction itself is correct. We describe a fine-grained proof system formalized in the LFSC framework that addresses some of these challenges with the use of computational side-conditions. We report results using a proof-producing version of the CVC4 SMT solver on unsatisfiable quantifier-free bit-vector benchmarks from the SMT-LIB benchmark library.

关键词： Formal logic

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