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On the Impact of Address Space Assignment on Performance in systems-on-Chip

On the Impact of Address Space Assignment on Performance in ...

引用

international conference on VLSI Design

作者： G. Hazari M. P. Desai H. Kasture Department of Electrical Engineering Indian Institute of Technology Bombay India

ISBN: (纸本)9780769527628;0769527620

Today, VLSI systems for computationally demanding applications are being built as systems-on-chip (SoCs) with a distributed memory subsystem which is shared by a large number of processing elements. the memory sub-system is a potential performance bottleneck in the system. In this paper, the authors consider such a distributed memory subsystem and study the impact of address space distribution on system performance. For a given application on such a system, we introduce the notion of address assignment quality. We show that this assignment quality metric is strongly correlated with memory subsystem throughput over large regions of the design space. We show this using open loop performance modeling of the memory subsystem, and justify this using a queueing and a Markov chain analysis. Further, we develop a detailed memory subsystem model for a multi-processor simulation system built on the Augmint framework. Using two (highly parallel) applications (matrix multiplication and bubble sort) the authors show that application throughput and assignment quality are strongly correlated over large regions of the design space. We infer that maximization of the assignment quality metric can be a fundamental goal in designing memory subsystems and in developing applications in such systems-on-chip

关键词： throughput Very large scale integration Predictive models Space technology System performance Queueing analysis Extraterrestrial measurements Computer applications distributed computing Performance analysis

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parallelization of DC Analysis through Multiport Decomposition

Parallelization of DC Analysis through Multiport Decompositi...

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international conference on VLSI Design

作者： Gaurav Trivedi Madhav P. Desai H. Narayanan Department of Electrical Engineering Indian Institute of Technology Bombay Mumbai India

ISBN: (纸本)9780769527628;0769527620

Physical problems offer scope for macro level parallelization of solution by their essential structure. For parallelization of electrical network simulation, the most natural structure based method is that of multiport decomposition. In this paper this method is used for the simulation of electrical networks consisting of resistances, voltage and current sources using a distributed cluster of weakly coupled processors. At the two levels in which equations are solved in this method the authors have used sparse LU for both levels in the first scheme and sparse LU in the inner level and conjugate gradient in the outer level in the second scheme. Results are presented for planar networks, for the cases where the numbers of slave processors are 1 and 2, and for circuit sizes up to 8.2 million nodes and 16.4 million edges using 8 slave processors. the authors use a cluster of Pentium IV processors linked through a 10/100MBPS Ethernet switch

关键词： Circuits Voltage Diodes Costs Resistors Equations Switches Large-scale systems Concurrent computing Computer networks

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Locality-Aware distributed Loop Scheduling for Chip Multiprocessors

Locality-Aware Distributed Loop Scheduling for Chip Multipro...

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international conference on VLSI Design

作者： L. Xue M. Kandemir G. Chen F. Li O. Ozturk R. Ramanarayanan B. Vaidyanathan Computer Science and Engineering Department Pennsylvania State University USA Computer Science and Engineering Department Pennsylvania State University

ISBN: (纸本)9780769527628;0769527620

Chip multiprocessors are becoming increasingly popular in embedded domain since they have important advantages over their single core counterparts from the parallelism, power efficiency, validation, and verification perspectives. However, extracting maximum performance from these multiprocessors requires compiler support in form of effective code parallelization. the goal of this paper is to present and experimentally evaluate a locality aware dynamic loop scheduling strategy that implements both locality aware loop iteration distribution across parallel processors and dynamic load balancing at runtime. this hybrid scheme has been implemented and tested along with four other previously-proposed loop scheduling schemes, including a locality aware one. Our experimental analysis reveals that the proposed approach generates better results than all other scheduling schemes (static or dynamic) tested. Our results also show that the improvements brought by the proposed scheduling scheme are consistent across experiments with different values of our major simulation parameters such as the number of processors and cache size per processor

关键词： Processor scheduling Dynamic scheduling Runtime Testing Computer science Power engineering and energy parallel processing Load management System-on-a-chip Multiprocessing systems

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Application Specific Datapath Extension with distributed I/O Functional Units

Application Specific Datapath Extension with Distributed I/O...

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international conference on VLSI Design

作者： Nagaraju Pothineni Anshul Kumar Kolin Paul Department of Computer Science Indian Institute of Technology New Delhi India

ISBN: (纸本)9780769527628;0769527620

Performance of an application can be improved through augmenting the processor with application specific functional units (AFUs). Usually a cluster of operations identified from the application forms the behavior of an AFU. Several researchers studied the impact of input and output (I/O) constraints for a legal operation cluster on the overall achievable speedup. the general observation is that the speedup potential grows with the relaxation of I/O constraints. Going further, in this paper, the authors investigate the speedup potential of AFUs in the absence of I/O constraints. Design challenge in the absence of I/O constraints is addressed in a very practical manner, through the identification of maximal convex subgraphs. Usually the available register ports are few but the number of inputs/outputs of the identified patterns are likely to be large. the authors solve the register port limitation by the design of distributed I/O functional units, in which the operands are communicated in multiple cycles. the experimental results show that selection of maximal clusters achieves average 50% higher speedup than selecting I/O constrained operation clusters. Also, our identification algorithm runs 2 to 3 orders faster than an exhaustive identification approach

关键词： Application software Reduced instruction set computing Law Legal factors Registers Application specific processors Hardware Automation Software tools Computer science

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VLSI Architecture for Matrix Inversion using Modified Gram-Schmidt based QR Decomposition

VLSI Architecture for Matrix Inversion using Modified Gram-S...

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international conference on VLSI Design

作者： Chitranjan K. Singh Sushma Honnavara Prasad Poras T. Balsara Center for Integrated Circuits and Systems Erik Jonsson School of Engineering and Computer Science University of Texas Dallas Richardson TX USA

ISBN: (纸本)9780769527628;0769527620

Matrix inversion and triangularization problems are common to a wide variety of communication systems, signal processing applications and solution of a set of linear equations. Matrix inversion is a computationally intensive process and its hardware implementation based on fixed-point (FP) arithmetic is a challenging problem. this paper proposes a fully parallel VLSI architecture under fixed-precision for the inverse computation of a real square matrix using QR decomposition with modified Gram-Schmidt (MGS) orthogonalization. the MGS algorithm is stable and accurate to the integral multiples of machine precision under fixed-precision for a well-conditioned non-singular matrix. For typical matrices (4 times 4) found in MIMO communication systems, the proposed architecture was able to achieve a clock rate of 277 MHz with a latency of 18 time units and area of 72K gates using 0.18-mum CMOS technology. For a generic square matrix of order n, the latency required is 5n - 2 which is better than all previously known architectures. With the use of LUTs and log-domain computations, the total area has been reduced compared to architectures based on linear-domain computations

关键词： Very large scale integration Matrix decomposition Computer architecture Delay CMOS technology Signal processing Equations Hardware Fixed-point arithmetic Concurrent computing

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A Scalable Frame-Level Pipelined Architecture for FSBM Motion Estimation

A Scalable Frame-Level Pipelined Architecture for FSBM Motio...

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international conference on VLSI Design

作者： Wei-feng He Meng-lian Zhao Chi-ying Tsui Zhi-gang Mao School of Microelectronics Shanghai Jiaotong University Shanghai China Institute of VLSI Design University of Zhejiang Hangzhou China Department of Electronic and Computer Engineering HKUST Hong Kong China Microelectronics Center Harbin Institute of Technology Harbin China

ISBN: (纸本)9780769527628;0769527620

Block-based motion estimation is widely used in video compression for removing video temporal redundancy. Frame-level pipelined full-search block-matching motion estimation architecture supports frame-level pipelined operation by exploiting the explicit parallelism among blocks. In this paper, a scalable improved frame-level pipelined architecture for FSBM motion estimation is proposed. the design efforts are focused on extending the array's MAD computation capability while still keeping nearly 100% processor utilization and low hardware overhead. Based on this architecture, a special frame-level pipelined architecture for the case of search range [-N,N -1] is presented, in which internal buffers FIFO1 and FIFO2 are removed and the array's computation capability is 4 times compared with previous W.F. He and Z.G. Mao's architecture. As a result, this architecture offers a feasible solution for HDTV and SHDTV video pictures

关键词： Motion estimation Computer architecture HDTV Systolic arrays Microelectronics Very large scale integration Video compression parallel processing Concurrent computing Hardware

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Improved First-Order Parameterized Statistical Timing Analysis for Handling Slew and Capacitance Variation

Improved First-Order Parameterized Statistical Timing Analys...

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international conference on VLSI Design

作者： Ratnakar Goyal Sachin Shrivastava Harindranath Parameswaran Parveen Khurana Cadence Design Systems India Private Limite Noida India

ISBN: (纸本)9780769527628;0769527620

With shrinking process node sizes, the inherent effect of process variations is playing an increasingly larger factor in defining the behavior of a circuit. Conventional static timing analysis (STA) using best case/worst case analysis (BC-WC) is overly pessimistic in many cases, and could also be optimistic in some cases. this has resulted in the promotion of statistical static timing analysis (SSTA) as a method for estimating yield of a circuit in terms of timing activities. SSTA provides a robust and tractable framework where the variations of the process parameter space can be captured in one analysis and the results of the analysis can be used to predict the yield of the design (with respect to timing), along with other reports of interest such as the probability of a net being critical. A popular technique for SSTA is the first-order parameterized approach where sensitivities of the timing activities to process parameter variations are propagated through the circuit, and the probability distributions of timing activities are computed at points of interest based on these sensitivities. In this paper, we describe a methodology for taking into account the effect of input slew and output load sensitivities on path arrival sensitivities. In this paper we also describe how slew sensitivities can be propagated and provide analytical expressions for the same. We also provide experimental results to show the increase in accuracy obtained as compared with Monte-Carlo analysis

关键词： Timing Capacitance Circuits Delay Performance analysis Yield estimation Robustness Probability distribution distributed computing Manufacturing processes

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Enhancing Locality in Two-Dimensional Space through Integrated Computation and Data Mappings

Enhancing Locality in Two-Dimensional Space through Integrat...

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international conference on VLSI Design

作者： Mahmut Kandemir Ozcan Ozturk Vijay S. R. Degalahal Computer Science and Engineering Department Pennsylvania State University USA Intel

ISBN: (纸本)9780769527628;0769527620

As the number of processors used in chip multiprocessors keeps increasing, NoC (network-on-chip) based multiprocessor architectures are becoming increasingly important. While the last couple of years have witnessed numerous proposals regarding how to architect NoC based parallel computing platforms, code and data mapping issues in these architectures have largely been ignored. In particular, there are very few papers so far focusing on providing compiler support for NoC based chip multiprocessor systems. Our goal in this paper is to demonstrate how an optimizing compiler can map data and computation to NoC nodes in a locality-aware manner such that the energy spent in data communications is minimized. the proposed approach formulates this locality problem within a linear algebraic framework and discusses two alternate solution strategies that determine appropriate computation/data mappings in NoC. Our experimental evaluation compares this proposed scheme against two alternate optimization strategies, one that optimizes data mapping alone and the other one that optimizes computation mapping alone. the collected results indicate that our approach improves energy consumption by about 25% with respect to a scheme that does not consider locality of communication during NoC mapping. More importantly, our results reveal that neither optimized data mapping alone nor optimized computation mapping alone is sufficient for achieving the best locality and the compiler needs to consider both in a coordinated fashion. In fact, our results show that the proposed approach improves energy consumption over the pure data mapping and pure computation mapping oriented schemes by around 22% and 20%, respectively, when considering all eight application codes we tested

关键词： Network-on-a-chip Optimizing compilers Computer architecture Energy consumption Testing Computer networks Proposals parallel processing Data communication Computer science

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A routing load balancing policy for grid computing environments

A routing load balancing policy for grid computing environme...

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20th international conference on Advanced Information Networking and Applications

作者： de Mello, Rodrigo Fernandes Senger, Luciano Jose Yang, Laurence Tianruo Univ Sao Paulo Inst Math Sci & Comp Sao Carlos SP Brazil Univ Estadual Ponta Grossa Dept Informat Technol Ponta Grossa PR Brazil St Francis Xavier Univ Dept Comp Sci Antigonish B2G 2W5 NS Canada

ISBN: (纸本)0769524664

the evolution of computers and networks has motivated the development of high performance systems using the distributed system concepts. Such evolution has motivated the study of load balancing techniques, low latency protocols, operating systems and middlewares. Furthermore, the evolution from distributed systems based on clusters to grid environments has motivated new researches to define load balancing algorithms to support scalable and heterogeneous computing capacity environments. In this paper, the Route load balancing algorithm is proposed, presented and evaluated. this algorithm is designed to equally distribute the workload of tasks of parallel applications over Grid computing environments. Experiments compare the performance of the proposed algorithm to others from literature. the obtained results allow to conclude that the Route algorithm is indicated for environments where there are several heterogeneous computers and parallel applications are composed of multiple tasks.

关键词： distributed computer systems

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A parallel classification method for genomic and proteomic problems

A parallel classification method for genomic and proteomic p...

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20th international conference on Advanced Information Networking and Applications

作者： Guarracino, M. R. Cifarelli, C. Seref, O. Pardalos, P. M. High Performance Computing and Networking Institute National Research Council Italy Department of Statistic Probability and Applied Statistics University of Rome La Sapienza Italy Center for Applied Optimization University of Florida Gainesville FL 32611-6595 United States

ISBN: (纸本)0769524664

Classification is one of the most widely used method in data mining with numerous applications in biomedicine. the scope and the resolution of data involved in many real life applications require very efficient implementations of classification methods, developed to run on parallel or distributed computational systems. In this study, a parallel implementation of an efficient algorithm that is based on regularized general eigenvalue classification is introduced. the proposed implementation is tested on a very large scale genomic data base and preliminary results regarding efficiency are presented.

关键词： Proteins

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