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检索条件"任意字段=20th International Symposium on Computer Architecture and High Performance Computing"

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Multi-Role SpTRSV on Sunway Many-core architecture 20

Multi-Role SpTRSV on Sunway Many-core Architecture<bold> </b...

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20th IEEE international Conference on high performance computing and Communications (HPCC) / 16th IEEE international Conference on Smart City (SmartCity) / 4th IEEE international Conference on Data Science and Systems (DSS)

作者： Li, Mingzhen Liu, Yi Yang, Hailong Luan, Zhongzhi Qian, Depei Beihang Univ Sch Comp Sci & Engn Beijing Peoples R China

ISBN: (纸本)9781538666142

Sparse triangular solver (SpTRSV) is an important and indispensable building block for many scientific applications. the parallelism of SpTRSV is exploited using Level-Set method in literature, however this method still suffers from high synchronization cost and irregular global memory access especially on many-core architecture such as Sunway. In this paper, we propose an efficient implementation of SpTRSV using the massive computing resources on Sunway architecture. Specifically, we divide the 64 CPEs in a core group into three different roles, worker, router and storer. We also build a logical shared memory by carefully manipulating the scratchpad memory located in each storer and allow synchronization using the unique register communication on Sunway architecture. We partition the sparse matrix into multiple bands and replace the irregular global memory accesses with shared memory accesses, which significantly improves the data locality during the calculation of a band. Our experiments with 12 representative datasets demonstrate that our approach achieves up to 5.14x (2.65x on average) speedup.

关键词： Registers Sparse matrices computer architecture Synchronization Program processors Parallel processing Conferences

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Exploring heterogeneous mobile architectures with a high-level programming model 29

Exploring heterogeneous mobile architectures with a high-lev...

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29th international symposium on computer architecture and high performance computing SBAC-PAD

作者： de Carvalho, Wilson Andrade, Guilherme Caldeira, Pedro Utsch, Renato Ferreira, Renato Rocha, Leonardo Carvalho, Renan Nasser, Millas Univ Fed Minas Gerais Belo Horizonte MG Brazil Univ Fed Sao Joao del Rei Sao Joao Del Rei MG Brazil

ISBN: (纸本)9781509012336

the development of new technologies is setting a new era characterized, among other factors, by the rise of sophisticated mobile devices containing CPUs and GPUs. this emerging scenario of heterogeneous mobile architectures brings challenging issues regarding the use of the available computing resources. Such issues are mainly related to the intrinsic complexity of coordinating these processors in order to increase application performance. In this sense, this paper presents a high-level programming model to implement parallel patterns that can be executed in a coordinate way by heterogeneous mobile architectures. A comparative analysis of performance and programming complexity is presented, contrasting code generated automatically from the proposed programming model with low-level manually-optimized implementations.

关键词： Program processors

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Assessing Time Predictability Features of ARM *** Multicores 30

Assessing Time Predictability Features of ARM *** Multicores

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30th international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Fernandez, Gabriel Cazorla, Francisco J. Abella, Jaume Girbal, Sylvain BSC Barcelona Spain CSIC IAAA Madrid Spain UPC Barcelona Spain THALES Res & Technol TRT Palaiseau France

ISBN: (纸本)9781538677698

the increasing performance needs in critical real-time embedded systems (CRTES), such as for instance the automotive domain, push for the adoption of high-performance hardware from the consumer electronics domain. However, their time-predictability features are quite unexplored. the ARM *** architecture is a good candidate for adoption in the CRTES market (i.e. in the automotive market it has already started being used). In this paper we study ARM ***'s capabilities to meet CRTES requirements. In particular, we perform a qualitative and quantitative assessment of its timing characteristics, focusing on shared multicore resources, and how this architecture can be reliably used in CRTES.

关键词： Program processors computer architecture Timing Real-time systems Monitoring Task analysis Benchmark testing

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GPUdmm: A high-performance and memory-oblivious GPU architecture using dynamic memory management

GPUdmm: A high-performance and memory-oblivious GPU architec...

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20th IEEE international symposium on high performance computer architecture, HPCA 2014

作者： Kim, Youngsok Lee, Jaewon Jo, Jae-Eon Kim, Jangwoo Department of Computer Science and Engineering POSTECH Korea Republic of

ISBN: (纸本)9781479930975

GPU programmers suffer from programmer-managed GPU memory because both performance and programmability heavily depend on GPU memory allocation and CPU-GPU data transfer mechanisms. To improve performance and programmability, programmers should be able to place only the data frequently accessed by GPU on GPU memory while overlapping CPU-GPU data transfers and GPU executions as much as possible. However, current GPU architectures and programming models blindly place entire data on GPU memory, requiring a significantly large GPU memory size. Otherwise, they must trigger unnecessary CPU-GPU data transfers due to an insufficient GPU memory size. In this paper, we propose GPUdmm, a novel GPU architecture to enable high-performance and memory-oblivious GPU programming. First, GPUdmm uses GPU memory as a cache of CPU memory to provide programmers a view of the CPU memory-sized programming space. Second, GPUdmm achieves high performance by exploiting data locality and dynamically transferring data between CPU and GPU memories while effectively overlapping CPU-GPU data transfers and GPU executions. third, GPUdmm can further reduce unnecessary CPU-GPU data transfers by exploiting simple programmer hints. Our carefully designed and validated experiments (e.g., PCIe/DMA timing) against representative benchmarks show that GPUdmm can achieve up to five times higher performance for the same GPU memory size, or reduce the GPU memory size requirement by up to 75% while maintaining the same performance. © 2014 IEEE.

关键词： Graphics processing unit

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Enterprise IT trends and implications for architecture research

Enterprise IT trends and implications for architecture resea...

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11th international symposium on high-performance computer architecture

作者： Ranganathan, P Jouppi, N Hewlett Packard Labs ISSL MMSL Palo Alto CA USA

ISBN: (纸本)0769522750

the last decade has seen several changes in the structure and emphasis of enterprise IT systems. Specific infrastructure trends have included the emergence of large consolidated data centers, the adoption of virtualization and modularization, and an increased commoditization of hardware. At the application level, both the workload mix and usage patterns have evolved to an increased emphasis on service-centric computing and SLA-driven performance tuning. these, often dramatic, changes in the enterprise IT landscape motivate equivalent changes in the emphasis of architecture research. In this paper, we summarize some recent trends in enterprise IT systems and discuss the implications for architecture research, suggesting some high-level challenges and open questions for the community to address.

关键词： computer architecture

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STM: Cloning the spatial and temporal memory access behavior

STM: Cloning the spatial and temporal memory access behavior

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20th IEEE international symposium on high performance computer architecture, HPCA 2014

作者： Awad, Amro Solihin, Yan Dept. of Electrical and Computer Engineering North Carolina State University United States

ISBN: (纸本)9781479930975

computer architects need a deep understanding of clients' workload in order to design and tune the architecture. Unfortunately, many important clients will not share their software to computer architects due to the proprietary or confidential nature of their software. One technique to mitigate this problem is producing synthetic traces (clone) that replicate the behavior of the original workloads. Unfortunately, today there is no universal cloning technique that can capture arbitrary memory access behavior of applications. Existing technique captures only temporal, but not spatial, locality. In order to study memory hierarchy organization beyond caches, such as including prefetchers and translation lookaside buffer (TLB), capturing only temporal locality is insufficient. In this paper, we propose a new memory access behavior cloning technique that captures both temporal and spatial locality. We abbreviate our scheme as Spatio-Temporal Memory (STM) cloning. We propose a new profiling method and statistics that capture stride patterns and transition probabilities. We show how the new statistics enable accurate clone generation that allow clones to be used in place of the original benchmarks for studying the L1/L2/TLB miss rates as we vary the L1 cache, L1 prefetcher, L2 cache, TLB, and page size configurations. © 2014 IEEE.

关键词： Cloning

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Accordion: Toward soft Near-threshold Voltage computing

Accordion: Toward soft Near-Threshold Voltage Computing

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20th IEEE international symposium on high performance computer architecture, HPCA 2014

作者： Karpuzcu, Ulya R. Akturk, Ismail Kim, Nam Sung University of Minnesota Twin Cities United States University of Wisconsin Madison United States

ISBN: (纸本)9781479930975

While more cores can find place in the unit chip area every technology generation, excessive growth in power density prevents simultaneous utilization of all. Due to the lower operating voltage, Near-threshold Voltage computing (NTC) promises to fit more cores in a given power envelope. Yet NTC prospects for energy efficiency disappear without mitigating (i) the performance degradation due to the lower operating frequency;(ii) the intensified vulnerability to parametric variation. To compensate for the first barrier, we need to raise the degree of parallelism - the number of cores engaged in computation. NTC-prompted power savings dominate the power cost of increasing the core count. Hence, limited parallelism in the application domain constitutes the critical barrier to engaging more cores in computation. To avoid the second barrier, the system should tolerate variation-induced errors. Unfortunately, engaging more cores in computation exacerbates vulnerability to variation further. To overcome NTC barriers, we introduce Accordion, a novel, light-weight framework, which exploits weak scaling along with inherent fault tolerance of emerging R(ecognition), M(ining), S(ynthesis) applications. the key observation is that the problem size not only dictates the number of cores engaged in computation, but also the application output quality. Consequently, Accordion designates the problem size as the main knob to trade off the degree of parallelism (i.e. the number of cores engaged in computation), with the degree of vulnerability to variation (i.e. the corruption in application output quality due to variation-induced errors). Parametric variation renders ample reliability differences between the cores. Since RMS applications can tolerate faults emanating from data-intensive program phases as opposed to control, variation-afflicted Accordion hardware executes fault-tolerant data-intensive phases on error-prone cores, and reserves reliable cores for control. © 2014 IEEE.

关键词： threshold voltage

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Petascale computing research challenges - A manycore perspective

Petascale computing research challenges - A manycore perspec...

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13th international symposium on high-performance computer architecture

作者： Pawlowski, Steve Intel Corp Digital Enterprise Grp Santa Clara CA 95051 USA

ISBN: (纸本)9781424408047

Future high performance computing will undoubtedly reach Petascale and beyond. Today's HPC is tomorrow's Personal computing. What are the evolving processor architectures towards Multi-core and Many-core for the best performance per watt;memory bandwidth solutions to feed the ever more powerful processors;intra-chip interconnect options for optimal bandwidth vs. power? With Moore's Law continuing to prove its viability and shrinking transistors' geometry, improving reliability is even more challenging. Intel Senior Fellow and Chief Technology Officer of Intel's Digital Enterprise Group, Steve Pawlowski, will provide his technology vision, insight and research challenges to achieve the vision of Petascale computing and beyond. © 2007 IEEE.

关键词： Computation theory

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HyFlow: A high performance Distributed Software Transactional Memory Framework 11

HyFlow: A High Performance Distributed Software Transactiona...

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20th international symposium on high performance Distributed computing

作者： Saad, Mohamed M. Ravindran, Binoy Virginia Tech ECE Dept Blacksburg VA 24061 USA

ISBN: (纸本)9781450305525

We present HyFlow - a distributed software transactional memory (D-STM) framework for distributed concurrency control. HyFlow is a Java framework for D-STM, with pluggable support for directory lookup protocols, transactional synchronization and recovery mechanisms, contention management policies, cache coherence protocols, and network communication protocols. HyFlow exports a simple distributed programming model that excludes locks: using (Java 5) annotations, atomic sections are defined as transactions, in which reads and writes to shared, local and remote objects appear to take effect instantaneously. No changes are needed to the underlying virtual machine or compiler. We describe HyFlow's architecture and implementation, and report on experimental studies comparing HyFlow against competing models including Java remote method invocation (RMI) with mutual exclusion and read/write locks, distributed shared memory (DSM), and directory-based D-STM. Our studies show that HyFlow outperforms competitors by as much as 40-190% on a broad range of transactional workloads on a 72-node system, with more than 500 concurrent transactions.

关键词： Software Transactional Memory Distributed systems Dataflow Control Flow Framework Java

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Wrangler: Virtual Cluster Provisioning for the Cloud 11

Wrangler: Virtual Cluster Provisioning for the Cloud

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20th international symposium on high performance Distributed computing

作者： Juve, Gideon Deelman, Ewa USC Informat Sci Inst Marina Del Rey CA 90292 USA

ISBN: (纸本)9781450305525

Cloud computing systems are becoming an important platform for science applications. Infrastructure as a Service (IaaS) clouds provide the capability to provision virtual machines (VMs) on demand with a specific configuration of hardware resources, but they do not provide functionality for managing those resources once provisioned. In order for such clouds to be used effectively for parallel and distributed scientific applications, tools need to be developed that can help users to deploy their applications in the cloud. this paper describes a system we have developed to provision, configure, and manage clusters of virtual machines.

关键词： Cloud computing virtual clusters

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