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检索条件"任意字段=20th International Symposium on Computer Architecture and High Performance Computing"

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echofs: A Scheduler-guided Temporary Filesystem to leverage Node-local NVMs 30

echofs: A Scheduler-guided Temporary Filesystem to leverage ...

引用

30th international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Miranda, Alberto Nou, Ramon Cortes, Toni BSC Barcelona Spain Univ Politecn Cataluna BSC Barcelona Spain

ISBN: (纸本)9781538677698

the growth in data-intensive scientific applications poses strong demands on the HPC storage subsystem, as data needs to be copied from compute nodes to I/O nodes and vice versa for jobs to run. the emerging trend of adding denser, NVM-based burst buffers to compute nodes, however, offers the possibility of using these resources to build temporary filesystems with specific I/O optimizations for a batch job. In this work, we present echofs, a temporary filesystem that coordinates with the job scheduler to preload a job's input files into node-local burst buffers. We present the results measured with NVM emulation, and different FS backends with DAX/FUSE on a local node, to show the benefits of our proposal and such coordination.

关键词： Buffer storage Metadata Fuses Nonvolatile memory Hardware computer architecture Random access memory

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Cloud workload prediction and generation models 29

Cloud workload prediction and generation models

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29th international symposium on computer architecture and high performance computing SBAC-PAD

作者： Madi-Wamba, Gilles Li, Yunbo Orgerie, Anne-Cecile Beldiceanu, Nicolas Menaud, Jean-Marc IMT Atlantique LS2N Nantes France CNRS IRISA Rennes France

ISBN: (纸本)9781509012336

Cloud computing allows for elasticity as users can dynamically benefit from new virtual resources when their workload increases. Such a feature requires highly reactive resource provisioning mechanisms. In this paper, we propose two new workload prediction models, based on constraint programming and neural networks, that can be used for dynamic resource provisioning in Cloud environments. We also present two workload trace generators that can help to extend an experimental dataset in order to test more widely resource optimization heuristics. Our models are validated using real traces from a small Cloud provider. Both approaches are shown to be complimentary as neural networks give better prediction results, while constraint programming is more suitable for trace generation.

关键词： Time series analysis Predictive models Programming Cloud computing Neural networks Virtual machining

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Predicting the Energy consumption of CUDA kernels using SimGrid 32

Predicting the Energy consumption of CUDA kernels using SimG...

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32nd IEEE international symposium on computer architecture and high-performance computing (SBAC-PAD) / 11th Workshop on Applications for Multi-Core architectures (WAMCA)

作者： Boughzala, Dorra Lefevre, Laurent Orgerie, Anne-Cecile Univ Lyon EnsL UCBL INRIACNRSLIP Lyon France Univ Rennes INRIA CNRS IRISA Rennes France

ISBN: (纸本)9781728199245

Building a sustainable Exascale machine is a very promising target in high performance computing (HPC). To tackle the energy consumption challenge while continuing to provide tremendous performance, the HPC community have rapidly adopted GPU-based systems. Today, GPUs have became the most prevailing components in the massively parallel HPC landscape thanks to their high computational power and energy efficiency. Modeling the energy consumption of applications running on GPUs has gained a lot of attention for the last years. Alas, the HPC community lacks simple yet accurate simulators to predict the energy consumption of general purpose GPU applications. In this work, we address the prediction of the energy consumption of CUDA kernels via simulation. We propose in this paper a simple and lightweight energy model that we implemented using the open-source framework SimGrid. Our proposed model is validated across a diverse set of CUDA kernels and on two different NVIDIA GPUs (Tesla M2075 and Kepler K20Xm). As our modeling approach is not based on performance counters or detailed-architecture parameters, we believe that our model can be easily approved by users who take care of the energy consumption of their GPGPU applications.

关键词： GPGPU computing CUDA kernels Energy modeling Simulation

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HyperSpace: Distributed Bayesian Hyperparameter Optimization 30

HyperSpace: Distributed Bayesian Hyperparameter Optimization

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30th international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Young, M. Todd Hinkle, Jacob Ramanathan, Arvind Kannan, Ramakrishnan Oak Ridge Natl Lab Computat Sci & Engn Div Oak Ridge TN 37830 USA Oak Ridge Natl Lab Comp Sci & Math Div Oak Ridge TN USA

ISBN: (纸本)9781538677698

As machine learning models continue to increase in complexity, so does the potential number of free model parameters commonly known as hyperparameters. While there has been considerable progress toward finding optimal configurations of these hyperparameters, many optimization procedures are treated as black boxes. We believe optimization methods should not only return a set of optimized hyperparameters, but also give insight into the effects of model hyperparameter settings. To this end, we present HyperSpace, a parallel implementation of Bayesian sequential model-based optimization. HyperSpace leverages high performance computing (HPC) resources to better understand unknown, potentially non-convex hyperparameter search spaces. We show that it is possible to learn the dependencies between model hyperparameters through the optimization process. By partitioning large search spaces and running many optimization procedures in parallel, we also show that it is possible to discover families of good hyperparameter settings over a variety of models including unsupervised clustering, regression, and classification tasks.

关键词： Bayesian optimization SMBO parallel computing HPC

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Pliant: Leveraging Approximation to Improve Datacenter Resource Efficiency 25

Pliant: Leveraging Approximation to Improve Datacenter Resou...

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25th IEEE international symposium on high performance computer architecture (HPCA)

作者： Kulkarni, Neeraj Qi, Feng Delimitrou, Christina Cornell Univ Ithaca NY 14853 USA

ISBN: (纸本)9781728114446

Cloud multi-tenancy is typically constrained to a single interactive service colocated with one or more batch, low-priority services, whose performance can be sacrificed when deemed necessary. Approximate computing applications offer the opportunity to enable tighter colocation among multiple applications whose performance is important. We present Pliant, a lightweight cloud runtime that leverages the ability of approximate computing applications to tolerate some loss in their output quality to boost the utilization of shared servers. During periods of high resource contention, Pliant employs incremental and interference-aware approximation to reduce contention in shared resources, and prevent QoS violations for co-scheduled interactive, latency-critical services. We evaluate Pliant across different interactive and approximate computing applications, and show that it preserves QoS for all co-scheduled workloads, while incurring a 2.1% loss in output quality, on average.

关键词： Quality of service Approximate computing Runtime Cloud computing Interference Optimization Synchronization

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Optimization of Partitioned architectures to Support Soft Real-Time Applications 20

Optimization of Partitioned Architectures to Support Soft Re...

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20th IEEE Pacific Rim international symposium on Dependable computing (PRDC)

作者： Tamas-Selicean, Domitian Pop, Paul Tech Univ Denmark DTU Compute DK-2800 Lyngby Denmark

ISBN: (纸本)9781479964741

In this paper we propose a new Tabu Search-based design optimization strategy for mixed-criticality systems implementing hard and soft real-time applications on the same platform. Our proposed strategy determined an implementation such that all hard real-time applications are schedulable and the quality of service of the soft real-time tasks is maximized. We have evaluated our strategy using an aerospace case study.

关键词： optimisation quality of service real-time systems search problems mixed criticality systems partitioned architecture optimisation real-time applications support soft real-time applications tabu search based design optimization Aerospace electronics computer architecture NASA Optimization Quality of service Real-time systems Software mixed-criticality optimization partitioned architecture real-time Quality of service real-time systems real-time application program avionics tabu search computer architecture soft real-time National Aeronautics and Space Administration computer software

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Stash directory: A scalable directory for many-core coherence

Stash directory: A scalable directory for many-core coherenc...

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20th IEEE international symposium on high performance computer architecture, HPCA 2014

作者： Demetriades, Socrates Cho, Sangyeun Computer Science Department University of Pittsburgh United States Memory Division Samsung Electronics Co. Korea Republic of

ISBN: (纸本)9781479930975

Maintaining coherence in large-scale chip multiprocessors (CMPs) embodies tremendous design trade-offs in meeting the area, energy and performance requirements. Sparse directory organizations represent the most energy-efficient and scalable approach towards many-core coherence. However, their limited associativity disallows the one-to-one correspondence of directory entries to cached blocks, rendering them inadequate in tracking all cached blocks. Unless the directory storage is generously over-provisioned, conflicts will force frequent invalidations of cached blocks, severely jeopardizing the system performance. As the chip area and power become increasingly precious with the growing core count, over-provisioning the directory storage becomes unsustainably costly. Stash Directory is a novel sparse directory design that allows directory entries tracking private blocks to be safely evicted without invalidating the corresponding cached blocks. By doing so, it improves system performance and increases the effective directory capacity, enabling significantly smaller directory designs. To ensure correct coherence under the new relaxed inclusion property, stash directory delegates to the last level cache the responsibility to discover hidden cached blocks when necessary, without however raising significant overhead concerns. Simulations on a 16-core CMP model show that Stash Directory can reduce space requirements to 1/8 of a conventional sparse directory, without compromising performance. © 2014 IEEE.

关键词： Energy efficiency

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QORE: A fault tolerant network-on-chip architecture with power-efficient quad-function channel (QFC) buffers

QORE: A fault tolerant network-on-chip architecture with pow...

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20th IEEE international symposium on high performance computer architecture, HPCA 2014

作者： Ditomaso, Dominic Kodi, Avinash Louri, Ahmed Electrical Engineering and Computer Science Ohio University Athens OH 45701 United States Electrical and Computer Engineering University of Arizona Tucson AZ 85721 United States

ISBN: (纸本)9781479930975

Network-on-Chips (NoCs) are quickly becoming the standard communication paradigm for the growing number of cores on the chip. While NoCs can deliver sufficient bandwidth and enhance scalability, NoCs suffer from high power consumption due to the router microarchitecture and communication channels that facilitate inter-core communication. As technology keeps scaling down in the nanometer regime, unpredictable device behavior due to aging, infant mortality, design defects, soft errors, aggressive design, and process-voltage-temperature variations, will increase and will result in a significant increase in faults (both permanent and transient) and hardware failures. In this paper, we propose QORE - a fault tolerant NoC architecture with Quad-Function Channel (QFC) buffers. the use of QFC buffers and their associated control (link and fault controllers) enhance fault-tolerance by allowing the NoC to dynamically adapt to faults at the link level and reverse propagation direction to avoid faulty links. Additionally, QFC buffers reduce router power and improve performance by eliminating in-router buffering. Our simulation results using real benchmarks and synthetic traffic mixes show that QORE improves speedup by 1.3× and throughput by 2.3× when compared to state-of-the art fault tolerant NoCs designs such as Ariadne and Vicis. Moreover, using Synopsys Design Compiler, we also show that network power in QORE is reduced by 21% with minimal control overhead. © 2014 IEEE.

关键词： Network-on-chip

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Customizable Heterogeneous Acceleration for Tomorrow's high-performance computing 17

Customizable Heterogeneous Acceleration for Tomorrow's High-...

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2015 IEEE 17th international Conference on high performance computing and Communications (HPCC)

作者： Cilardo, Alessandro Flich, Jose Gagliardi, Mirko Gavila, Rafael T. Univ Naples Federico II DIETI Naples Italy Univ Politecn Valencia GAP Valencia Spain

ISBN: (纸本)9781479989379

high-performance computing as we know it today is experiencing unprecedented changes, encompassing all levels from technology to use cases. this paper explores the adoption of customizable, deeply heterogeneous manycore systems for future QoS-sensitive and power-efficient high-performance computing. At the heart of the proposed architecture is a NoC-based manycore system embracing medium-end CPUs, GPU-like processors, and reconfigurable hardware regions. the paper discusses the high-level design principles inspiring this innovative architecture as well as the key role that heterogeneous acceleration, ranging from multicore processors and GPUs down to FPGAs, might play for tomorrow's high-performance computing.

关键词： field programmable gate arrays graphics processing units multiprocessing systems network-on-chip parallel processing power aware computing quality of service FPGA GPU-like processors NoC-based many-core system QoS-sensitive computing customizable heterogeneous acceleration heterogeneous acceleration heterogeneous manycore systems high-level design principles high-performance computing innovative architecture medium-end CPU multicore processors power-efficient high-performance computing reconfigurable hardware regions Acceleration computer architecture Field programmable gate arrays Hardware Program processors Quality of service Registers Field programmable gate arrays high performance computing Quality of service power aware computing Program processors Multiprocessing systems network-on-chip computer architecture Registers acceleration PARALLEL PROCESSING (computerS) Multi-core processors computer hardware Graphics Processing Unit

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Remove the memory wall: From performance modeling to architecture optimization 20

Remove the memory wall: From performance modeling to archite...

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20th IEEE international Parallel and Distributed Processing symposium, IPDPS 2006

作者： Sun, Xian-He Department of Computer Science Illinois Institute of Technology United States

ISBN: (纸本)1424400546

Data access is a known bottleneck of high performance computing (HPC). the prime sources of this bottleneck are the performance gap between the processor and memory storage and the large memory requirements of ever-hungry applications. Although advanced memory hierarchies and parallel file systems have been developed in recent years, they only provide high bandwidth for contiguous, well-formed data streams, performing poorly for accessing small, noncontiguous data. Unfortunately, many HPC applications make a large number of requests for small and noncontiguous pieces of data, as do high-level I/O libraries such as HDF-5. the problematic memory wall remains after years of study and, in fact, is becoming the most important issue of HPC. We propose a new I/O architecture for HPC. Unlike traditional I/O designs where data is stored and retrieved by request, our architecture is based on a novel "Server-Push" model in which a data access server proactively pushes data from a file server to the compute node's memory or to it's cache directly based on the architecture design. Simulation results show that with the new approach the cache hit rates increase well above 90% for various benchmark applications that are notorious for poor cache performance. performance evaluation is the driven force of the push-based model. Mechanisms of performance modeling, evaluation, and optimization are applied to data access pattern identification, prefetching algorithm design, data replacement strategy development, and architecture optimization to enable the "Server-Push" model. Our current success illustrates the power and unique role of performance evaluation in computing.

关键词： Computational methods

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