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检索条件"任意字段=20th International Symposium on Computer Architecture and High Performance Computing"

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swDarknet: A Heterogeneous Parallel Deep Learning Framework Suitable for SW26010 Pro Processor 20th

swDarknet: A Heterogeneous Parallel Deep Learning Framework ...

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20th IFIP WG 10.3 international Conference on Network and Parallel computing, NPC 2024

作者： Liu, Huazeng Tian, Min Wu, Xiaoming Yang, Meihong Ren, Zenghui Li, Yanlong Jinan China Jinan Key Laboratory of High Performance Computing Shandong Provincial Key Laboratory of Computer Networks Shandong Fundamental Research Center for Computer Science Jinan China

ISBN: (纸本)9789819628292

As the size of AI models grows dramatically to achieve higher accuracy, more and more models are trained on supercomputers with massive computing and memory. However, it is still challenging to accelerate deep learning applications on supercomputer systems with many-core architectures. In this paper, we propose swDarknet: a Darknet-based heterogeneous parallel deep learning framework on the SW26010 Pro processor. First, We designed three heterogeneous parallel DNN layers: adaptive block-splitting strategy for matrix-multiplication layer, optimized memory access for convolutional layer, and block-based parallel pooling layer. Second, we proposed a model averaging (MA) method to efficiently scale swDarknet across many processors. Finally, we evaluated the performance of swDarknet on a core group. As compared with darknet, the convolutional layers achieved an average speedup of 32x. When training AlexNet and VGG-16, swDarknet can achieve up to 36.79× and 181.35× speedup, respectively. © IFIP international Federation for Information Processing 2025.

关键词： Supercomputers

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Optimizing Vo-Viso: A Modified Methodology to Parallel computing with Isolating Data in Memristor Arrays 20th

Optimizing Vo-Viso: A Modified Methodology to Parallel Comp...

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20th IFIP WG 10.3 international Conference on Network and Parallel computing, NPC 2024

作者： Wang, Wenqing Chen, Yabo Xu, Nuo Hu, Yihong Huang, Chenglong Wei, Shaojun Fang, Liang National University of Defense Technology Changsha410073 China Tsinghua University Beijing100084 China

ISBN: (纸本)9789819628292

the MAGIC NOR gate-based memristor array is a promising processing-in-memory (PIM) approach due to its massive parallelism, flexible logical operation, and non-volatile memory characteristics. the Vo-Viso MAGIC NOR gate operation mode is proposed to achieve high-throughput parallel computing and isolate other data within a memristor array. However, Viso has a cumulative effect on the node voltage of the active row, calling into question the feasibility of Vo-Viso operation mode. In this paper, circuit analysis defines the necessary circuit parameter conditions for enabling parallel computing and isolation units in the MAGIC NOR gate array. By algorithms in Python and CUDA C++ exploration, we determined that achieving the necessary conditions within the array parameters ranges—including the tolerance margin VΔ, array size, Vo, Viso and memristor parameters suitable for real-world circuit requirements—is unfeasible. In response to these challenges, we modified the memristor array architecture. the modified architecture employs transistors to activate compute units while safeguarding the rest selectively. the feasibility of this architecture is validated by SPICE with selected transistors fabricated using a 65 nm process, taking into account transistor resistance and the fluctuations in Vset and Vreset in the 8×8 modified memristor array. To accommodate the design requirement of the state-of-the-art memristor array, the feasibility of 64×64 modified memristor array, taking into account the impact of wire resistance, is further verified. this paper bridges the gap between reliable high-throughput parallel computing operation and MAGIC NOR PIM architecture. © IFIP international Federation for Information Processing 2025.

关键词： SPICE

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SUCP Analysis for Region-Centric UAV-Assisted MEC Networks 20th

SUCP Analysis for Region-Centric UAV-Assisted MEC Networks

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20th IFIP WG 10.3 international Conference on Network and Parallel computing, NPC 2024

作者： Li, Yan Yi, Zhaozhi Long, Qingmin Luo, Lailong Guo, Deke School of Computer and Communication Engineering Changsha University of Science and Technology Changsha410004 China National Key Laboratory of Information Systems Engineering National University of Defense Technology Changsha410073 China

ISBN: (纸本)9789819628636

With the increase of computing-intensive and delay-sensitive applications, mobile edge computing (MEC) technology has sprung up. It effectively satisfies the needs of user equipment (UE) for real-time computing resources by placing servers at the edge of the network. However, traditional MEC infrastructures are constrained by their fixed locations and emergency mobility needs. Unmanned aerial vehicles (UAVs) offer an effective solution with low cost, high mobility, and flexible deployment capabilities. In this paper, we propose a region-centric UAV-assisted MEC model, where the whole network space is divided into a set of hexagonal cells of equal area, and all UAVs in the same cell jointly process UE offloading data. Assume all UAVs are assumed to be equipped with independent MEC servers, and both UAVs and terrestrial UE follow independent homogeneous Poisson point process (PPP) distributions. Using the stochastic geometry analysis framework, we derive the successful uplink communication probability (SUCP) of uplink transmission for users. Finally, we compare the simulation results with the theoretical values to verify the model’s accuracy and evaluate the influence of key performance parameters on the network performance. © IFIP international Federation for Information Processing 2025.

关键词： Stochastic systems

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Make LLM Inference Affordable to Everyone: Augmenting GPU Memory with NDP-DIMM 31

Make LLM Inference Affordable to Everyone: Augmenting GPU Me...

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31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Liu, Lian Zhao, Shixin Li, Bing Ren, Haimeng Xu, Zhaohui Wang, Mengdi Li, Xiaowei Han, Yinhe Wang, Ying Institute of Computing Technology Chinese Academic of Sciences China University of Chinese Academy of Sciences China Zhongguancun Laboratory China Institute of Microelectronics Chinese Academy of Sciences China ShanghaiTech University School of Information Science and Technology China

ISBN: (纸本)9798331506476

the billion-scale Large Language Models (LLMs) necessitate deployment on expensive server-grade GPUs with large-storage HBMs and abundant computation capability. As LLM-assisted services become popular, achieving cost-effective LLM inference on budget-friendly hardware becomes the current trend. this has sparked extensive research into relocating LLM parameters from expensive GPUs to external host memory. However, the restricted bandwidth between the host and GPU memory limits the inference performance of existing solutions. this work introduces Hermes, a budget-friendly system that leverages the near-data processing units (NDP) within commodity DRAM DIMMs to enhance the performance of a single consumer-grade GPU, achieving efficient LLM inference. We recognize that the inherent activation sparsity in LLMs naturally divides weight parameters into two categories, termed 'hot' and 'cold' neurons, respectively. Hot neurons, which consist of only approximately 20% of all weight parameters, account for 80% of the total computational load. In contrast, cold neurons make up the other 80% of parameters but are responsible for just 20% of the computational workload. Leveraging this observation, we propose a heterogeneous computing strategy: mapping hot neurons to a single computation-efficient GPU without large-capacity HBMs, while offloading cold neurons to NDP-DIMMs, which offer large memory size but limited computation capabilities. In addition, the dynamic nature of activation sparsity necessitates a real-time partition of hot and cold neurons and adaptive remapping of cold neurons across multiple NDP-DIMM modules. To tackle these issues, we introduce a lightweight predictor that ensures optimal real-time neuron partition and adjustment between GPU and NDP-DIMMs. Furthermore, we utilize a window-based online scheduling mechanism to maintain load balance among multiple NDP-DIMM modules. In summary, Hermes facilitates the deployment of LLaMA2-70B on consumer-grade hardware

关键词： Budget control

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L2SCD: Low-Latency Serverless computing Dispatcher via Programmable Network Hardware 20th

L2SCD: Low-Latency Serverless Computing Dispatcher via Prog...

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20th IFIP WG 10.3 international Conference on Network and Parallel computing, NPC 2024

作者： Liu, Song Luo, Yangyu Xu, Jiapei Yuan, Xinjing Zhang, Jianzhong College of Computer Science and DISSec Nankai University Tianjin China

ISBN: (纸本)9789819628292

the serverless computing dispatcher receives many requests in user space and distributes them to worker nodes. these requests traverse between kernel space and user space, which increases the dispatching latency. For workflows with extremely short execution times that are invoked thousands of times per second, this latency significantly affects their completion time. therefore, minimizing dispatching latency is crucial to ensuring the responsiveness of workflows. Drawing on the capabilities of modern programmable network devices, we introduce a serverless computing dispatcher that runs on DPU and programmable switches. At the DPU, the dispatcher uses DPDK to extract request information and add it to the packet header. At the programmable switch, the dispatcher executes the dispatching algorithm and forwards the request to the appropriate function at line speed, avoiding the request in the kernel space and user space transmission time and reducing scheduling latency. Experiments demonstrate that, in high concurrency scenarios, L2SCD significantly reduces the average and P99 latency of single function invoking, improving performance by 15× and 27×, compared to two baselines on average, respectively. © IFIP international Federation for Information Processing 2025.

关键词： Cloud computing In-Network computing Serverless

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From theory to Practice of Multidimensional Big Data Analytics over Big Healthcare Data: A Real-Life Case Study 28th

From Theory to Practice of Multidimensional Big Data Analyti...

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28th international symposium on Database Engineered Applications, IDEAS 2024

作者： Cuzzocrea, Alfredo Hafsaoui, Abderraouf Gallo, Carmine iDEA Lab University of Calabria Rende Italy Department of Computer Science University of Paris City Paris France

ISBN: (纸本)9783031834714

this paper provides practical and experimental results coming from the real-life research project that focuses on Big Data Analytics over Big Healthcare Data about chronical pain of patients in real-life hospitals and medical centers of North Italy (Region Lombardy), named as Pain-RELife. In this context, we devise innovative Multidimensional Big Data Analytics tools and a reference Cloud-based architecture that implements our analytics paradigm. Finally, we provide our analytical results based on advanced tools such as Multidimensional Clustering and Multidimensional Regression. © the Author(s), under exclusive license to Springer Nature Switzerland AG 2025.

关键词： Advanced Big Data Systems Healthcare Data Science Multidimensional Big Data Analytics Tools

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Diagnosability of the Lexicographic Product of Paths and Complete Bipartite Graphs Under PMC Model 20th

Diagnosability of the Lexicographic Product of Paths and...

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20th IFIP WG 10.3 international Conference on Network and Parallel computing, NPC 2024

作者： Chen, Bu Li, Feng Computer College Qinghai Normal University Xi’ning China

ISBN: (纸本)9789819628292

the processors within a multiprocessor system use an interconnection network for communication and data transmission, hence the structure of the interconnection network determines various aspects of the system’s performance. In the event of processor failures within the system, the system’s fault diagnosis capability is very significant. Diagnosability is the crucial parameter for evaluating the fault diagnosis capability of the interconnection network in multiprocessor systems. Studying diagnosability using diagnosis model such as the PMC model is beneficial for improving and optimizing multiprocessor systems. this paper uses the lexicographic product to generate a network structure Pm∘Kx,y which helps maintain the system’s parallel processing capability and high-performance computing. When m≥4, x+y≥5 and y>x, the diagnosability of Pm∘Kx,y under the PMC model is found to be 2x+y, and when 0≤h © IFIP international Federation for Information Processing 2025.

关键词： Interconnection networks (circuit switching)

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FRIDA: Reconfigurable Arrays for Dynamically Scheduled high-Level Synthesis 25

FRIDA: Reconfigurable Arrays for Dynamically Scheduled High-...

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33rd ACM/SIGDA international symposium on Field-Programmable Gate Arrays, FPGA 2025

作者： Coulon, Louis Ramirez, Lucas Anderson, Jason Stojilović, Mirjana Ienne, Paolo School of Computer and Communication Sciences EPFL Lausanne Switzerland Electrical and Computer Engineering Department University of Toronto Toronto Canada

ISBN: (纸本)9798400713965

Reconfigurable computing fabrics include FPGAs and CGRAs. FPGAs offer flexible bit-level reconfigurability and can map almost any program via high-level synthesis (HLS) compilers, but they incur high area and speed overheads compared to ASICs. CGRAs, in contrast, provide ASIC-like performance but limited flexibility, typically supporting only feedforward programs with unambiguous memory accesses, far from the capabilities of HLS compilers. this work introduces a new class of reconfigurable arrays inspired by modern dynamically scheduled HLS (DHLS) tools. Unlike traditional HLS, DHLS compilers no longer produce explicit state machines, eliminating the need for look-up tables. Instead, they delegate scheduling decisions to a set of coarse-grained primitives. Our arrays leverage these primitives as processing elements and combine FPGA-style interconnect topology for high routing flexibility with CGRA-like bus-based interconnect. We present a framework to explore these arrays and evaluate a preliminary architecture using DHLS benchmarks. the results show an average of ∼2× speed improvement, but unfortunately only a ∼20% area reduction compared to an FPGA implemented on the same technology node. © 2025 Copyright held by the owner/author(s).

关键词： Program compilers

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Dynamic Sharded Blockchain architecture for Industrial Emergency Data Sharing 18th

Dynamic Sharded Blockchain Architecture for Industrial Emer...

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18th international Conference on Wireless Artificial Intelligent computing Systems and Applications, WASA 2024

作者： Ren, Linjie Xu, Tianyi Guo, Runkun Wang, Cong Qiu, Tie College of Intelligence and Computing Tianjin University Tianjin300350 China Questrom School of Business Boston University BostonMA02215 United States School of Computer Qinghai Minzu University Xining810007 China

ISBN: (纸本)9783031714665

Sharding is a recognized solution for improving blockchain performance in industrial data sharing. Current sharding systems can periodically adjust shards to adapt to dynamic manufacturing scenarios, but they struggle to ensure low latency for emergency tasks that are massive, unpredictable, and time-sensitive because they cannot adjust shards at runtime. To address these problems, we present DSBA, a novel dynamic sharded blockchain architecture that enhances the performance of industrial emergency data sharing. Firstly, we propose a hierarchical architecture that segregates verification and consensus functions to prioritize time-sensitive emergency tasks while preserving the inherent concurrency of sharding. Secondly, we implement a dynamic sharding method based on reputation diffusion to select reliable endorsement nodes of high performance to construct shards, thereby ensuring efficient and secure emergency data sharing. Finally, we design an efficient micro-block synchronization mechanism to expedite the final consistency of emergency data. through analysis and extensive experiments, DSBA achieves a 50% decrease in emergency transaction latency and reduces the failure rate to below 20% when compared to existing sharding systems. © the Author(s), under exclusive license to Springer Nature Switzerland AG 2025.

关键词： Blockchain Dynamic Sharding Emergency Data Sharing Industrial Internet of things(IIoT)

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MLPerf Power: Benchmarking the Energy Efficiency of Machine Learning Systems from μWatts to MWatts for Sustainable AI 31

MLPerf Power: Benchmarking the Energy Efficiency of Machine ...

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31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Tschand, Arya Rajan, Arun Tejusve Raghunath Idgunji, Sachin Ghosh, Anirban Holleman, Jeremy Kiraly, Csaba Ambalkar, Pawan Borkar, Ritika Chukka, Ramesh Cockrell, Trevor Curtis, Oliver Fursin, Grigori Hodak, Miro Kassa, Hiwot Lokhmotov, Anton Miskovic, Dejan Pan, Yuechao Manmathan, Manu Prasad Raymond, Liz John, Tom St. Suresh, Arjun Taubitz, Rowan Zhan, Sean Wasson, Scott Kanter, David Reddi, Vijay Janapa Meta United States Harvard University United States NVIDIA United States UNC Charlotte / Syntiant United States Codex Dell United States Intel United States SMC Japan FlexAI / cTuning AMD United States KRAI Google United States Decompute GATE Overflow India MLCommons

ISBN: (纸本)9798331506476

Rapid adoption of machine learning (ML) technologies has led to a surge in power consumption across diverse systems, from tiny IoT devices to massive datacenter clusters. Benchmarking the energy efficiency of these systems is crucial for optimization, but presents novel challenges due to the variety of hardware platforms, workload characteristics, and system-level interactions. this paper introduces MLPerf® Power, a comprehensive benchmarking methodology with capabilities to evaluate the energy efficiency of ML systems at power levels ranging from microwatts to megawatts. Developed by a consortium of industry professionals from more than 20 organizations, coupled with insights from academia, MLPerf Power establishes rules and best practices to ensure comparability across diverse architectures. We use representative workloads from the MLPerf benchmark suite to collect {1, 8 4 1} reproducible measurements from 60 systems across the entire range of ML deployment scales. Our analysis reveals trade-offs between performance, complexity, and energy efficiency across this wide range of systems, providing actionable insights for designing optimized ML solutions from the smallest edge devices to the largest cloud infrastructures. this work emphasizes the importance of energy efficiency as a key metric in the evaluation and comparison of the ML system, laying the foundation for future research in this critical area. We discuss the implications for developing sustainable AI solutions and standardizing energy efficiency benchmarking for ML systems. © 2025 IEEE.

关键词： computer architecture energy efficiency machine learning mlperf sustainable ai

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