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Generative AI Techniques for the Simulation of Groundwater Well Data at Hanford Site

Generative AI Techniques for the Simulation of Groundwate...

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20th international Conference on Data Science, ICDATA 2024, held as part of the World Congress in computer Science, computer Engineering and Applied computing, CSCE 2024

作者： Rivera-Noriega, Fabiola De La Noval, Alejandro Upadhyay, Himanshu Lagos, Leonel Soni, Jayesh Florida International University MiamiFL33199 United States

ISBN: (纸本)9783031858550

this study compares the quality of synthetic data generated by four generative AI algorithms: Conditional Generative Adversarial Networks (CGAN), Variational Autoencoders (VAE), Synthetic Minority Over-sampling Technique for Regression (SMOTER), and Time Generative Adversarial Networks (TimeGAN). these models are trained on groundwater well data sourced from the Hanford site in Washington, USA, which has substantial missing data samples. Using these models, additional data were generated to replace these missing values. the datasets generated from each model are evaluated using a Gradient Boosting algorithm, and their data distributions are visualized. Comparative analysis reveals that the CGAN model produced synthetic data with a probability distribution closest to the original dataset. Furthermore, when the CGAN-generated dataset was combined with the original dataset, it yielded the best performance metrics among all generated datasets, demonstrating its excellence in effectively generating high-quality synthetic data. this highlights the potential of CGANs in addressing the challenges posed by missing data in environmental studies. © the Author(s), under exclusive license to Springer Nature Switzerland AG 2025.

关键词： Normal distribution

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20th international Conference on Foundations of computer Science, FCS 2024, and 20th international Conference on Frontiers in Education, FECS 2024, held as part of the World Congress in computer Science, computer Engineering and Applied computing, CSCE 2024

20th International Conference on Foundations of Computer Sci...

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20th international Conference on Foundations of computer Science, FCS 2024, and 20th international Conference on Frontiers in Education, FECS 2024, held as part of the World Congress in computer Science, computer Engineering and Applied computing, CSCE 2024

ISBN: (纸本)9783031859298

the proceedings contain 38 papers. the special focus in this conference is on Foundations of computer Science. the topics include: Exploring Efficient but Intricate Delivery Truck Routing Heuristics in Supply Chain Management;a Novel Simple Data Structure for Selecting, Inserting, and Deleting in Square Root Time;Autosymmetry Using GF(2) Matrices;TOIChain™: A Proposal for high performance Tamper Resistant Transactions Without Scaling Limits;searching Real Numbers in Constant Time;MultiMap Implementation in OpenJDK;optimization of the Floyd-Warshall Shortest Path Algorithm;triangle Packing in Graphs with Bounded Degree;navigating the Ethical Landscape of Big Data Collection and Analysis;Assessing ABET’s Outcomes through a Software Engineering Capstone Course;ECAF: Educational Cybersecurity Assessment Framework for Small Businesses;Leveraging Chat-GPT to Generate Educational Assessment Materials for Software Engineering;a Longitudinal Study to Investigate the Impact of a Service-Learning Course on Its Participants;tertiary Mathematics Students in Different Learning Environments: Perceptions and Achievement;using Logical Fallacies to Educate computer Science Students;Assessing ChatGPT for Algorithm Time Complexity Education;capstone Projects as Ventures to New Knowledge;exploratory Physics Laboratory Experiments;A Personal Tutoring Bot with VR/AR Tools;ES4AL: A Website for Effectiveness Study for Algorithm Learning in computer Science;INDRA: A Drone Penetration Testing Platform for Cybersecurity Education;Exploring the Potential of Generative AI in Education: Opportunities, Challenges, and Best Practices for Classroom Integration;digital Badging as a Motivator in an Undergraduate Course;Coding Process Visualizations for Improved Learning and Academic Integrity in CS1;OBDev: Wireless On Board Development Environment for Raspberry Pi Pico W;unravelling Dropout Intentions: Multifaceted Factors Influencing Student Retention in computer Science Education;to Hack or Not to H

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More than Automation: User Insights into the Functionality and Interface of Wheelchair-Mounted Robotic Arms 25

More Than Automation: User Insights into the Functionality a...

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ACM/IEEE international Conference on Human-Robot Interaction (HRI)

作者： Lesong Jia Breelyn Kane Styler Na Du School of Computing and Information University of Pittsburgh Pittsburgh USA Human Engineering Research Laboratories VA Pittsburgh Healthcare System Pittsburgh USA

ISBN: (数字)9798350378931

ISBN: (纸本)9798350378948

While voice-controlled automated Wheelchair-mounted robotic arms (WMRAs) could potentially offer more natural and simplified interactions than manual control, they introduce new challenges related to human-robot collaboration. To explore user expectations in terms of functionality and interface, we conducted semi-structured interviews with 13 powered wheelchair users who have upper limb impairments. A prototype with a robotic arm, a camera, and a Unity-based simulated interface was developed to help users understand the concept and functionality of the voice-controlled automated WMRA system during interviews. With safety as a priority, we found that users prioritized the WMRA's ability to grasp objects in challenging positions, such as on the ground or at high locations, and emphasized the need for a versatile gripper. Users also expected the WMRA to assist in performing complex daily tasks, with varying expectations for its performance based on task difficulty. Regarding the interface, users sought more information about the system's awareness and task execution, while emphasizing the importance of avoiding information overload. the demand for detailed safety information, such as temperature and gripping force, pointed to the need for enhanced sensor capabilities in the WMRA system. Additionally, concerns about privacy underscored the need for clear communication on privacy policies. Our results provide user-centered insights for automated WMRA, offering design implications and future research directions in areas such as user modeling, hardware, algorithms, and interface development.

关键词： Privacy Limbs Wheelchairs Human-robot interaction Grasping Manipulators Hardware Safety Mobile robots Interviews

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Vector Register Sharing Mechanism for high performance Hardware Acceleration 30th

Vector Register Sharing Mechanism for High Performance Hard...

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30th international Conference on Parallel and Distributed Processing Techniques, PDPTA 2024, held as part of the World Congress in computer Science, computer Engineering and Applied computing, CSCE 2024

作者： Tanaka, Tomoaki Kato, Michiya Osana, Yasunori Miyoshi, Takefumi Tada, Jubee Tanaka, Kiyofumi Nakajo, Hironori Department of Electrical Engineering and Computer Science Graduate School of Engineering Tokyo University of Agriculture and Technology 2-24-16 Nakacho Tokyo Koganei-shi184-8588 Japan Research and Education Institute for Semiconductors and Informatics Kumamoto University 2-39-1 Kurokami Kumamoto Chuo-ku860-8555 Japan WasaLabo LLC. K-2 Buransyu 6-5-20 Minaminaruse Tokyo Machida-shi194-0045 Japan Graduate School of Science and Engineering Yamagata University 1-4-12 Kojirakawa-machi Yamagata Yamagata-shi990-8560 Japan Japan Advanced Institute of Science and Technology 1-1 Asahidai Ishikawa Nomi923-1292 Japan Division of Advanced Information Technology Computer Science Institute of Engineering Tokyo University of Agriculture and Technology 2-24-16 Nakacho Tokyo Koganei-shi184-8588 Japan

ISBN: (纸本)9783031856372

In recent years, demand for data-parallel processing has been growing, and this parallelism often appears in AI processes. One method to accelerate these processes is using DSA, domain-specific architecture. A common data transfer method on DSA is DMA, which is direct memory access. there are several studies on DMA-based accelerators. However, few studies focus on data transfer methods. In this paper, a vector register-sharing mechanism has been proposed as a new data transfer method. Our proposed mechanism is named "SHAVER". In this mechanism, a part of vector registers is directly shared with an accelerator. An open-source RISC-V vector co-processor is used to evaluate the mechanism’s potential. It has been implemented on an FPGA and a simulator for the evaluations. the results indicate the possibility of the proposal mechanism to achieve a maximum of 7.13% speedup over DMA transfer. © the Author(s), under exclusive license to Springer Nature Switzerland AG 2025.

关键词： Vectors

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Processing Neocognitron of Face Recognition on high performance Environment Based on GPU with CUDA architecture

Processing Neocognitron of Face Recognition on High Performa...

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20th international symposium on computer architecture and high performance computing

作者： Poli, Gustavo Saito, Jose Hiroki Mari, Joao F. Zorzan, Marcelo R. Univ Fed Sao Carlos Dept Comp BR-13560 Sao Carlos SP Brazil

ISBN: (纸本)9780769534237

this work presents an implementation of Neocognitron Neural Network, using a high performance computing architecture based on GPU (Graphics Processing Unit). Neocognitron is an artificial neural network, proposed by Fukushima and collaborators, constituted of several hierarchical stages of neuron layers, organized in. two-dimensional matrices called cellular planes. For the high performance computation of Face Recognition application using Neocognitron it was used CUDA (Compute Unified Device architecture) as API (Application Programming Interface) between the CPU and the GPU, from GeForce 8800 GTX of NVIDIA company, with 128 ALU's. As face image databases it was used a face database created at UFS-Car and the CMU-PIE (Carnegie Mellon University Pose, Illumination and Expression) database. the load balancing was achieved through the use of cellular connections as threads organized in blocks, following the CUDA philosophy), of development. the results showed the feasibility of this type of device as a massively parallel data processing tool, and that smaller the granularity and the data dependency of the parallel processing, better is its performance.

关键词： Graphics processing unit

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A Methodology for Developing high Fidelity Communication Models for Large-scale Applications Targeted on Multicore Systems

A Methodology for Developing High Fidelity Communication Mod...

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20th international symposium on computer architecture and high performance computing

作者： Lively, Charles W. Taylor, Valerie E. Alam, Sadaf R. Vetter, Jeffrey S. Texas A&M Univ College Stn TX 77843 USA Oak Ridge Natl Lab Oak Ridge TN USA

ISBN: (纸本)9780769534237

Resource sharing and implementation of software stack for emerging multicore processors introduce performance and scaling challenges for large-scale scientific applications, particularly on systems with thousands of processing elements. Traditional performance optimization, tuning and modeling techniques that rely on uniform representation of computation and communication requirements are only partially useful due to the complexity of applications and underlying systems and software architecture. In this paper, we propose a workload modeling methodology that allows application developers to capture and represent hierarchical decomposition and distribution of their applications thereby allowing them to explore and identify optimal mapping of a workload on a target system. We demonstrate the proposed methodology on a Teraflopsscale fusion application that is developed using message-passing (MPI) programming paradigm. Using our analysis and projection results, we obtain insight into the performance characteristics of the application on a quad-core system and also identify optimal mapping on a Teraflops-scale platform.

关键词： Message passing

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Hiding Communication Delays in Clustered Microarchitectures

Hiding Communication Delays in Clustered Microarchitectures

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20th international symposium on computer architecture and high performance computing

作者： LaDuca, Robert J. Sharkey, Joseph J. Ponomarev, Dmitry V. BAE Systems Assured Information Security State University of New York at Binghamton

ISBN: (纸本)9780769534237

Clustered microarchitectures represent a viable solution for addressing wire delays in communication-bound architectures by partitioning monolithic datapath structures into smaller components. While supporting high frequencies, clustered processors usually degrade the instruction throughput due to the inter-cluster communication delays and non-balanced workload distribution. In this paper, we propose and evaluate novel instruction steering policies to reduce or eliminate cross-cluster communication delays while respecting workload balance. Our first technique hides the inter-cluster communication latencies by examining operand readiness information. the proposed policy steers instructions with two register sources to the cluster predicted to generate the last-produced operand. While the later-produced operand is being generated, the transport of the early-produced operand can occur in parallel, hiding the communication delay. Our second technique steers an entire group of instructions co-renamed in a cycle to the same cluster if the number of intra-group register dependencies exceed a threshold. this is done in a round-robin fashion in order to reduce impact on workload balancing.

关键词： computer architecture

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A high performance Massively Parallel Approach for Real Time Deformable Body Physics Simulation

A High Performance Massively Parallel Approach for Real Time...

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20th international symposium on computer architecture and high performance computing

作者： de Farias, thiago S. M. C. Almeida, Mozart W. S. Teixeira, Joao Marcelo X. N. Teichrieb, Veronica Kelner, Judith Univ Fed Pernambuco UFPE Comp Sci Ctr CIn Virtual Real & Multimedia Res Grp GRVM BR-50670901 Recife PE Brazil

ISBN: (纸本)9780769534237

Single processor technology has been evolving across last decades, but due to physical limitations of chip manufacturing process, the industry is pursuing alternatives to sustain computational power growth, including the creation of multi-core systems. Parallel computing targets problems that are scalable and possibly distributed, dividing the problem into smaller pieces. this approach may be explored to satisfy real time constraints required by real time physics simulation. this work introduces an optimal solution to implement accurate simulation of deformable bodies in real time. this is accomplished through the use of a meshless simulation technique, known as Point Based Animation, implemented using a parallel framework 'the NVIDIA Compute Unified Device architecture (CUDA). Our implementation showed significative improvements on performance in comparison to the former CPU one: impressive speedups around 20x could be achieved in the simulation of deformable bodies with 575 physical elements (phyxels) and 53,504 surface elements (surfels).

关键词： Deformation

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Scan islands - A scan partitioning architecture and its implementation on the Alpha 21364 processor 20

Scan islands - A scan partitioning architecture and its impl...

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20th IEEE VLSI Test symposium (VTS 02)

作者： Bhavsar, DK Davies, RA Intel Corp Shrewsbury MA 01545 USA

the paper presents a pragmatic scan partitioning architecture that allows less than perfect scan design in high performance, VLSI circuits to cost-effectively achieve test development and manufacturing test goals. the... 详细信息

ISBN: (纸本)0769515703

关键词： Automatic control Automatic test pattern generation Centralized control Circuit testing computer aided manufacturing computer architecture high performance computing Microprocessors Pins Very large scale integration

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Practical data value speculation for future high-end processors

Practical data value speculation for future high-end process...

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20th IEEE international symposium on high performance computer architecture, HPCA 2014

作者： Perais, Arthur Seznec, André IRISA/INRIA Rennes France

Dedicating more silicon area to single thread performance will necessarily be considered as worthwhile in future - potentially heterogeneous - multicores. In particular, Value prediction (VP) was proposed in the mid 9... 详细信息

ISBN: (纸本)9781479930975

关键词： data dependency PROCESSOR thREADS Program thread

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