the proceedings contain 72 papers. the topics discussed include: fitting the router characteristics in NoCs to meet QoS requirements;a small area 8bits 50MHz CMOS DAC for bluetooth transmitter;router architecture for ...
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ISBN:
(纸本)9781595938169
the proceedings contain 72 papers. the topics discussed include: fitting the router characteristics in NoCs to meet QoS requirements;a small area 8bits 50MHz CMOS DAC for bluetooth transmitter;router architecture for high-performance NoCs;a 9.6 Kb/s CMOS FSK MODEM for data transmission through power lines;a 4.1 GHz prescaler using double data throughput E-TSPC structures;TrACS: transcevier architecture and wireless channel simulator;a CMOS AM demodulator for instrumentation applications;design of digital FM demodulator based on a 2nd° order all-digital phase-locked loop;digital PM demodulator for Brazilian data collecting system;a unified and reconfigurable Montgomery multiplier architecture without four-to-two CSA;optimization techniques for a reconfigurable, self-timed, and bit-serial architecture;RoSA: a reconfigurable stream-based architecture;and a reconfigurable platform for multi-service edge routers.
In this work the design and implementation of a fully integrated ISO 11784/5 RFID reader front-end ASIC is presented, for both HDX and FDX transponder types. the ASIC was designed in a 0.18 μm. CMOS-HV technology, an...
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the proceedings contain 112 papers. the topics discussed include: BSIM compact MOSFET models for SPICE simulation;a mixed-design technique for integrated MEMS using a circuit simulator with HDL;on the use of compact m...
ISBN:
(纸本)9788363578015
the proceedings contain 112 papers. the topics discussed include: BSIM compact MOSFET models for SPICE simulation;a mixed-design technique for integrated MEMS using a circuit simulator with HDL;on the use of compact modeling for RF/analog design automation;the art of modeling and predictive simulation in power electronics and microsystems;a compact model of VES-BJT device;femtosecond precision via RF backplane in MTCA crates;design and preliminary evaluation of integrated radiation spectrometer for longitudinal e-bunch diagnostics at FELs;software components of MTCA-based image acquisition system;a continuous-time instrumentation amplifier employing a novel auto-zeroing structure;a simple 1 GHz non-overlapping two-phase clock generators for SC circuits;and cascode amplifiers with low-gain variability using body-biasing temperature and supply compensation.
this paper proposes a low-noise area-efficient voltage bandgap reference (BGR) for neural applications in 180 nm CMOS TSMC process. A single resistor is placed between the bipolars base terminals of the BGR core repla...
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this work presents the design and implementation details of a current generator intended to be used in a temperature sensor. the generator gives rise to both a PTAT and a reference current. the reference current is re...
In the physical design of VLSI circuits, the placement and routing steps are responsible for finding cell positions and interconnecting cell pins. they significantly impact the circuit layout quality. Placement and ro...
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ISBN:
(数字)9798331522124
ISBN:
(纸本)9798331522131
In the physical design of VLSI circuits, the placement and routing steps are responsible for finding cell positions and interconnecting cell pins. they significantly impact the circuit layout quality. Placement and routing were originally solved separately in a divide-and-conquer approach to cope withdesign complexity, resulting in a decoupling that often leads to poor solutions. To mitigate this problem, a few techniques seeking to integrate those steps have recently emerged. Unfortunately, some of those techniques do not consider the detailed placement information, making it difficult to evaluate their outcomes. In this paper, we present GRCMO, a technique that optimizes Global Routing by moving a few cells to their medians, respecting the detailed placement rules, and rerouting the affected nets. GRCMO was implemented in the well-established open-source platform OpenROAD, making its use within a complete RTL-to-GDSII flow possible. Experimental results using the ISPD 2018 Contest circuits showed that, in comparison to the standard global routing solutions from OpenROAD, GRCMO is able to reduce the estimated wirelength by 0.43%, on average, and from 0.5% up to 0.7% for the biggest circuits, requiring less than 20 iterations and moving 2.61% of the cells, on average.
this work presents the design and implementation details of a current generator intended to be used in a temperature sensor. the generator gives rise to both a PTAT and a reference current. the reference current is re...
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ISBN:
(数字)9798331522124
ISBN:
(纸本)9798331522131
this work presents the design and implementation details of a current generator intended to be used in a temperature sensor. the generator gives rise to both a PTAT and a reference current. the reference current is realized by a proper combination of a PTAT current and a CTAT current. the ratio of the PTAT current to the reference current contains the temperature information, which can be converted into time via relaxation oscillators, and then from time to digital via a counter. To generate the currents, a MOSFET-based current generator supplied with 900 mV and consuming less than 450 $n A$ is proposed. the simulation results show that the error of the current ratio when translated to temperature is less than $\pm 1.7\ { }^{\circ} \mathrm{C}$ at $32{ }^{\circ} \mathrm{C}$ and less than $\pm 3.1{ }^{\circ} \mathrm{C}$ at $-20{ }^{\circ} \mathrm{C}$ and $85{ }^{\circ} \mathrm{C}$ . the one-point calibration of the current generator was carried out through an exponentially scaled network of integrated resistors.
In this paper we present a novel digital design technique called soft-well circuit design improving digital circuits in fine-pitch technology. Improved noise immunity, higher-speed and reduced static power leakage may...
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ISBN:
(纸本)9781595938169
In this paper we present a novel digital design technique called soft-well circuit design improving digital circuits in fine-pitch technology. Improved noise immunity, higher-speed and reduced static power leakage may be traded for somewhat increased silicon area. the importance of soft-well design may increase in future technology where leakage and noise immunity is expected to severely impact circuit performance.
this paper describes the design of a CAMS IC AM demodulator. design details of the monolithic implementation of a highly accurate synchronous rectifier in a standard 0.35 mu m CMOS process on a +/- 2.5 V voltage suppl...
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ISBN:
(纸本)9781595938169
this paper describes the design of a CAMS IC AM demodulator. design details of the monolithic implementation of a highly accurate synchronous rectifier in a standard 0.35 mu m CMOS process on a +/- 2.5 V voltage supply are presented. the derived circuit implements an envelope detector with a +/- 1.5 V output swing on a 15 pF load. Small distortion (thD = -60 dB) and low noise (SNR = 84.7 dB) are some attractive features of the proposed design.
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