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检索条件"任意字段=21st ACM Symposium on Parallelism in Algorithms and Architectures"

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SPAA'09 - Proceedings of the 21st Annual symposium on parallelism in algorithms and architectures

SPAA'09 - Proceedings of the 21st Annual Symposium on Parall...

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21st Annual symposium on parallelism in algorithms and architectures, SPAA'09

ISBN: (纸本)9781605586069

The proceedings contain 43 papers. The topics discussed include: speed scaling of processes with arbitrary speedup curves on a multiprocessor;the bell is ringing in speed-scaled multiprocessor scheduling;mapping filtering streaming applications with communication costs;scheduling to minimize staleness and stretch in real-time data warehouses;parameterized maximum and average degree approximation in topic-based publish-subscribe overlay network design;selfishness in transactional memory;at-most-once semantics in asynchronous shared memory;memory models: a case for rethinking parallel languages and hardware;the life and times of a ZooKeeper;Cassandra - a structured storage system on a P2P network;Pregel: a system for large-scale graph processing;towards transactional memory semantics for C++;on avoiding spare aborts in transactional memory;inherent limitations on disjoint-access parallel implementations of transactional memory;reducers and other Cilk++ hyperobjects;and beyond nested parallelism: tight bounds on work-stealing overheads for parallel futures.

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SPAA'09: Proceedings of the Twenty-First Annual symposium on parallelism in algorithms and architectures - Foreword

Annual ACM Symposium on Parallelism in Algorithms and Archit...

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Annual acm symposium on parallelism in algorithms and architectures 2009年 iii页

作者： Bender, Michael A. Stony Brook University Tokutek Inc. United States

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Hybrid CPU-GPU scheduling and execution of tree traversals 16

Hybrid CPU-GPU scheduling and execution of tree traversals

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21st acm SIGPLAN symposium on Principles and Practice of Parallel Programming (PPoPP)

作者： Liu, Jianqiao Hegde, Nikhil Kulkarni, Milind Purdue Univ Sch Elect & Comp Engn W Lafayette IN 47907 USA

ISBN: (纸本)9781450340922

GPUs offer the promise of massive, power-efficient parallelism. However, exploiting this parallelism requires code to be carefully structured to deal with the limitations of the SIMT execution model. In recent years, there has been much interest in mapping irregular applications to GPUs: applications with unpredictable, data-dependent behaviors. While most of the work in this space has focused on ad hoc implementations of specific algorithms, recent work has looked at generic techniques for mapping a large class of tree traversal algorithms to GPUs, through careful restructuring of the tree traversal algorithms to make them behave more regularly. Unfortunately, even this general approach for GPU execution of tree traversal algorithms is reliant on ad hoc, handwritten, algorithm-specific scheduling (i.e., assignment of threads to warps) to achieve high performance. The key challenge of scheduling is that it is a highly irregular process, that requires the inspection of thread behavior and then careful sorting of the threads into warps. In this paper, we present a novel scheduling and execution technique for tree traversal algorithms that is both general and automatic. The key novelty is a hybrid approach: the GPU partially executes tasks to inspect thread behavior and transmits information back to the CPU, which uses that information to perform the scheduling itself, before executing the remaining, carefully scheduled, portion of the traversals on the GPU. We applied this framework to five tree traversal algorithms, achieving significant speedups over optimized GPU code that does not perform application-specific scheduling. Further, we show that in many cases, our hybrid approach is able to deliver better performance even than GPU code that uses hand-tuned, applicationspecific scheduling.

关键词： Heterogeneous architectures Scheduling Irregular applications Tree traversal

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Performance evaluation of interthread communication mechanisms on multicore/multithreaded architectures 12

Performance evaluation of interthread communication mechanis...

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21st acm symposium on High-Performance Parallel and Distributed Computing, HPDC '12

作者： Meneghin, Massimiliano Pasetto, Davide Franke, Hubertus Petrini, Fabrizio Xenidis, Jimi IBM Research Lab. Dublin Ireland IBM T.J. Watson Yorktown Heights NY United States IBM Research Lab. Austin TX United States

ISBN: (纸本)9781450308052

The three major solutions for increasing the nominal performance of a CPU are: multiplying the number of cores per socket, expanding the embedded cache memories and use multi-threading to reduce the impact of the deep memory hierarchy. Systems with tens or hundreds of hardware threads, all sharing a cache coherent UMA or NUMA memory space, are today the de-facto standard. While these solutions can easily provide benefits in a multi-program environment, they require recoding of applications to leverage the available parallelism. Threads must synchronize and exchange data, and the overall performance is heavily influenced by the overhead added by these mechanisms, especially as developers try to exploit finer grain parallelism to be able to use all available resources. Copyright © 2012 acm.

关键词： Cache memory

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Allocation and Scheduling of Dataflow Graphs on Hybrid Dataflow/von Neumann architectures 23

Allocation and Scheduling of Dataflow Graphs on Hybrid Dataf...

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21st acm/IEEE International symposium on Formal Methods and Models for System Design (MEMOCODE)

作者： Bhagyanath, Anoop Kercher, Nadine Schneider, Klaus RPTU Kaiserslautern Landau Dept Comp Sci Kaiserslautern Germany

ISBN: (纸本)9798400703188

Hybrid dataflow/von Neumann processors expose their processing units and datapaths to the compiler to exploit the instruction-level parallelism of sequential programs. Generating code from dataflow graphs for such processors that use FIFO-buffered datapaths requires (1) an allocation that maps the nodes of the dataflow graph to the processing units (PUs) of the processor, and (2) a schedule for firing the nodes on the PUs that does not violate the FIFO behavior of the buffers. In previous work, we have encoded the constraints required to ensure the FIFO behavior for the code generation as a SAT problem. In this paper, we consider PU allocation and node scheduling in isolation, inspired by the traditional compilers, which also treat register allocation and instruction scheduling as separate problems. If a schedule is given, we reduce the PU allocation problem to a graph coloring problem so that heuristics can solve it efficiently. We also perform interference analysis, similar to register interference analysis to reveal special properties of the PU allocation graph. If a PU allocation is given, the scheduling problem is almost reduced to a 2SAT problem so that it can also be solved efficiently.

关键词： dataflow graphs dataflow computing code generation exposed datapath architectures

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Comparative Framework for the Analysis of Thermal and Resource Management algorithms for Multi-Core architectures 21

Comparative Framework for the Analysis of Thermal and Resour...

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21st International symposium on Quality Electronic Design (ISQED)

作者： Akmal, Moeez Saeed, Muhammad Sarmad Sardar, Muhammad Usama Shafi, Hareem Hasan, Osman Khdr, Heba Henkel, Joerg Natl Univ Sci & Technol NUST Sch Elect Engn & Comp Sci Islamabad Pakistan Tech Univ Dresden Dresden Germany Karlsruhe Inst Technol Karlsruhe Germany

ISBN: (纸本)9781728142074

On-chip multi-core architectures have emerged as a new paradigm for executing highly parallel and resource demanding applications. However, inefficient resource management and thermal issues in these multi-core architectures may lead to performance degradation. To cater for these issues, several resource and thermal management algorithms have been proposed. These algorithms are usually analyzed independently and under different environmental settings, which makes a fair comparison between them very difficult. In order to overcome this problem, this paper presents a generic framework for analyzing various resource and thermal management algorithms under similar settings. The proposed framework is developed using C++ and has been successfully used to compare mDTM and a variant of DsRem.

关键词： Temperature control

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Integration and Evaluation of Quantum Accelerators for Data-Driven User Functions 21

Integration and Evaluation of Quantum Accelerators for Data-...

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21st International symposium on Quality Electronic Design (ISQED)

作者： Hubregtsen, Thomas Segler, Christoph Pichlmeier, Josef Sarkar, Aritra Gabor, Thomas Bertels, Koen BMW Grp Res New Technol Innovat Garching Germany Delft Univ Technol Delft Netherlands Tech Univ Munich Dept Informat Garching Germany Ludwig Maximilians Univ Munchen Munich Germany

ISBN: (纸本)9781728142074

Quantum computers hold great promise for accelerating computationally challenging algorithms on noisy intermediate-scale quantum (NISQ) devices in the upcoming years. Much attention of the current research is directed towards algorithmic research on artificial data that is disconnected from live systems, such as optimization of systems or training of learning algorithms. In this paper we investigate the integration of quantum systems into industry-grade system architectures. In this work we propose a system architecture for the integration of quantum accelerators. In order to evaluate our proposed system architecture we investigated various data-driven functions for various accelerators, including a classical system, a gate-based quantum accelerator and a quantum annealer. The data-driven function predict user preference and is trained on real-world data. This work also includes an evaluation of the quantum enhanced kernel, that previously was only evaluated on artificial data. In our evaluation, we showed that the quantum-enhanced kernel performs at least equally well to a classical state-of-the-art kernel when simulated. We also showed a low reduction in accuracy and latency numbers within acceptable bounds when running on the gate-based IBM quantum accelerator. We therefore conclude it is feasible to integrate NISQ-era devices in industry-grade system architectures in preparation for future advancements in quantum hardware.

关键词： Quantum machine learning quantum architectures quantum devices quantum modelling hybrid quantum/classical algorithms

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Allocation and Scheduling of Dataflow Graphs on Hybrid Dataflow/von Neumann architectures

Allocation and Scheduling of Dataflow Graphs on Hybrid Dataf...

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acm and IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE)

作者： Anoop Bhagyanath Nadine Kercher Klaus Schneider Department of Computer Science RPTU Kaiserslautern Landau Germany

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JParEnt: Parallel entropy decoding for JPEG decompression on heterogeneous multicore architectures 7

JParEnt: Parallel entropy decoding for JPEG decompression on...

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Euro-Par Conference / 7th International Workshop on Programming Models and Applications for Multicores and Manycores (PMAM) held in conjunction with the 21st SIGPLAN symposium on Principles and Practice of Parallel Programming (PPoPP)

作者： Sodsong, Wasuwee Jung, Minyoung Park, Jinwoo Burgstaller, Bernd Yonsei Univ Dept Comp Sci Seoul South Korea

ISBN: (纸本)9781450341967

The JPEG format employs Huffman codes to compress the entropy data of an image. Huffman codewords are of variable length, which makes parallel entropy decoding a difficult problem. To determine the start position of a codeword in the bitstream, the previous codeword must be decoded first. We present JParEnt, a new approach to parallel entropy decoding for JPEG decompression on heterogeneous multicores. JParEnt conducts JPEG decompression in two steps: (1)an efficient sequential scan of the entropy data on the CPU to determine the start-positions (boundaries) of coefficient blocks in the bitstream, followed by (2)a parallel entropy decoding step on the graphics processing unit (GPU). The block boundary scan constitutes a reinterpretation of the Huffman-coded entropy data to determine codeword boundaries in the bitstream. We introduce a dynamic workload partitioning scheme to account for GPUs of low compute power relative to the CPU. This configuration has become common with the advent of SoCs with integrated graphics processors (IGPs). We leverage additional parallelism through pipelined execution across CPU and GPU. For systems providing a unified address space between CPU and GPU, we employ zero-copy to completely eliminate the data transfer overhead. Our experimental evaluation of JParEnt was conducted on six heterogeneous multicore systems: one server and two desktops with dedicated GPUs, one desktop with an IGP, and two embedded systems. For a selection of more than 1000JPEG images, JParEnt outperforms the SIMD-implementation of the libjpeg-turbo library by up to a factor of 4.3x, and the previously fastest JPEG decompression method for heterogeneous multicores by up to a factor of 2.2x. JParEnt's entropy data scan consumes 45% of the entropy decoding time of libjpeg-turbo on average. Given this new ratio for the sequential part of JPEG decompression, JParEnt achieves up to97% of the maximum attainable speedup (95% on average). On the IGP-based desktop platform,

关键词： JPEG decoding entropy decoding prefix codes heterogeneous multicores GPU programming

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LALP: A Novel Language to Program Custom FPGA-Based architectures

LALP: A Novel Language to Program Custom FPGA-Based Architec...

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International symposium on Computer Architecture and High Performance Computing (SBAC-PAD)

作者： Ricardo Menotti Joao M.P. Cardoso Marcio M. Fernandes Eduardo Marques Coordenação de Informática Universidade Tecnológica Federal do Paraná Campo Mourao Brazil Departamento de Computação Universidade Federal de São Carlos Sao Carlos Brazil Faculdade de Engenharia Universidade do Porto Porto Portugal Institute Ciências Matemáticas e Computação Universidade de Sáo Paulo Sao Carlos Brazil

Field-Programmable Gate Arrays (FPGAs) are becoming increasingly important in embedded and high-performance computing systems. They allow performance levels close to the ones obtained from Application-Specific Integrated Circuits (ASICs), while still keeping design and implementation flexibility. However, to efficiently program FPGAs, one needs the expertise of hardware developers and to master hardware description languages (HDLs) such as VHDL or Verilog. The attempts to furnish a high-level compilation flow (e.g., from C programs) still have open issues before efficient and consistent results can be obtained. Bearing in mind the FPGA resources, we have developed LALP, a novel language to program FPGAs. A compilation framework including mapping capabilities supports the language. The main ideas behind LALP is to provide a higher abstraction level than HDLs, to exploit the intrinsic parallelism of hardware resources, and to permit the programmer to control execution stages whenever the compiler techniques are unable to generate efficient implementations. In this paper we describe LALP, and show how it can be used to achieve high-performance computing solutions.

关键词： Pipeline processing Field programmable gate arrays Clocks Counting circuits High level synthesis Computer architecture Hardware design languages Signal processing algorithms Kernel Centralized control

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