Conventional shrinking methods to improve VLSI chip performance by continual scaling of device and interconnect geometries may allow CMOS juggernaut to reach about 22 nm nodes. During the post-shrinking era, a slew of...
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ISBN:
(纸本)9781605585222
Conventional shrinking methods to improve VLSI chip performance by continual scaling of device and interconnect geometries may allow CMOS juggernaut to reach about 22 nm nodes. During the post-shrinking era, a slew of mesoscopic and nanoscale technologies such as quantum tunneling devices, plasmon based transistors, ionic transport based crossbar structures, nanomagnetic logic, grapheme FET's, self-assembled array of quantum dots, and molecular devices are likely to emerge as commercially viable technologies in order to sustain the demands for exponential economic growth throughout the first quarter of the 21st *** tunneling in nanometric devices augurs a revolutionary shift of paradigm for circuit and CAD tools design that must account for quantum effects as well as local interactions between self-assembled circuit elements. These circuit elements may consist of a 2-dimensional array of self-organized quantum dots that can be instrumented to perform cellular automata class of algorithms or a 3-dimensional array of self-organized nanowires to perform a random Boolean network (RBN) class of algorithms. The talk will also briefly introduce neuromorphic nanoarchitectures consisting of 2-D array of amorphous-Silicon based memristor devices and also THz digital systems deploying surface plasmon polariton (SPP).
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