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Proceedings - 21st international conference on field programmable logic and applications, fpl 2011

Proceedings - 21st International Conference on Field Program...

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21st international conference on field programmable logic and applications, fpl 2011

ISBN: (纸本)9780769545295

The proceedings contain 101 papers. The topics discussed include: unifying finite difference option-pricing for hardware acceleration;an evaluation of selective depipelining for FPGA-based energy-reducing irregular code coprocessors;dependable optically reconfigurable gate array with a phase-modulation type holographic memory;accelerating fluid registration algorithm on multi-FPGA platforms;modeling and evaluation of dynamic partial reconfigurable datapaths for FPGA-based systems using stochastic networks;software/hardware framework for generating parallel long-period random numbers using the well method;a run-time adaptive FPGA architecture for Monte Carlo simulations;precore - a token-based speculation architecture for high-level language to hardware compilation;implementing stream-processing applications on FPGAs: a DSL-based approach;and revisiting the Newton-Raphson iterative method for decimal division.

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A routing architecture for mapping dataflow graphs at run-time

A routing architecture for mapping dataflow graphs at run-ti...

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21st international conference on field programmable logic and applications, fpl 2011

作者： Koch, Dirk Torresen, Jim Department of Informatics University of Oslo Norway

ISBN: (纸本)9780769545295

While it is feasible with today's commercial tools to swap from one module to another, many applications demand more advanced configuration schemes, for example, to map different dataflow graphs onto an FPGA. To support this, we will improve an existing on-FPGA communication architecture in order to carry out arbitrary routing among multiple freely placed modules. This results in a circuit switching network that will be efficiently implemented directly within the FPGA routing fabric. © 2011 IEEE.

关键词： field programmable gate arrays (FPGA)

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Failure probability and fault observability of SRAM-FPGA systems

Failure probability and fault observability of SRAM-FPGA sys...

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21st international conference on field programmable logic and applications, fpl 2011

作者： Bernardeschi, Cinzia Cassano, Luca Domenici, Andrea Department of Information Engineering University of Pisa Italy

ISBN: (纸本)9780769545295

We describe a simulation-based fault injection technique for failure probability and fault observability as-sessment of SRAM-FPGA systems. Our approach relies on a model of FPGA netlists realised with the stochastic Activity Networks formalism. Faults can be injected into the model either stochastically or exhaustively one at a time. Fault propagation is traced to the output pins, using a four-valued logic that enables faulty signals to be tagged and recognized. We considered some of the ITC'99 benchmarks as examples. © 2011 IEEE.

关键词： field programmable gate arrays (FPGA)

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20Gbps C-based complex event processing

20Gbps C-based complex event processing

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21st international conference on field programmable logic and applications, fpl 2011

作者： Inoue, Hiroaki Takenaka, Takashi Motomura, Masato System IP Core Research Laboratories NEC Corporation Kawasaki Japan Graduate School of Information Science and Technology Hokkaido University Sapporo Japan

ISBN: (纸本)9780769545295

This paper presents the world's fastest complex event processing system, designed to process a large number of events on FPGAs. Unlike conventional SQL-based approaches, our approach features logic automation constructed with a new C-based event language that supports regular expressions on the basis of C functions, so that a wide variety of event-processing applications can be efficiently mapped to FPGAs. Evaluations on an FPGA-based NIC show that we have achieved 20Gbps event processing performance in a financial trading application with only a small logic increase, 2.7%. © 2011 IEEE.

关键词： field programmable gate arrays (FPGA)

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Automated resource-aware floorplanning of reconfigurable areas in partially-reconfigurable FPGA systems

Automated resource-aware floorplanning of reconfigurable are...

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21st international conference on field programmable logic and applications, fpl 2011

作者： Bolchini, Cristiana Miele, Antonio Sandionigi, Chiara Politecnico di Milano Dip. di Elettronica e Informazione P.zza L. da Vinci 32 Milano Italy

ISBN: (纸本)9780769545295

The floorplanning activity is a key step in the design of systems on FPGAs, but the approaches available today rarely consider both the constraints imposed by the heterogeneous distribution of the resources in the devices and the reconfiguration capabilities. In fact, current-generation FPGAs present a complex architecture, but also offer more sophisticated reconfiguration features. The proposed floorplanner, based on an accurate model of the devices, takes into account all these elements and finds an optimal solution, suitable for reconfigurable designs. © 2011 IEEE.

关键词： field programmable gate arrays (FPGA)

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A new process characterization method for FPGAs based on electromagnetic analysis

A new process characterization method for FPGAs based on ele...

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21st international conference on field programmable logic and applications, fpl 2011

作者： Bruguier, Florent Benoit, Pascal Maurine, Philippe Torres, Lionel LIRMM CNRS University of Montpellier 2 161 rue Ada 34095 Montpellier Cedex 5 France

ISBN: (纸本)9780769545295

Thanks to their inherent regularity and reconfigurability, FPGAs offer an ideal structure to manage process variability. Recent works from the literature have addressed the process characterization problem for FPGAs: proposed approaches rely on process sensors (ring oscillators) and a measurement subsystem implemented into the configurable logic blocks. In this article, we propose for the first time in the literature a non-invasive characterization method based on electromagnetic analysis. The whole experimental set-up is described and the characterization accuracy is discussed. This paper proves the feasibility of this new method on FPGAs. © 2011 IEEE.

关键词： field programmable gate arrays (FPGA)

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Exploring Gabor filter implementations for visual cortex modeling on FPGA

Exploring Gabor filter implementations for visual cortex mod...

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21st international conference on field programmable logic and applications, fpl 2011

作者： Cho, Yong Cheol Peter Bae, Sungmin Jin, Yongseok Irick, Kevin M. Narayanan, Vijaykrishnan Department of Computer Science and Engineering Pennsylvania State University University Park PA United States

ISBN: (纸本)9780769545295

Gabor filters are widely used to model the behavior of the V1 stage of the primary visual cortex of mammalian vision systems. Acceleration of this filter is critical for various real-time vision applications. In this work, we explore a variety of design options for the Gabor filter to tradeoff resource utilization, performance and accuracy. Our results indicate that our optimizations enable a variety of design options to meet a wide range of application constraints. © 2011 IEEE.

关键词： field programmable gate arrays (FPGA)

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High frequency trading acceleration using FPGAs

High frequency trading acceleration using FPGAs

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21st international conference on field programmable logic and applications, fpl 2011

作者： Leber, Christian Geib, Benjamin Litz, Heiner University of Heidelberg 68131 Mannheim Germany

ISBN: (纸本)9780769545295

This paper presents the design of an application specific hardware for accelerating High Frequency Trading applications. It is optimized to achieve the lowest possible latency for interpreting market data feeds and hence enable minimal round-trip times for executing electronic stock trades. The implementation described in this work enables hardware decoding of Ethernet, IP and UDP as well as of the FAst protocol which is a common protocol to transmit market feeds. For this purpose, we developed a microcode engine with a corresponding instruction set as well as a compiler which enables the flexibility to support a wide range of applied trading protocols. The complete system has been implemented in RTL code and evaluated on an FPGA. Our approach shows a 4x latency reduction in comparison to the conventional Software based approach. © 2011 IEEE.

关键词： field programmable gate arrays (FPGA)

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A comparison on FPGA of modular multipliers suitable for elliptic curve cryptography over GF(p) for specific p values

A comparison on FPGA of modular multipliers suitable for ell...

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21st international conference on field programmable logic and applications, fpl 2011

作者： Hamilton, Mark Marnane, William P. Tisserand, Arnaud Claude Shannon Institute for Discrete Mathematics Coding and Cryptography Department of Electrical and Electronic Engineering University College Cork Ireland IRISA CNRS Université Rennes 1 6 rue Kérampont 22305 Lannion France

ISBN: (纸本)9780769545295

In this paper we provide a comparison of different modular multipliers suitable for use in an elliptic curve processor, when working with a Mersenne prime modulus. Mersenne primes allow for the use of fast modular reduction techniques. Several multipliers are presented that can be implemented solely in slice logic. A design that makes use of the DSP48E blocks on Virtex 5 FPGAs is also described. The different multipliers are compared for speed, area and power consumption when implemented on a Virtex 5 FPGA. © 2011 IEEE.

关键词： field programmable gate arrays (FPGA)

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On timing yield improvement for FPGA designs using architectural symmetry

On timing yield improvement for FPGA designs using architect...

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21st international conference on field programmable logic and applications, fpl 2011

作者： Yu, Haile Xu, Qiang Leong, Philip H.W. Dept. of Computer Science and Engineering Chinese University of Hong Kong Hong Kong School of Electrical and Information Engineering University of Sydney Australia

ISBN: (纸本)9780769545295

As semiconductor manufacturing technology continues towards reduced feature sizes, timing yield will degrade due to increased process variation. This work proposes the use of architectural symmetry in FPGA so that multiple timing-equivalent configurations can be derived from a single initial implementation, allowing the application of post-silicon tuning to mitigate process variation effects. Experimental results on twenty MCNC benchmark circuits for various process technologies demonstrate timing yield improvement using the proposed method. © 2011 IEEE.

关键词： field programmable gate arrays (FPGA)

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