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Embedded Systems start-Up under Timing Constraints on Modern FPGAs

Embedded Systems Start-Up under Timing Constraints on Modern...

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international conference on field programmable logic and applications

作者： Joachim Meyer Juanjo Noguera Michael Huebner Rodney stewart Juergen Becker Institute for Information Processing Technologies Karlsruhe Institute of Technology Karlsruhe Germany Xilinx Inc. Ireland

In this paper we present novel techniques, methods and tool flows that enable embedded systems implemented on FPGAs to start-up under tight timing constraints (i.e., hard deadlines). Meeting the application deadline is achieved by exploiting the FPGA programmability in order to implement a two-stage system start-up approach, as well as a suitable memory hierarchy. This reduces the FPGA configuration time as well as the startup time of the embedded software. Thereby the start-up time for timing-critical parts of a design neither dependent on the complexity nor on the start-up time of the complete system. An automotive case study is used to demonstrate the feasibility and quantify the benefits of the proposed approach.

关键词： field programmable gate arrays Timing Hardware Embedded systems Ash Memory management

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RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

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international conference on field programmable logic and applications

作者： Christopher Lavin Marc Padilla Jaren Lamprecht Philip Lundrigan Brent Nelson Brad Hutchings NSF Center for High-Performance Reconfigurable Computing (CHREC) Department of Electrical and Computer Engineering Brigham Young University Provo UT USA

Creating CAD tools for commercial FPGAs is a difficult task. Closed proprietary device databases and unsupported interfaces are largely to blame for the lack of CAD research found on commercial architectures versus hypothetical architectures. This paper formally introduces RapidSmith, a new set of tools and APIs that enable CAD tool creation for Xilinx FPGAs. Based on the Xilinx Design Language (XDL), RapidSmith provides a compact, yet, fast device database with hundreds of APIs that enable the creation of placers, routers and several other tools for Xilinx devices. RapidSmith alleviates several of the difficulties of using XDL and this work demonstrates the kinds of research facilitated by removing such challenges.

关键词： field programmable gate arrays Wires Tiles Routing Design automation Databases Data structures

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Memory-Efficient and Fast Run-Time Reconfiguration of Regularly structured Designs

Memory-Efficient and Fast Run-Time Reconfiguration of Regula...

引用

international conference on field programmable logic and applications

作者： Brahim Al Farisi Karel Heyse Karel Bruneel Dirk stroobandt Ghent University ELlS Department Gent Belgium

Previous work has shown that run-time reconfiguration of FPGAs benefits greatly from the use of Tunable LUT (TLUT) circuits. These can be rapidly transformed into a specialized LUT circuit and are also very memory efficient when representing regularly structured designs, where the same hardware module is instantiated many times. However, the memory requirements and reconfiguration time of a run-time reconfigurable application are also dependent on the reconfiguration mechanism. In this paper, we will show that the memory requirements of conventional ICAP reconfiguration grow very fast with the number of modules, resulting in excessive memory usage. We propose to use Shift-Register-LUT (SRL) reconfiguration which is faster and results in a memory usage that is independent of the number of modules.

关键词： Table lookup field programmable gate arrays Memory management Finite impulse response filter Routing Equations Boolean functions

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FPGA Interconnect Architecture Exploration Based on a statistical Model

FPGA Interconnect Architecture Exploration Based on a Statis...

引用

international conference on field programmable logic and applications

作者： Zhen Wang Ding Xie Jinmei Lai ASIC & System State Key Laboratory Fudan University Shanghai China

This paper presents a novel statistical model to help exploring the FPGA interconnect architecture design space efficiently. A series of parameters featuring the GRM-based (General Routing Matrix) interconnect architecture are defined. By analyzing these parameters such as routing segments type, channel width and drive relation, our model is able to calculate the average hops indicator which is approved in experiments to be a good estimation of the timing performance of architectures. With our model, we evaluate hundreds of architectures and figure out the formula expressing the possible trade-offs between performance and area. We select several representatives and conclude that routing segment is still a powerful tool in design trade-offs.

关键词： Routing Solid modeling field programmable gate arrays Wires Benchmark testing Integrated circuit interconnections Integrated circuit modeling

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Scalable Arbiters and Multiplexers for On-FGPA Interconnection Networks

Scalable Arbiters and Multiplexers for On-FGPA Interconnecti...

引用

international conference on field programmable logic and applications

作者： Giorgos Dimitrakopoulos Christoforos Kachris Emmanouil Kalligeros Informatics & Communications Engineering University of West Macedonia Greece Networks Laboratory Athens Information Technology (AIT) Greece Information & Communication Systems Engineering University of the Aegean Greece

Soft on-FGPA interconnection networks are gaining increasing importance since they simplify the integration of heterogeneous components and offer, at the same time, a modular solution to the complex system-wide communication issues. The switches are the basic building blocks of such interconnection networks and their design critically affects the performance of the whole network. The way data traverse each switch is governed by the operation of the arbiter and the crossbar's multiplexers that need to be efficiently mapped on the FPGA fabric under tight area and delay constraints. This paper explores the design space of an arbiter and a multiplexer as a unified entity and proposes two new circuit alternatives that allow the design of scalable soft FPGA switches.

关键词： Multiplexing Delay field programmable gate arrays Encoding Multiprocessor interconnection System-on-a-chip Table lookup

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The Impact of Aging on an FPGA-Based Physical Unclonable Function

The Impact of Aging on an FPGA-Based Physical Unclonable Fun...

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international conference on field programmable logic and applications

作者： Abhranil Maiti Logan McDougall Patrick Schaumont Electrical and Computer Engineering Virginia Tech Blacksburg VA USA

On-chip Physical Unclonable Functions (PUFs) are emerging as a powerful security primitive that can potentially solve several security problems. A PUF needs to be robust against reversible as well as irreversible temporal changes in circuits. While the effect of the reversible temporal changes on PUFs is well studied, it is equally important to analyze the effect of the irreversible temporal changes i.e. aging on PUFs. In this work, we perform an accelerated aging testing on an FPGA-based ring oscillator PUF (RO-PUF) and analyze how it affects the functionality of the PUF. Based on our experiment using a group of 90-nm Xilinx FPGAs, we observe that aging makes PUF responses unreliable. On the other hand, the randomness of PUF responses remains unaffected despite aging.

关键词： field programmable gate arrays High definition video stress Accelerated aging System-on-a-chip

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Methods and Mechanisms for Hardware Multitasking: Executing and Synchronizing Fully Relocatable Hardware Tasks in Xilinx FPGAs

Methods and Mechanisms for Hardware Multitasking: Executing ...

引用

international conference on field programmable logic and applications

作者： Xabier Iturbe Khaled Benkrid Tughrul Arslan Raul Torrego Imanol Martinez System Level Integration Group University of Edinburgh Edinburgh UK IKERLAN-IK4 Research Alliance Embedded System-on-Chip Group Basque Spain

This paper presents the details of a novel technique which allows for the implementation and execution of completely relocatable hardware tasks onto dynamically reconfigurable FPGAs. Our novel technique harnesses the internal configuration access port (ICAP) for inter-task communication and synchronization, leading to very little logic overheads. The advantages of this technique include fault-tolerance, as tasks could be relocated freely on the fabric to circumvent damaged resources, and high performance, due to better exploitation of the logic fabric. The work is part of a larger effort in our group which aims to build a fully operational dynamically reconfigurable computer which would satisfy the often conflicting requirements of high performance, fault-tolerance and high level programming.

关键词： Hardware field programmable gate arrays Table lookup Clocks Software Synchronization Buffer storage

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Reconfiguring Distributed applications in FPGA Accelerated Cluster with Wireless Networking

Reconfiguring Distributed Applications in FPGA Accelerated C...

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international conference on field programmable logic and applications

作者： Xin Yu Niu Kuen Hung Tsoi Wayne Luk Department of Electrical and Electronic Engineering Imperial College London UK Department of Computing Imperial College London UK

FPGA accelerators are capable of improving computation and energy efficiency of many applications targeting a cluster of machines. In this work, we focus on an FPGA accelerated cluster system coupled with a wireless network. Comparing with conventional Ethernet based approaches, the proposed system with wireless network enables a light-weight and efficient method for the FPGA devices to exchange information directly. Customisable monitoring facilities are developed to support changing a distributed application dynamically at run time. The N-Body simulation application is used to demonstrate the effectiveness and potential of the proposed system. Experiments show that this approach can achieve up to 4.2 times improvement in latency. By applying the proposed inter-FPGA wireless network to the N-Body application, we achieve enhanced power efficiency while fulfilling thermal constraints in all nodes.

关键词： field programmable gate arrays Monitoring Wireless networks Temperature measurement Temperature sensors Wireless sensor networks

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A Low-Cost Sensor for Aging and Late Transitions Detection in Modern FPGAs

A Low-Cost Sensor for Aging and Late Transitions Detection i...

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international conference on field programmable logic and applications

作者： Abdulazim Amouri Mehdi Tahoori Institute of Computer Science and Engineering Karlsruhe Institute of Technology (KIT) Karlsruhe Germany

Transistor aging due to Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) is a major reliability issue for aggressive device downscaling at nanoscale. state-of-the-art FPGA chips, which use most recent CMOS technologies and smallest feature sizes to meet high performance demands, are at the front line to face this problem. In this paper, we present the design and mapping of a low-cost logic level aging sensor for FPGA-based designs. The mapping of this sensor is designed to provide controlled sensitivity, ranging from a warning sensor to late transition detector. The functionality of the sensor has been verified on a Virtex5-based board. Area, delay, and power overhead of a set of sensors mapped for most aging-critical paths of representative designs are very modest. (≈ 1.3% area, ≈ 1.6% performance, and ≈ 1.5% power overhead).

关键词： Delay Clocks Aging field programmable gate arrays Sensitivity Image edge detection Human computer interaction

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Design of a High Switching Frequency FPGA-Based SPWM Generator for DC/AC Inverters

Design of a High Switching Frequency FPGA-Based SPWM Generat...

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international conference on field programmable logic and applications

作者： Matina Lakka Eftichios Koutroulis Apostolos Dollas Department of Electronic & Computer Engineering Technical University of Crete Chania Greece

The Sinusoidal Pulse Width Modulation (SPWM) principle is widely used in power electronic DC/AC converters (inverters) in energy conversion and motor control applications. The digital SPWM generation unit implementations have dominated over their counterparts based on analog circuits. In this paper, an FPGA-based SPWM generator is presented, which is capable to operate at switching frequencies up to 1 MHz (requiring FPGA operation at 100-160 MHz), thus it is capable to support the high switching frequency requirements of modern power electronic DC/AC converters. The successful operation of the proposed SPWM generator at high switching frequencies is demonstrated with post place-and-route simulation results for design verification and actual runs on hardware for design validation and proof-of-concept. The switching frequency of this system is an order of magnitude faster than previously proposed FPGA-implemented SPWM systems.

关键词： Switching frequency Generators field programmable gate arrays Inverters Pulse width modulation

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