检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

177 篇 会议

馆藏范围

177 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

75 篇 工学
- 70 篇 计算机科学与技术...
- 34 篇 电子科学与技术（可...
- 26 篇 软件工程
- 12 篇 电气工程
- 6 篇 信息与通信工程
- 6 篇 控制科学与工程
- 5 篇 动力工程及工程热...
- 3 篇 土木工程
- 3 篇 化学工程与技术
- 2 篇 机械工程
- 2 篇 仪器科学与技术
- 2 篇 建筑学
- 2 篇 生物医学工程（可授...
- 2 篇 安全科学与工程
- 1 篇 光学工程
- 1 篇 农业工程
- 1 篇 环境科学与工程（可...
- 1 篇 生物工程
23 篇 理学
- 16 篇 数学
- 4 篇 系统科学
- 3 篇 物理学
- 3 篇 化学
- 3 篇 统计学（可授理学、...
- 1 篇 生物学
11 篇 管理学
- 8 篇 管理科学与工程(可...
- 6 篇 工商管理
- 2 篇 图书情报与档案管...
5 篇 法学
- 5 篇 社会学
3 篇 经济学
- 3 篇 应用经济学
1 篇 农学
- 1 篇 作物学

主题

96 篇 field programmab...
66 篇 field programmab...
33 篇 hardware
20 篇 routing
15 篇 clocks
14 篇 table lookup
14 篇 registers
14 篇 logic gates
14 篇 delay
13 篇 computer archite...
12 篇 random access me...
11 篇 software
11 篇 system-on-a-chip
8 篇 wires
7 篇 memory managemen...
7 篇 throughput
7 篇 algorithm design...
7 篇 adders
6 篇 tiles
6 篇 arrays

机构

4 篇 department of el...
2 篇 system ip core r...
2 篇 department of co...
2 篇 department of el...
2 篇 innovation works...
2 篇 school of comput...
2 篇 ist tul
2 篇 xilinx inc. irel...
2 篇 school of comput...
2 篇 computer enginee...
2 篇 microprocessor a...
2 篇 electrical and e...
2 篇 school of microe...
2 篇 universidad de l...
2 篇 institute of tel...
2 篇 department of co...
2 篇 electrical and i...
2 篇 department of co...
2 篇 graduate school ...
2 篇 abm digital ug

作者

4 篇 dollas apostolos
3 篇 lei he
3 篇 zhe feng
3 篇 apostolos dollas
2 篇 wayne luk
2 篇 anderson jason h...
2 篇 hoang le
2 篇 manfred glesner
2 篇 harry sidiropoul...
2 篇 nelson brent
2 篇 siozios kostas
2 篇 jason h. anderso...
2 篇 luk wayne
2 篇 fearghal morgan
2 篇 dimitrios soudri...
2 篇 maruyama tsutomu
2 篇 krzysztof kepa
2 篇 pascal benoit
2 篇 benoit pascal
2 篇 kostas siozios

语言

177 篇 英文

检索条件"任意字段=21st International Conference on Field Programmable Logic and Applications, FPL 2011"

共 177 条记录，以下是141-150 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

A Coarse Grain Reconfigurable Processor Architecture for stream Processing Engine

A Coarse Grain Reconfigurable Processor Architecture for Str...

引用

international conference on field programmable logic and applications

作者： Takefumi Miyoshi Hideyuki Kawashima Yuta Terada Tsutomu Yoshinaga The University of Electro-Communications Tokyo Japan University of Tsukuba Tsukuba Ibaraki Japan

This paper proposes a processor architecture for DR-SPE, a dynamic reconfigurable stream processing engine. DR-SPE is special-purpose hardware for stream data processing, which achieves high processing performance by exploiting parallelism in the target query. It also handles query registration and execution order of operations at runtime. Available operations in DR-SPE are the same as those in streams on Wires. In this paper, DR-SPE is implemented on a FPGA XC6VLX240T-1, and its performance is evaluated. The results of the evaluation show that DR-SPE achieves register modification within 506 μsec when the configuration path is driven at 1 Mbps, which is not achieved by streams on Wires. DR-SPE also achieves flexibility and can support complicated queries by providing 10 × 10 operation units tiled onto an FPGA. DR-SPE achieves comparable operation throughput with streams on Wires at the expense of requiring more LUTs.

关键词： field programmable gate arrays Hardware Switches Hardware design languages Registers Radiation detectors Computer architecture

来源：评论

学校读者我要写书评

暂无评论

Memory Virtualization for Multithreaded Reconfigurable Hardware

Memory Virtualization for Multithreaded Reconfigurable Hardw...

引用

international conference on field programmable logic and applications

作者： Andreas Agne Marco Platzner Enno Lubbers Computer Engineering Group University of Paderborn Paderborn Germany Innovation Works EADS Deutschland GmbH Munich Germany

With the introduction of multithreaded programming for reconfigurable hardware, it is possible to map both sequential software and parallel hardware to a single CPU/FPGA platform using threads as a unifying development model. At the same time, platform FPGAs are a natural technology for implementing computationally intensive systems in the aerospace, automotive and industrial domains, as they combine high performance and flexibility with lower non-recurring engineering (NRE) costs when compared to low-volume ASIC solutions. The reusability and portability of hardware components in these safety-critical domains could be significantly improved by using multithreaded programming. However, the unique design considerations for memory virtualization, as required in safety-critical systems, are difficult to transfer directly from software to autonomous hardware threads. This paper presents a transparent and efficient way of augmenting current multithreaded and partially reconfigurable hardware runtime environments with dedicated, hardware-thread-aware memory address translation units to provide seamless memory translation for hardware threads. We show an analysis of the overheads, as well as an experimental evaluation of the latencies caused by address translation.

关键词： Hardware Instruction sets field programmable gate arrays Operating systems Programming Memory management

来源：评论

学校读者我要写书评

暂无评论

FPGA-Based Acceleration of Block Matching Motion Estimation Techniques

FPGA-Based Acceleration of Block Matching Motion Estimation ...

引用

international conference on field programmable logic and applications

作者： Diego Gonz´lez Guillermo Botella Soumak Mokheerje Uwe Meyer-Base Computer Architecture Department Complutense University of Madrid Madrid Spain Dept. Electrical and Computer Engineering Florida State University Tallahassee Florida USA

This paper focuses on the hardware acceleration of Block Matching motion estimation techniques (Search reduction family) suitable for the standard H.264/AVC MPEG-4 part 10 video compression. Many representative motion estimation search algorithms are explained here. As hardware, the well known Altera DE2 platform with a Cyclone II EP2C35F672C6 is used with a soft core NIOS II processor. C2H compiler which permits us to speed up the system at least two magnitude order is used to accelerate our source code. The paper shows the results in terms of performance and resources needed. This is the starting point to accelerate motion estimation algorithms using many strategies considering an ad-hoc motion estimation processor.

关键词： Acceleration Hardware Motion estimation field programmable gate arrays Throughput Transform coding Educational institutions

来源：评论

学校读者我要写书评

暂无评论

ERDB: An Embedded Routing Database for Reconfigurable Systems

ERDB: An Embedded Routing Database for Reconfigurable System...

引用

international conference on field programmable logic and applications

作者： Krzysztof Kepa Fearghal Morgan Peter Athanas Technology Center Nokia Siemens Networks Sp. z o. o. Wroclaw Poland Electrical & Electronic Engineering National University of Ireland Galway Ireland Configurable Computing Laboratory ECE Virginia Tech Blacksburg VA USA

This work presents an Embedded Routing Database (ERDB), which contains the complete description of the inter-tile routing shapes available in various Xilinx FPGA tiles, and the mapping of programmable Interconnection Point (PIP) bits within the FPGA configuration bit stream. ERDB provides the RC system with knowledge of its own architecture and facilitates RC systems in implementing autonomic (self-managing and adaptive) computing. ERDB also protects the integrity of the RC system and supports design Intellectual Property (IP) protection. The paper describes the automated generation of a size-optimised ERDB (3.7 MB memory footprint for the Virtex-5 LX50T device) and its application within the Secure Reconfiguration Controller (SeReCon), as a minimised FPGA fabric description for on-line verification of IP core's integrity during partial reconfiguration. Results demonstrate the feasibility and accuracy of the SeReCon/ERDB-based design (IP core) routing verification that, when applied to an example IP block, detects >;99% of the configured PIPs.

关键词： field programmable gate arrays Wires Tiles Routing Shape Databases IP networks

来源：评论

学校读者我要写书评

暂无评论

Latch-Based Performance Optimization for FPGAs

Latch-Based Performance Optimization for FPGAs

引用

international conference on field programmable logic and applications

作者： Bill Teng Jason H. Anderson Department of ECE University of Toronto Toronto ONT Canada

We explore using pulsed latches for timing optimization -- a first in the FPGA community. Pulsed latches are transparent latches driven by a clock with a non-standard (non-50%) duty cycle. We exploit existing functionality within commercial FPGA chips to implement latch-based optimizations that do not have the power or area drawbacks associated with other timing optimization approaches, such as clock skew and retiming. We propose an algorithm that iteratively replaces certain flip-flops in a logic design with latches for an improvement in circuit speed. Results show that much of the performance improvement achieved by using multiple skewed clocks can also be achieved using a single clock and latches. We also consider the impact of short delay paths (i.e. minimum delays), which can cause hold-time violations. Under conservative minimum delay assumptions, our latch-based optimization, operating on the routed design, provides a 5% performance improvement, on average, essentially for "free" (i.e. without any re-routing/delay padding). We show that short paths greatly hinder the ability of using latches for speed improvement, motivating further work to reduce their effects.

关键词： Clocks Latches Delay Optimization field programmable gate arrays Routing

来源：评论

学校读者我要写书评

暂无评论

VPFPAP: A Special-Purpose VLIW Processor for Variable-Precision Floating-Point Arithmetic

VPFPAP: A Special-Purpose VLIW Processor for Variable-Precis...

引用

international conference on field programmable logic and applications

作者： Yuanwu Lei Yong Dou Jie Zhou Sufeng Wang Department of Computer Science National University of Defense Technology Changsha China

Many scientific computing applications require efficient variable-precision floating-point arithmetic. This paper presents a special-purpose Variable-Precision Floating-Point Arithmetic Processor (VPFPAP) based on Very Large Instruction Word (VLIW) structure. The proposed processor uses a unified hardware structure, equipped with multiple custom basic variable-precision arithmetic units, to implement various variable-precision algebraic and transcendental functions. The performance is improved by the explicitly parallel technology of VLIW instruction and by dynamically varying the precision of intermediate computation. Finally, we create a prototype of VPFPAP unit into a Xilinx Virtex-6 XC6VLX760-2FF1760 FPGA chip. The experimental results show that our design, based on FPGA running at 253 MHz, outperforms the approach of a software-based library running on an Intel Core i3 530 CPU at 2.93 GHz by a factor of 5-38X for basic variable precision arithmetic operations and elementary functions.

关键词： VLIW Random access memory Polynomials Approximation methods Approximation algorithms Hardware field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

Pipelined Floating-Point Architecture for a Phase and Magnitude Detector Based on CORDIC

Pipelined Floating-Point Architecture for a Phase and Magnit...

引用

international conference on field programmable logic and applications

作者： Pongyupinpanich Surapong Manfred Glesner Microelectronic Systems Research Group Technische Universität Darmstadt Darmstadt Germany

To improve the computation precision of the beams control system in a heavy ion accelerator system, a floating-point phase and magnitude digital detector is proposed. The coordinate rotation digital computer (CORDIC) algorithm is utilized to compute results in digital form. Due to the hardware design simplicity, shifting and adding operations become two main operators to perform the computation. The proposed CORDIC core is based on floating-point arithmetic units to obtain high accuracy for the closed-loop control system. A Pipeline-based architecture is applied instead of CORIDC's iteration process in order to maximize computation performance. Moreover, comparison of hardware 8-and 16-stage pipeline-based simulations with Matlab/simulink is statically analysis to differentiate the accuracy of the two hardware architectures. Finally, resource efficiencies based on target Xilinx FPGA xc5vlx110 and 130-nm Silicon technology are shown that 8-and 16-stage hardwares consume maximum 18% and 38% of total slices at 134 MHz on the target FPGA, as well as 43,164 um and 83,769 um at 617 MHz on Silicon technology.

关键词： Pipeline processing Computer architecture field programmable gate arrays Silicon Hardware Control systems Detectors

来源：评论

学校读者我要写书评

暂无评论

Heracles: Fully Synthesizable Parameterized MIPS-Based Multicore System

Heracles: Fully Synthesizable Parameterized MIPS-Based Multi...

引用

international conference on field programmable logic and applications

作者： Michel A. Kinsy Michael Pellauer Srinivas Devadas Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology Cambridge MA USA

Heracles is an open-source complete multicore system written in Verilog. It is fully parameterized and can be reconfigured and synthesized into different topologies and sizes. Each processing node has a fully bypassed, 7-stage pipelined microprocessor running the MIPS-III ISA, a 4-stage input-buffer, virtual-channel router, and a local variable-size shared memory. Our design is highly modular with clear interfaces between the core, the memory hierarchy, and the on-chip network. In the baseline design, the microprocessor is attached to two caches, one instruction cache and one data cache, which are oblivious to the global memory organization. The memory system in Heracles can be configured as one single global shared memory (SM), or distributed shared memory (DSM), or any combination thereof. Each core is connected to the rest of the network of processors by a parameterized, realistic, wormhole router. We show different topology configurations of the system, and their synthesis results on the Xilinx Virtex-5 LX330T FPGA board. We also provide a small MIPS cross-compiler tool chain to assist in developing software for Heracles.

关键词： Routing Multicore processing Topology Random access memory field programmable gate arrays Network topology

来源：评论

学校读者我要写书评

暂无评论

Measuring and Reducing the Performance Gap between Embedded and Soft Multipliers on FPGAs

Measuring and Reducing the Performance Gap between Embedded ...

引用

international conference on field programmable logic and applications

作者： Hadi Parandeh-Afshar Paolo Ienne Communication and Computer Science Department Federal Institute of Technology Lausanne Switzerland

To bridge the gap between FPGAs and ASICs for arithmetic dominated circuits, one key step is to improve multipliers on FPGAs. This is a key feature that FPGA vendors have tried to improve in recent years by embedding ASIC like multipliers in the DSP blocks. However, due to the limited number of DSP blocks in an FPGA, their fixed location and bit-width limitation, efficient soft logic implementation of multipliers is fundamental. This is the reason that FPGA vendors have enhanced the logic blocks architecture to improve certain arithmetic circuits such as adder tree, which is the basic part of a parallel multiplier. This paper has two main contributions: (1) The performance gap between embedded and soft multipliers is measured and the design space is explored and (2) the current performance gap is reduced by employing a number of target specific mapping and arithmetic transformation techniques. For this purpose, a multiplier generator tool is developed and two conventional multiplication techniques are implemented in this tool. We compare our multipliers with the ones that are generated by Altera core generator tool considering a wide range of bit-widths. Therefore, this paper can be used as a reference for the digital circuit designers to choose the right way of implementing multipliers on FPGAs based on their design constraints.

关键词： field programmable gate arrays Adders Delay Digital signal processing Pipeline processing Table lookup Space exploration

来源：评论

学校读者我要写书评

暂无评论

Unifying Finite Difference Option-Pricing for Hardware Acceleration

Unifying Finite Difference Option-Pricing for Hardware Accel...

引用

international conference on field programmable logic and applications

作者： Qiwei Jin Wayne Luk David B. Thomas Department of Computing Imperial College London UK Department of Electrical and Electronic Engineering Imperial College London UK

Explicit finite difference method is widely used in finance for pricing many kinds of options. Its regular computational pattern makes it an ideal candidate for acceleration using reconfigurable hardware. However, because the corresponding hardware designs must be optimised both for the specific option and for the target platform, it is challenging and time consuming to develop designs efficiently and productively. This paper presents a unifying framework for describing and automatically implementing financial explicit finite difference procedures in reconfigurable hardware, allowing parallelised and pipelined implementations to be created from high-level mathematical expressions. The proposed framework is demonstrated using three option pricing problems. Our results show that an implementation from our framework targeting a Virtex-6 device at 310MHz is more than 24 times faster than a software implementation fully optimised by the Intel compiler on a four-core Xeron CPU at 2.66GHz. In addition, the latency of the FPGA solvers is up to 90 times lower than the corresponding software solvers.

关键词： Pricing field programmable gate arrays Pipeline processing Hardware Software Mathematical model Europe

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共18页 << < 9 10 11 12 13 14 15 16 17 18 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：