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Resource management for the heterogeneous arrays of hardware accelerators

Resource management for the heterogeneous arrays of hardware...

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21st international conference on field programmable logic and applications, fpl 2011

作者： Pohl, Zdenek Tichy, Milan Department of Signal Processing Institute of Information Theory and Automation 182 08 Prague Czech Republic

ISBN: (纸本)9780769545295

The resource management (RM) of heterogeneous hardware cores within the large-scale embedded systems have been one of the key implementation and research subjects in last years. In future systems, consisting of growing number of heterogeneous hardware cores, the RM have to be implemented to control the energy drain, exploit maximally the performance potential, and also to improve robustness of the system by bypassing failing components. We present the resource management providing an API for parallel execution of operations on a heterogeneous set of resources. The RM controls the tasks execution and monitors the performance. The information collected by the RM is used to optimize the execution. In this paper, we propose and present the SW implementation of the RM for the MicroBlaze soft-core processor running the Linux OS and accelerated by the heterogeneous array of hardware accelerators. © 2011 IEEE.

关键词： field programmable gate arrays (FPGA)

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Scalable arbiters and multiplexers for on-FGPA interconnection networks

Scalable arbiters and multiplexers for on-FGPA interconnecti...

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21st international conference on field programmable logic and applications, fpl 2011

作者： Dimitrakopoulos, Giorgos Kachris, Christoforos Kalligeros, Emmanouil Informatics and Communications Engineering University of West Macedonia Greece Greece Information and Comm. Systems Engineering University of the Aegean Greece

ISBN: (纸本)9780769545295

Soft on-FGPA interconnection networks are gaining increasing importance since they simplify the integration of heterogeneous components and offer, at the same time, a modular solution to the complex system-wide communication issues. The switches are the basic building blocks of such interconnection networks and their design critically affects the performance of the whole network. The way data traverse each switch is governed by the operation of the arbiter and the crossbar's multiplexers that need to be efficiently mapped on the FPGA fabric under tight area and delay constraints. This paper explores the design space of an arbiter and a multiplexer as a unified entity and proposes two new circuit alternatives that allow the design of scalable soft FPGA switches. © 2011 IEEE.

关键词： field programmable gate arrays (FPGA)

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Exploitation of parallel search space evaluation with FPGAs in combinatorial problems: The Eternity II case

Exploitation of parallel search space evaluation with FPGAs ...

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21st international conference on field programmable logic and applications, fpl 2011

作者： Malakonakis, Pavlos Dollas, Apostolos Dept. of Electronic and Computer Engineering Technical University of Crete Chania 73100 Greece

ISBN: (纸本)9780769545295

The Eternity II puzzle is a combinatorial search problem which qualifies as a computational grand challenge. As no known closed form solution exists, its solution is based on exhaustive search, making it an excellent candidate for FPGA-based architectures, in which complex data structures and non-trivial recursion are implemented in hardware. This paper presents such an architecture, which was designed and fully implemented on a Virtex5 FPGA (XUP ML505 board). Despite the serial nature of the recursion, as parallelism can be applied with the initiation of multiple searches, the system shows a measured speedup of 2.6 vs. a high-end multi-core compute server. © 2011 IEEE.

关键词： field programmable gate arrays (FPGA)

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A methodology and tool framework for supporting rapid exploration of memory hierarchies in FPGAS

A methodology and tool framework for supporting rapid explor...

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21st international conference on field programmable logic and applications, fpl 2011

作者： Sidiropoulos, Harry Siozios, Kostas Soudris, Dimitrios School of Electrical and Computer Engineering National Technical University Athens Greece

ISBN: (纸本)9780769545295

This paper introduces a novel methodology for enabling apid exploration of memory hierarchies onto FPGA devices. The methodology is software supported by a new open-source tool framework, named NAROUTO. Among others, the proposed framework enables critical tasks during architecture's design, such as memory hierarchy and floor-planning. Furthermore, NAROUTO framework is the only available solution for power/energy evaluation of different memory organizations. Experimental results shown that NAROUTO framework leads to significant area, power (about 82%) and performance (about 46%) improvements, as compared to existing solutions. © 2011 IEEE.

关键词： field programmable gate arrays (FPGA)

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Synthesizing tiled matrix decomposition on FPGAs

Synthesizing tiled matrix decomposition on FPGAs

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21st international conference on field programmable logic and applications, fpl 2011

作者： Tai, Yi-Gang Psarris, Kleanthis Dan Lo, Chia-Tien Department of Computer Science University of Texas at San Antonio San Antonio TX 78249 United States Computer Science and Software Engineering Southern Polytechnic State University Marietta GA 30060 United States

ISBN: (纸本)9780769545295

Hardware accelerators such as FPGAs and GPUs in heterogeneous systems are being increasingly important for many applications. For high performance computing, the flexibility and efficiency of FPGA makes it an attractive alternative to other approaches. However, for applications that have to decompose large matrices, not many scalable solutions can be found on FPGAs. In this paper, we propose a scalable QR matrix decomposer on FPGAs based on the latest advances in tiled matrix decomposition algorithms for high performance linear algebra. The proposed design can decompose a matrix of size limited only by off-chip memory and has the potential to achieve high performance. © 2011 IEEE.

关键词： field programmable gate arrays (FPGA)

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XDL-based module generators for rapid FPGA design implementation

XDL-based module generators for rapid FPGA design implementa...

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21st international conference on field programmable logic and applications, fpl 2011

作者： Ghosh, Subhrashankha Nelson, Brent Dept. of Electrical and Computer Engineering Brigham Young University Provo UT 84602 United States

ISBN: (纸本)9780769545295

XDLCoreGen is described, a module generator framework which directly generates placed and routed hard macros in XDL. XDLCoreGen is intended to be used in a rapid prototyping flow such as HMFlow, which achieves short FPGA implementation times by bypassing the conventional Xilinx tool flow and directly assembling designs from pre-built hard macros. The structure of XDLCoreGen is described and its unique cache-based router is highlighted as a key component to achieving extremely fast module generation times. Testing results are provided to demonstrate XDLCoreGen's ability to generate fully placed and routed hard macros in milliseconds. © 2011 IEEE.

关键词： field programmable gate arrays (FPGA)

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FPGA acceleration of the phylogenetic parsimony kernel?

FPGA acceleration of the phylogenetic parsimony kernel?

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21st international conference on field programmable logic and applications, fpl 2011

作者： Alachiotis, Nikolaos stamatakis, Alexandros Exelixis Lab. Scientific Computing Group Heidelberg Institute for Theoretical Studies Heidelberg Germany

ISBN: (纸本)9780769545295

The phylogenetic parsimony function is a popular, discrete criterion for reconstructing evolutionary trees based on molecular sequence data. Parsimony strives to find the phylogenetic tree that explains the evolutionary history of organisms by the least number of mutations. Because parsimony is a discrete function, it should fit well to FPGAs. We present a versatile FPGA implementation of the parsimony function and compare its performance to a highly optimized SSE3- and AVX-vectorized software *** find that, because of a particular constellation in our lab, the speedups that can be achieved by using an FPGA, are substantially less impressive, than usually reported in papers on FPGA acceleration of bioinformatics *** conclude that, a competitive spirit between SW and HW application developers can contribute toward obtaining more objective performance comparisons. © 2011 IEEE.

关键词： field programmable gate arrays (FPGA)

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Compact hardware architecture for Hummingbird cryptographic algorithm

Compact hardware architecture for Hummingbird cryptographic ...

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21st international conference on field programmable logic and applications, fpl 2011

作者： San, Ismail At, Nuray Anadolu University Electrical and Electronics Engineering Department Iki Eylül Kampüsü Eskişehir Turkey

ISBN: (纸本)9780769545295

Hummingbird is an ultra-lightweight cryptographic algorithm aiming at resource-constrained devices. In this paper, we present an enhanced hardware implementation of the Hummingbird cryptographic algorithm that is based on the memory blocks embedded within Spartan-3 FPGAs. The enhancement is not only from the introduction of the coprocessor approach but also from the employment of serialized data processing principles. Due to the compactness of the proposed architecture, remaining reconfigurable area in FPGAs can be used for other purposes. Comparisons to the other reported FPGA implementation of the Hummingbird cryptographic algorithm indicate that the proposed architecture outperforms the previous work in terms of both efficiency and area. We remark that our architecture can also be used as standalone although it is built via coprocessor approach. © 2011 IEEE.

关键词： field programmable gate arrays (FPGA)

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Compact CLEFIA implementation on FPGAS

Compact CLEFIA implementation on FPGAS

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21st international conference on field programmable logic and applications, fpl 2011

作者： Proença, Paulo Chaves, Ricardo Instituto Superior Técnico INESC-ID Rua Alves Redol 9 1000-029 Lisbon Portugal

ISBN: (纸本)9780769545295

In this paper two compact hardware structures for the, computation of the CLEFIA encryption algorithm are, presented. One structure based on the existing state of the art, and a novel structure with a more compact organization. This, paper shows that, with the use of the existing embedded, FPGA components and a careful scheduling, throughputs, above 1Gbit/s can be achieved with a resource usage as low, as 86 LUTs and 3 BRAMs on a VIRTEX 5 FPGA., Implementation results suggest that a LUT reduction up to, 67% can be achieved at a performance cost of 17% on a, VIRTEX 4 FPGA, resulting in Throughput/Slice efficiency, gains up to 2.5 times, when compared with the related state, of the art. © 2011 IEEE.

关键词： field programmable gate arrays (FPGA)

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An easily testable routing architecture and efficient test technique

An easily testable routing architecture and efficient test t...

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21st international conference on field programmable logic and applications, fpl 2011

作者： Inoue, Kazuki Yosho, Hiroki Amagasaki, Motoki Iida, Masahiro Sueyoshi, Toshinori Graduate School of Science and Technology Kumamoto University 2-39-1 Kurokami Kumamoto 860-8555 Japan

ISBN: (纸本)9780769545295

Generally, a programmable LSI such as an FPGA is difficult to test as compared to an ASIC. There are two major reasons for this. One is that automatic test pattern generator (ATPG) cannot be used because of the programmability of the FPGA. The other reason is that the FPGA architecture is very complex. In this paper, we propose a novel FPGA architecture that will simplify the testing of the device. The architecture is very simple and has several types of circuit blocks and orderly wire connections. This paper also presents efficient test configurations for our proposed architecture. We tested the interconnects of our architecture by using our configurations and achieved 100% test coverage for a short test time. © 2011 IEEE.

关键词： field programmable gate arrays (FPGA)

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