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检索条件"任意字段=21st International Conference on Field Programmable Logic and Applications, FPL 2011"

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Measuring and reducing the performance gap between embedded and soft multipliers on FPGAS

Measuring and reducing the performance gap between embedded ...

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21st international conference on field programmable logic and applications, fpl 2011

作者： Parandeh-Afshar, Hadi Ienne, Paolo Switzerland

ISBN: (纸本)9780769545295

To bridge the gap between FPGAs and ASICs for arithmetic dominated circuits, one key step is to improve multipliers on FPGAs. This is a key feature that FPGA vendors have tried to improve in recent years by embedding ASIC like multipliers in the DSP blocks. However, due to the limited number of DSP blocks in an FPGA, their fixed location and bit-width limitation, efficient soft logic implementation of multipliers is fundamental. This is the reason that FPGA vendors have enhanced the logic blocks architecture to improve certain arithmetic circuits such as adder tree, which is the basic part of a parallel multiplier. This paper has two main contributions: (1) The performance gap between embedded and soft multipliers is measured and the design space is explored and (2) the current performance gap is reduced by employing a number of target specific mapping and arithmetic transformation techniques. For this purpose, a multiplier generator tool is developed and two conventional multiplication techniques are implemented in this tool. We compare our multipliers with the ones that are generated by Altera core generator tool considering a wide range of bit-widths. Therefore, this paper can be used as a reference for the digital circuit designers to choose the right way of implementing multipliers on FPGAs based on their design constraints. © 2011 IEEE.

关键词： field programmable gate arrays (FPGA)

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Design of a high switching frequency FPGA-based SPWM generator for DC/AC inverters

Design of a high switching frequency FPGA-based SPWM generat...

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21st international conference on field programmable logic and applications, fpl 2011

作者： Lakka, Matina Koutroulis, Eftichios Dollas, Apostolos Department of Electronic and Computer Engineering Technical University of Crete GR-73100 Chania Greece

ISBN: (纸本)9780769545295

The Sinusoidal Pulse Width Modulation (SPWM) principle is widely used in power electronic DC/AC converters (inverters) in energy conversion and motor control applications. The digital SPWM generation unit implementations have dominated over their counterparts based on analog circuits. In this paper, an FPGA-based SPWM generator is presented, which is capable to operate at switching frequencies up to 1 MHz (requiring FPGA operation at 100-160MHz), thus it is capable to support the high switching frequency requirements of modern power electronic DC/AC converters. The successful operation of the proposed SPWM generator at high switching frequencies is demonstrated with post place-and-route simulation results for design verification and actual runs on hardware for design validation and proof-of-concept. The switching frequency of this system is an order of magnitude faster than previously proposed FPGA-implemented SPWM systems. © 2011 IEEE.

关键词： field programmable gate arrays (FPGA)

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A novel power reduction technique for block matching Motion Estimation hardware

A novel power reduction technique for block matching Motion ...

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21st international conference on field programmable logic and applications, fpl 2011

作者： Akin, Abdulkadir Ulusel, Onur Can Ozcan, Tevfik Zafer Sayilar, Gokhan Hamzaoglu, Ilker Faculty of Engineering and Natural Sciences Sabanci University Orhanli Tuzla 34956 Istanbul Turkey

ISBN: (纸本)9780769545295

Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. Therefore, in this paper, we propose comparison prediction (CP) technique for reducing the power consumption of block matching (BM) ME hardware. CP technique reduces the power consumption of absolute difference operations performed by BM ME hardware. CP technique can easily be used in all BM ME hardware. In this paper, we applied it to a 256 processing element fixed block size ME hardware implementing full search algorithm. It reduced the average dynamic power consumption of this ME hardware by 2.2% with no Peak Signal-to-Noise Ratio (PSNR) loss and by 9.3% with 0.04% PSNR loss on a XC2VP30-7 FPGA. © 2011 IEEE.

关键词： field programmable gate arrays (FPGA)

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Remote FPGA Lab with interactive control and visualisation interface

Remote FPGA Lab with interactive control and visualisation i...

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21st international conference on field programmable logic and applications, fpl 2011

作者： Morgan, Fearghal Cawley, Seamus Callaly, Frank Agnew, Shane Rocke, Patrick O'Halloran, Martin Drozd, Nina Kȩpa, Krzysztof Mc Ginley, Brian Electrical and Electronic Engineering National University of Ireland Galway Ireland

ISBN: (纸本)9780769545295

This paper describes a scalable and extendable Remote field programmable Gate Array Laboratory (RemoteFPGA) which can be used to enhance the learning of digital systems and FPGA applications. The web-based console provides an always-on, real-time, interactive control and visualisation interface to/from a bank of remote FPGAs. A Xilinx ISE project template enables integration of user HDL-based designs to execute on the RemoteFPGA. Host-FPGA communication is supported using a register-based interface. Users can create real-time, interactive and visual demonstrators of digital systems components. The paper presents a demonstrator for a Finite state Machine (FSM) application, and illustrates the use of web-based control and visualisation for enhanced learning of FSM behaviour. The paper also presents a case study of the use of RemoteFPGA in undergraduate teaching. © 2011 IEEE.

关键词： field programmable gate arrays (FPGA)

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Speculative debug insertion for FPGAs

Speculative debug insertion for FPGAs

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21st international conference on field programmable logic and applications, fpl 2011

作者： Hung, Eddie Wilton, steven J.E. Department of Electrical and Computer Engineering University of British Columbia Vancouver BC Canada

ISBN: (纸本)9780769545295

FPGA prototypes have become an increasingly important part of the overall integrated circuit design and verification flow, providing the ability to test an integrated circuit running at (near) speed with realistic inputs and outputs. When unexpected behaviour is observed in the prototype, it is necessary to determine the source of this behaviour;this usually requires observing signals that are internal to one of the devices in the prototype. Tools currently exist to enable FPGAs to be instrumented, but these are normally used in a reactive manner;that is, instrumentation is only added after incorrect behaviour has been observed. In this paper, we propose speculative debug insertion, in which a tool automatically predicts what signals will be useful during debug, and instruments the design during the first compilation. If done correctly, this can significantly accelerate the debug process, especially for large prototypes containing many FPGAs. However, it is important that this does not negatively affect the performance, capacity, power, or compilation time. We show that speculative debug insertion is possible, and experimentally evaluate the limits to speculative insertion. © 2011 IEEE.

关键词： field programmable gate arrays (FPGA)

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Improving security of SDDL designs through interleaved placement on Xilinx FPGAs

Improving security of SDDL designs through interleaved place...

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21st international conference on field programmable logic and applications, fpl 2011

作者： Velegalati, Rajesh Kaps, Jens-Peter ECE Department George Mason University Fairfax VA United States

ISBN: (纸本)9780769545295

Implementations of mathematically secure cryptographic, algorithms leak information through side channels, during run time. Differential Power Analysis (DPA) attacks, exploit power leakage to obtain the secret information., Dynamic and Differential logic (DDL), one of the popular, countermeasures against DPA attacks, tries to achieve constant, power consumption thereby decorrelating the leakage, with the data being processed. Separated Dynamic and, Differential logic (SDDL), a variant of DDL, achieves this, goal by duplicating the original design into Direct and Complementary, parts which exhibit constant switching activity, per clock cycle and have balanced net delays. Traditionally, on field programmable Gate Arrays (FPGAs) both parts are, placed side-by-side to ensure symmetrical routing. However, due to process variations both parts will have slightly, different delays. This limits the effectiveness of SDDL., In this paper we introduce a design flow to achieve, interleaved placement of SDDL designs on Xilinx Spartan-, 3E FPGAs while preserving symmetric routing. We explore, several placement configurations with respect to routing and, security. The results of our experiments show that a well-balanced, placement of SDDL can double the effectiveness of, the SDDL countermeasures on FPGAs. © 2011 IEEE.

关键词： field programmable gate arrays (FPGA)

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An optimized FPGA implementation of the modified space vector modulation algorithm for AC drives control

An optimized FPGA implementation of the modified space vecto...

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21st international conference on field programmable logic and applications, fpl 2011

作者： Alecsa, Bogdan Onea, Alexandru Automatic Control and Applied Informatics Department Gheorghe Asachi Technical University Iasi Romania

ISBN: (纸本)9780769545295

This paper presents an optimized FPGA implementation of the 5 step modified space vector modulation algorithm. The algorithm is modeled in Matlab Simulink using System Generator software from Xilinx. After validation through simulation, the algorithm is translated into a synchronous hardware automaton and then implemented in a low cost Spartan-3E FPGA device. Design performance in terms of occupied area and achieved speed is presented and compared to other existing implementations. The algorithm is used in AC drives control, and is especially useful due to minimized switching losses and short execution time. Also, its feature of using only one of the zero space vectors proves advantageous when using a low cost current measurement scheme based on voltage drop over low side shunt resistors. Experimental results verify the correct system functioning and validate the design method. © 2011 IEEE.

关键词： field programmable gate arrays (FPGA)

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An implementation of the mean shift filter on FPGA

An implementation of the mean shift filter on FPGA

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21st international conference on field programmable logic and applications, fpl 2011

作者： Trieu, Dang Ba Khac Maruyama, Tsutomu Systems and Information Engineering University of Tsukuba 1-1-1 Ten-ou-dai Tsukuba Ibaraki 305-8573 Japan

ISBN: (纸本)9780769545295

Mean shift algorithm is a procedure which is often used for color image segmentation. Its computational cost, however, is very high, and many techniques for reducing the cost have been researched. This paper describes an approach for real time processing of a mean shift algorithm using an FPGA. In our approach, the image is scanned from top to bottom (or bottom to top), and L lines around the target line are buffered on the FPGA, and the pixels on the target line can be processed efficiently using the buffered pixels. When the pixels are shifted out of the L lines, they are put in queues, and processed afterward. In our circuit, the processing of several pixels is interleaved to hide the delay caused by the long feedback in the mean shift filter. A technique to reduce the number of on-chip memory banks used for storing the L lines is also introduced. The performances of our circuit for 768×512 pixel images is 50 to 130 fps according to the size of the mean shift filter. © 2011 IEEE.

关键词： field programmable gate arrays (FPGA)

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Scalable FRM-SSA SoC design for the simulation of networks with thousands of biochemical reactions in real time

Scalable FRM-SSA SoC design for the simulation of networks w...

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21st international conference on field programmable logic and applications, fpl 2011

作者： Hazapis, Orsalia Georgia Manolakos, Elias S. Department of Informatics and Telecommunications University of Athens Greece Greece

ISBN: (纸本)9780769545295

Simulation of biomolecular networks with thousands of reactions is becoming essential for systems biology. We are presenting the design of a scalable System on Chip parallel architecture that implements Gillespie's First Reaction Method in reconfigurable FPGA hardware. Our SoC architecture can deliver performance (Mega-Reactions/sec) and throughput (MReaction cycles/sec) that is increasing linearly with the number of processors when simulating large biomolecular networks with up to m = 4096 reactions using a moderate size FPGA. We have synthesized and verified various SoC instances with up to N=8 Processing Elements for Xilinx Virtex 5 and Altera Cyclone III FPGAs, reaching clock frequencies up to 180 MHz and delivering simulation performance that is more than 2 order of magnitude higher than that of Intel Core 2 and i7 CPUs running at frequencies above 2GHz. © 2011 IEEE.

关键词： field programmable gate arrays (FPGA)

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Novel and highly efficient reconfigurable implementation of data mining classification tree

Novel and highly efficient reconfigurable implementation of ...

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21st international conference on field programmable logic and applications, fpl 2011

作者： Chrysos, Grigorios Dagritzikos, Panagiotis Papaefstathiou, Ioannis Dollas, Apostolos Microprocessor and Hardware Laboratory Department of Electronic and Computer Engineering Technical University of Crete Chania Greece

ISBN: (纸本)9780769545295

The available e-data throughout the Web are growing at such a high rate that data mining on the web is considered the biggest challenge of information technology. As a result it is crucial to find new and innovative ways for classifying and mining those huge amounts of data. In this paper we present an implementation of a state-of-the-art data mining algorithm on a modern FPGA. This is one of the first approaches utilizing the resources of an FPGA to accelerate certain very CPU intensive data-mining/data-classification schemes and our real-world results from actual runs on hardware demonstrate that it is a highly promising one. In particular, our FPGA-based system achieves, depending on the data classified, a speedup from 4x and up to 50x (on average 25x) when compared with a state-of-theart multi-core CPU, including I/O overhead. © 2011 IEEE.

关键词： field programmable gate arrays (FPGA)

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