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Proceedings: 21st international conference on Computer Design

Proceedings: 21st International Conference on Computer Desig...

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Proceedings: 21st international conference on Computer Design ICCD 2003

The proceedings contains 91 papers. Topics discussed include energy efficiency, timing verification, electrical analysis for system LSI, power optimization, gene chip design, system level design, system performance, micro processor test and diagnosis, physical design, performance optimization, clock and signal distribution, performance and power driven physical design, instruction execution, test compression technology, physical design for regular fabrics and field programmable gate arrays, array design optimization, test compaction, techniques for synthesizing into fabrics, hardware partitioning, energy aware design and applications, high speed design issues and test challenges, efficiency and reliability, novel methods in logic synthesis, communication and context management and board test and power aware test.

关键词： Integrated circuit layout

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A Routing Architecture for Mapping Dataflow Graphs at Run-Time

A Routing Architecture for Mapping Dataflow Graphs at Run-Ti...

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international conference on field programmable logic and applications

作者： Dirk Koch Jim Torresen Department of Informatics University of Oslo Norway

While it is feasible with today's commercial tools to swap from one module to another, many applications demand more advanced configuration schemes, for example, to map different dataflow graphs onto an FPGA. To support this, we will improve an existing on-FPGA communication architecture in order to carry out arbitrary routing among multiple freely placed modules. This results in a circuit switching network that will be efficiently implemented directly within the FPGA routing fabric.

关键词： Routing field programmable gate arrays Multiplexing Wires Switches Fabrics Table lookup

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Failure Probability and Fault Observability of SRAM-FPGA Systems

Failure Probability and Fault Observability of SRAM-FPGA Sys...

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international conference on field programmable logic and applications

作者： Cinzia Bernardeschi Luca Cassano Andrea Domenici Department of Information Engineering University of Pisa Italy

We describe a simulation-based fault injection technique for failure probability and fault observability assessment of SRAM-FPGA systems. Our approach relies on a model of FPGA netlists realised with the stochastic Activity Networks formalism. Faults can be injected into the model either stochastically or exhaustively one at a time. Fault propagation is traced to the output pins, using a four-valued logic that enables faulty signals to be tagged and recognized. We considered some of the ITC'99 benchmarks as examples.

关键词： field programmable gate arrays Observability Circuit faults logic gates Table lookup Clocks storage area networks

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Time Domain Analysis for High Frequency applications in the field of EMC Compliance Measurements: Novel Method to Trace Transient RF Disturbances

Time Domain Analysis for High Frequency Applications in the ...

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21st international conference on Radioelektronika

作者： Winter, Wolfgang Wood, Zuzana Emv GmbH Wallbergstr 7 D-82024 Taufkirchen Germany

ISBN: (纸本)9781612843223

Time Domain Measurements have been used for several years in frequency applications below 1 GHz and very suitable to measure transient and time limited disturbing RF signals. The new generation of High speed field programmable Gate Arrays (FPGA) in combination with analogue digital converters and RF down converters enable measurements with high precision. The achievable measurement accuracy is directly comparable to high end RF test receivers with the conventional super heterodyne design. The achieved measurement accuracy could be used to design CISP 16-1-1 compliant digital RF receivers. The additional technical features like real time spectrum and high speed Quasi Peak detector measurements open new analysis methods to understand RF disturbances. Typical examples of complex RF signals which have to be measured under CISPR standards are all automotive electronic modules which are controlling the internal communication bus system, internal RF devices (automotive WLAN, UMTS, GSM, WCDMA, MIMO, multiband smart phones, Net-books) and all on board regenerative energy systems using high power switching devices like Insulated Gate Bipolar Transistors (IGBT), or inverters.

关键词： RF receiver Time Domain Analysis EMC

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A Novel FPGA Architecture of Commentz-Walter Algorithm using Bit-Split string-Matching Engines 21

A Novel FPGA Architecture of Commentz-Walter Algorithm using...

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21st international conference on Advances in ICT for Emerging Regions, ICter 2021

作者： Vidanagamachchi, Sugandima M. Dewasurendra, Shirley D. University of Ruhuna Faculty of Science Department of Computer Science Sri Lanka University of Peradeniya Faculty of Engineering Department of Computer Engineering Sri Lanka

ISBN: (纸本)9781665466837

This paper describes a reconfigurable hardware implementation of CommentzWalter algorithm with bit-split string matching engines to match multiple protein sequences. It is reported that multiple pattern matching using the most widely used Aho-Corasick algorithm for different applications has been carried out on graphics processing units and field programmable gate arrays to accelerate the matching process. Commentz-Walter algorithm, is a multiple pattern matching algorithm and more complex than Aho-Corasick. There are no reports of it being directly implemented in any hardware platform except as software implementations on general purpose processors. In this work, a specific architecture for our target application using CommentzWalter algorithm has been developed and tested with a simulator for hardware description languages. This architecture can match multiple patterns of proteins efficiently when implemented on a field programmable Gate Array. Finally, we compare a previously developed hardware architecture of bit-split Aho-Corasick with our bit-split Commentz-Walter architecture. Using the Intel stratix IV GX EP4SGX230KF40C2 FPGA chip as the target device, the compilation results with Quartus II show that the synthesis logic utilization is 5% with 2203 total number of registers, 64896 FPGA block memory bits and 4 DSP block 18-bit elements. The simulation and practical experimental results show that the proposed architecture can effectively improve the performance of the Commentz-Walter algorithm. © 2021 IEEE.

关键词： field programmable gate arrays (FPGA)

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An FPGA Based Architecture for Concurrent System Design Applied to Human-robot Interaction applications 21

An FPGA Based Architecture for Concurrent System Design Appl...

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21st ISPE Inc international conference on Concurrent Engineering

作者： Zhang, Lin Slaets, Peter Bruyninckx, Herman Katholieke Univ Leuven Dept Mech Engn B-3000 Leuven Belgium Int Univ Coll Grp T B-3000 Leuven Belgium

ISBN: (纸本)9781614994404;9781614994398

This paper presents a hardware and software architecture for vision-based human-robot interaction designed for field programmable gate array (FPGA) based embedded system. The configurable logic and memory blocks connected through programmable interconnects on the FPGA permit programmers to create complex systems running multiple processing cores in parallel, which motivated the authors to implement vision algorithms and robot controllers on a single system-on-chip (SoC) board, aiming at low cost, low power consumption and high performance in human-robot interaction for industrial and educational robots. The architecture is a product derived from a component based programming model together with a systematic methodology for concurrent system design proposed by the authors.

关键词： field programmable gate array embedded system concurrent system design vision based robot control software and hardware architecture

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Optimizing an Open-Source Processor for FPGAs: A Case study

Optimizing an Open-Source Processor for FPGAs: A Case Study

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international conference on field programmable logic and applications

作者： Lyonel Barthe Luis Vitorio Cargnini Pascal Benoit Lionel Torres LIRMM UMR 5506 CNRS University of Montpellier Montpellier France

Optimizing a processor for FPGA architectures is a challenging task. In this paper, we attempt to bridge the performance gap between commercial and open-source processors by introducing various design and implementation strategies at the register transfer abstraction level, where most optimizations require several design trade-offs to ensure an efficient and proper use of available resources. Using an open-source processor as a case study, we demonstrate the effectiveness of the proposed methods through a set of synthesis and benchmark results.

关键词： field programmable gate arrays Registers Hazards Pipelines Optimization Benchmark testing Computer architecture

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Automated Resource-Aware Floorplanning of Reconfigurable Areas in Partially-Reconfigurable FPGA Systems

Automated Resource-Aware Floorplanning of Reconfigurable Are...

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international conference on field programmable logic and applications

作者： Cristiana Bolchini Antonio Miele Chiara Sandionigi Dipartimento di Elettronica e Informazione Politecnico di Milano Milan Italy

The floor planning activity is a key step in the design of systems on FPGAs, but the approaches available today rarely consider both the constraints imposed by the heterogeneous distribution of the resources in the devices and the reconfiguration capabilities. In fact, current-generation FPGAs present a complex architecture, but also offer more sophisticated reconfiguration features. The proposed floor planner, based on an accurate model of the devices, takes into account all these elements and finds an optimal solution, suitable for reconfigurable designs.

关键词： field programmable gate arrays Digital signal processing Shape Pins Wires Performance evaluation Fabrics

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Leros: A Tiny Microcontroller for FPGAs

Leros: A Tiny Microcontroller for FPGAs

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international conference on field programmable logic and applications

作者： Martin Schoeberl Department of Informatics and Mathematical Modeling Technical University of Denmark Denmark

Leros is a tiny microcontroller that is optimized for current low-cost FPGAs. Leros is designed with a balanced logic to on-chip memory relation. The design goal is a microcontroller that can be clocked in about half of the speed a pipelined on-chip memory and consuming less than 300 logic cells. The architecture, which follows from the design goals, is a pipelined 16-bit accumulator processor. An implementation of Leros needs at least one on-chip memory block and a few hundred logic cells. The application areas of Leros are twofold: First, it can be used as an intelligent peripheral device for auxiliary functions in an FPGA based system-on-chip design. Second, the very small size of Leros makes it an attractive soft core for many-core research with low-cost FPGAs.

关键词： System-on-a-chip field programmable gate arrays Clocks Registers Pipelines Delta modulation Microcontrollers

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FPGA design and implementation for vertex extraction of polygonal shapes

FPGA design and implementation for vertex extraction of poly...

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21st international conference on Electronics Communications and Computers, CONIELECOMP 2011

作者： Martinez-Carballido, Jorge Guevara-Escobedo, Jorge Ramirez-Cortes, Juan M. Alejos-Palomares, Ruben Instituto Nacional de Astrofísica Óptica Y Electrónica Mexico Mexico Universidad de Las Américas Puebla Mexico Mexico

ISBN: (纸本)9781424495573

This work focuses on developing systems of blocks in SIMULINK and VHDL to reuse on design of applications involving the recognition of polygonal objects. Usage of this work reduces time in the development of prototype solutions using FPGAs. The vertex extraction algorithm uses contour's corners as the candidate set to select vertices by using local properties. SIMULINK and VHDL implementations were tested to be equal at I/O level. Using a Spartan 3E FPGA starter kit for the hardware implementation probed that the VHDL implementation synthesizes. Binary images are loaded into the FPGA through a microSD memory card and the resulting data from the FPGA process is visualized through the starter Kit built-in alphanumeric LCD. Test cases consider artificial cases to ensure wide case testing for case combination of the algorithm. These sets of components in software and hardware contribute by easing implementations on computer vision applications using polygons for object identification. © 2011 IEEE.

关键词： field programmable gate arrays (FPGA)

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