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A New Process Characterization Method for FPGAs Based on Electromagnetic Analysis

A New Process Characterization Method for FPGAs Based on Ele...

引用

international conference on field programmable logic and applications

作者： Florent Bruguier Pascal Benoit Philippe Maurine Lionel Torres LIRMM CNRS University of Montpellier 2 Montpellier France

Thanks to their inherent regularity and reconfigurability, FPGAs offer an ideal structure to manage process variability. Recent works from the literature have addressed the process characterization problem for FPGAs: proposed approaches rely on process sensors (ring oscillators) and a measurement subsystem implemented into the configurable logic blocks. In this article, we propose for the first time in the literature a non-invasive characterization method based on electromagnetic analysis. The whole experimental set-up is described and the characterization accuracy is discussed. This paper proves the feasibility of this new method on FPGAs.

关键词： field programmable gate arrays Temperature measurement Frequency measurement Ring oscillators Sensor phenomena and characterization Voltage measurement

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Implementing stream-Processing applications on FPGAs: A DSL-Based Approach

Implementing Stream-Processing Applications on FPGAs: A DSL-...

引用

international conference on field programmable logic and applications

作者： Jocelyn Serot Francois Berry Sameer Ahmed LASMEA Universite Blaise Pascal / CNRS Clermont-Ferrand France

We introduce CAPH, a new domain-specific language (DSL) suited to the implementation of stream-processing applications on field programmable gate arrays (FPGA). CAPH relies upon the actor/dataflow model of computation. applications are described as networks of purely dataflow actors exchanging tokens through unidirectional channels. The behavior of each actor is defined as a set of transition rules using pattern matching. The CAPH suite of tools currently comprises a reference interpreter and a compiler producing both SystemC and synthetizable VHDL code. We describe the implementation, with a preliminary version of the compiler, of a simple real-time motion detection application on a FPGA-based smart camera platform. The language reference manual and a prototype compiler are available from http://***/Personnel/***/***.

关键词： field programmable gate arrays Programming streaming media Hardware Hardware design languages Computational modeling Real time systems

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An FPGA Solver for SAT-Encoded Formal Verification Problems

An FPGA Solver for SAT-Encoded Formal Verification Problems

引用

international conference on field programmable logic and applications

作者： Kenji Kanazawa Tsutomu Maruyama Systems and Information Engineering University of Tsukuba Ibaraki Japan

Formal verification is one of the most important applications of the satisfiability (SAT) problem. WSAT and its variants are one of the best performing stochastic local search algorithms. In this paper, we propose an FPGA solver for SAT-encoded verification problems based on a WSAT algorithm. The size of the verification problems is very large, and most of the data used in the algorithm have to be placed in off-chip DRAMs. The performance of the solver is limited by the throughput and access delay of the DRAMs, not by the parallelism in FPGA. We show how much speed-up is possible under this situation using the memory throughput, memory access delay and the operational frequency of FPGA as parameters.

关键词： Random access memory field programmable gate arrays logic gates Delay Parallel processing Throughput System-on-a-chip

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A Methodology and Tool Framework for Supporting Rapid Exploration of Memory Hierarchies in FPGAs

A Methodology and Tool Framework for Supporting Rapid Explor...

引用

international conference on field programmable logic and applications

作者： Harry Sidiropoulos Kostas Siozios Dimitrios Soudris School of Electrical & Computer Engineering National Technical University of Athens Greece

This paper introduces a novel methodology for enabling rapid exploration of memory hierarchies onto FPGA devices. The methodology is software supported by a new open-source tool framework, named NAROUTO. Among others, the proposed framework enables critical tasks during architecture's design, such as memory hierarchy and floor-planning. Furthermore, NAROUTO framework is the only available solution for power/energy evaluation of different memory organizations. Experimental results shown that NAROUTO framework leads to significant area, power (about 82%) and performance (about 46%) improvements, as compared to existing solutions.

关键词： field programmable gate arrays IP networks Pins Estimation Routing Multiplexing Delay

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Improving FPGA Reliability with Wear-Levelling

Improving FPGA Reliability with Wear-Levelling

引用

international conference on field programmable logic and applications

作者： Edward stott Peter Y. K. Cheung Department of Electrical and Electronic Engineering Imperial College London London UK

As VLSI circuits achieve smaller geometries, reliability is becoming an growing problem. The flexibility of FPGAs enables novel techniques for meeting this challenge, and one such technique is wear-levelling: periodic reconfiguration to eliminate electrical stress hotspots. In this work we have have carried out accelerated-life experiments in FPGAs to assess the feasibility of three wear-levelling strategies for reducing timing degradation. All three techniques resulted in significant improvements to robustness compared with a static configuration, and we have demonstrated that wear-levelling is a promising tool for improving FPGA reliability.

关键词： Degradation field programmable gate arrays Table lookup stress Delay Adders

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Compact CLEFIA Implementation on FPGAS

Compact CLEFIA Implementation on FPGAS

引用

international conference on field programmable logic and applications

作者： Paulo Proenca Ricardo Chaves Instituto Superior Técnico / INESC-ID Lisbon Portugal

In this paper two compact hardware structures for the computation of the CLEFIA encryption algorithm are presented. One structure based on the existing state of the art and a novel structure with a more compact organization. This paper shows that, with the use of the existing embedded FPGA components and a careful scheduling, throughputs above 1Gbit/s can be achieved with a resource usage as low as 86 LUTs and 3 BRAMs on a VIRTEX 5 FPGA. Implementation results suggest that a LUT reduction up to 67% can be achieved at a performance cost of 17% on a VIRTEX 4 FPGA, resulting in Throughput/Slice efficiency gains up to 2.5 times, when compared with the related state of the art.

关键词： field programmable gate arrays Throughput Hardware Table lookup Processor scheduling Pipelines Encryption

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20Gbps C-Based Complex Event Processing

20Gbps C-Based Complex Event Processing

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international conference on field programmable logic and applications

作者： Hiroaki Inoue Takashi Takenaka Masato Motomura System IP Core Research Laboratories NEC Corporation Kawasaki Japan Graduate School of Information Science and Technology Hokkaido University Sapporo Japan

This paper presents the world's fastest complex event processing system, designed to process a large number of events on FPGAs. Unlike conventional SQL-based approaches, our approach features logic automation constructed with a new C-based event language that supports regular expressions on the basis of C functions, so that a wide variety of event-processing applications can be efficiently mapped to FPGAs. Evaluations on an FPGA-based NIC show that we have achieved 20Gbps event processing performance in a financial trading application with only a small logic increase, 2.7%.

关键词： Smoothing methods Real time systems field programmable gate arrays Data mining Hardware Software Algorithm design and analysis

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XDL-Based Module Generators for Rapid FPGA Design Implementation

XDL-Based Module Generators for Rapid FPGA Design Implementa...

引用

international conference on field programmable logic and applications

作者： Subhrashankha Ghosh Brent Nelson NSF Center for High-Performance Reconfigurable Computing (CHREC) Department of Electrical and Computer Engineering Brigham Young University Provo UT USA

XDLCoreGen is described, a module generator framework which directly generates placed and routed hard macros in XDL. XDLCoreGen is intended to be used in a rapid prototyping flow such as HM Flow, which achieves short FPGA implementation times by bypassing the conventional Xilinx tool flow and directly assembling designs from pre-built hard macros. The structure of XDLCoreGen is described and its unique cache-based router is highlighted as a key component to achieving extremely fast module generation times. Testing results are provided to demonstrate XDLCoreGen's ability to generate fully placed and routed hard macros in milliseconds.

关键词： field programmable gate arrays Generators Switches Adders Wires logic gates Tiles

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Exploring Gabor Filter Implementations for Visual Cortex Modeling on FPGA

Exploring Gabor Filter Implementations for Visual Cortex Mod...

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international conference on field programmable logic and applications

作者： Yong Cheol Peter Cho Sungmin Bae Yongseok Jin Kevin M. Irick Vijaykrishnan Narayanan Department of Computer Science and Engineering Pennsylvania State University University Park PA USA

Gabor filters are widely used to model the behavior of the V1 stage of the primary visual cortex of mammalian vision systems. Acceleration of this filter is critical for various real-time vision applications. In this work, we explore a variety of design options for the Gabor filter to tradeoff resource utilization, performance and accuracy. Our results indicate that our optimizations enable a variety of design options to meet a wide range of application constraints.

关键词： Convolution Kernel Digital signal processing Gabor filters Interpolation field programmable gate arrays Computer architecture

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A Model for Matrix Multiplication Performance on FPGAs

A Model for Matrix Multiplication Performance on FPGAs

引用

international conference on field programmable logic and applications

作者： Colin Yu Lin Hayden Kwok-Hay So Philip H.W. Leong Electrical and Electronic Engineering University of Hong Kong Hong Kong China Electrical and Information Engineering University of Sydney Sydney Australia

Computations involving matrices form the kernel of a large spectrum of computationally demanding applications for which FPGAs have been utilized as accelerators. Their performance is related to their underlying architectural and system parameters such as computational resources, memory and I/O bandwidth. A simple analytic model that gives an estimate of the performance of FPGA-based sparse matrix-vector and matrix-matrix multiplication is presented, dense matrix multiplication being a special case. The efficiency of existing implementations are compared to the model and performance trends for future technologies examined.

关键词： Sparse matrices field programmable gate arrays Bandwidth System-on-a-chip Computational modeling Matrix decomposition Schedules

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