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检索条件"任意字段=21st International Symposium on Computer Architecture and High Performance Computing"

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Warped-Compaction: Maximizing GPU Register File Bandwidth Utilization via Operand Compaction 31

Warped-Compaction: Maximizing GPU Register File Bandwidth Ut...

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31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Jeong, Eunbi Jeong, Ipoom Yoon, Myung Kuk Kim, Nam Sung Ewha Womans University Department of Computer Science and Engineering Seoul Korea Republic of Yonsei University Department of System Semiconductor Engineering Seoul Korea Republic of Yonsei University Department of Electrical and Electronic Engineering Seoul Korea Republic of University of Illinois Urbana-Champaign Urbana United States

ISBN: (纸本)9798331506476

The GPU has been successfully used for diverse emerging compute-intensive applications, including imaging, computer vision, and more recently, deep learning, to name a few. To offer high performance for such applications, it is provisioned with massive Register Files (RFs) to exploit high Thread-Level Parallelism (TLP). As RFs are designed to store thousands of contexts and provide very high bandwidth for uninterrupted supply of operands to hundreds of compute units for high TLP, they have become one of the most power-hungry components in the GPU. Meanwhile, faced with the end of Dennard scaling, it is more important than ever to innovate the microarchitecture of (power-constrained) GPUs to continuously improve the performance of future compute-intensive *** this work, we propose a GPU microarchitecture, WarpedCompaction, designed to utilize given RFs more efficiently, instead of relying on larger-capacity and/or higher-bandwidth RFs to further improve GPU performance. Specifically, first, we reverse-engineer the latest GPU's RF organization through microbenchmarking. This uncovers that each sub-core within a streaming multiprocessor contains only two dual-ported RF banks, and accesses to these banks are arbitrated solely based on register IDs. We also reveal that, despite the modest configurations, RF banks are largely underutilized, staying inactive for 33.5% of the time. Second, we observe that previously proposed RF optimization techniques, data forwarding and dead register elimination, cannot address this underutilization problem. This is mainly due to the (R1) insufficient RF access requests from a limited number of Operand Collector Units (OCUs) and (R2) inefficient operand distribution by the conventional RF bank arbitration. Third, we present two architectural solutions to tackle the observed inefficiency: (S1) OCU sharing and (S2) skewed arbitrator. Building on enhanced OCU early allocation for partially ready instructions and operand forwardin

关键词： Compaction

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Estimating the Impact of Communication Schemes for Distributed Graph Processing 21

Estimating the Impact of Communication Schemes for Distribut...

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21st IEEE international symposium on Parallel and Distributed computing (ISPDC)

作者： Ye, Tian Kuppannagari, Sanmukh R. De Rose, Cesar A. F. Wijeratne, Sasindu Kannan, Rajgopal Prasanna, Viktor K. Univ Southern Calif Dept Comp Sci Los Angeles CA 90007 USA Pontificia Univ Catolica Rio Grande do Sul Sch Technol Porto Alegre Brazil

ISBN: (数字)9781665488020

ISBN: (纸本)9781665488020

Extreme scale graph analytics is imperative for several real-world Big Data applications with the underlying graph structure containing millions or billions of vertices and edges. Since such huge graphs cannot fit into the memory of a single computer, distributed processing of the graph is required. Several frameworks have been developed for performing graph processing on distributed systems. The frameworks focus primarily on choosing the right computation model and the partitioning scheme under the assumption that such design choices will automatically reduce the communication overheads. For any computational model and partitioning scheme, communication schemes - the data to be communicated and the virtual interconnection network among the nodes - have significant impact on the performance. To analyze this impact, in this work, we identify widely used communication schemes and estimate their performance. Analyzing the trade-offs between the number of compute nodes and communication costs of various schemes on a distributed platform by brute force experimentation can be prohibitively expensive. Thus, our performance estimation models provide an economic way to perform the analyses given the partitions and the communication scheme as input. We validate our model on a local HPC cluster as well as the cloud hosted NSF Chameleon cluster. Using our estimates as well as the actual measurements, we compare the communication schemes and provide conditions under which one scheme should be preferred over the others.

关键词： Distributed Graph Processing performance Estimation Communication Schemes Cluster computing

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GSArch: Breaking Memory Barriers in 3D Gaussian Splatting Training via Architectural Support 31

GSArch: Breaking Memory Barriers in 3D Gaussian Splatting Tr...

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31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： He, Houshu Li, Gang Liu, Fangxin Jiang, Li Liang, Xiaoyao Song, Zhuoran Shanghai Jiao Tong University Department of Computer Science and Engineering Shanghai China Institute of Automation Chinese Academy of Sciences Beijing China

ISBN: (纸本)9798331506476

3D Gaussian Splatting (3DGS) introduces a novel methodology for representing scenes with anisotropic 3D Gaussian primitives, achieving exceptional quality and rendering speed in neural scene representation (NSR). However, the insufficient training speed of 3DGS limits its applicability in tasks that require online learning to perceive dynamic environments, such as autonomous driving and embodied intelligence. Although recent work, GSCore, has introduced a specialized accelerator for the rendering process of 3DGS, it overlooks the time-consuming backward propagation during 3DGS *** this paper, we propose GSArch, a hardware architecture designed to overcome memory barriers and boost the efficiency of 3DGS training. Through a thorough characterization of 3DGS training, we identify three root causes of inefficiency: redundant data loading from off-chip memory, time-consuming atomic write operations, and severe bank conflicts during on-chip buffer reading. To address these challenges, GSArch introduces three architectural innovations. First, acknowledging that Gaussians vary in shape and often span multiple pixels, with larger Gaussians causing more repetitive data loading, GSArch employs hybrid memory management. This approach categorizes Gaussians into 'hot' and 'cold' ones, storing hot Gaussians in a fast but small on-chip buffer to reduce redundant loading while minimizing hardware costs. Second, GSArch leverages the informativeness variability of Gaussians' gradients to filter out low-contribution gradients, significantly reducing atomic operations. Lastly, a rearrangement unit is designed to pack conflicting memory read requests into non-conflicting bundles. Our evaluation results demonstrate that GSArch achieves up to 6.49 × and 15.42 × speedups compared to Nvidia A100 and Jetson AGX Xavier, respectively, with substantially lower energy consumption and negligible image quality loss. © 2025 IEEE.

关键词： Gaussian distribution

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Demonstration of Trajectory Presentation of Conducting Motions Using Tactile Sensation for Visually Impaired 21

Demonstration of Trajectory Presentation of Conducting Motio...

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21st IEEE international symposium on Mixed and Augmented Reality (ISMAR)

作者： Ueda, Yuto Sugiura, Yuta Keio Univ Tokyo Japan

ISBN: (数字)9781665453653

ISBN: (纸本)9781665453653

In this demonstration, we show a method of presenting conducting motions by tactile presentation using vibration actuators. The purpose is to support visually impaired people who have difficulty participating in orchestral or other performance activities by presenting the trajectory of conducting motions. This demonstration explores new possibilities of augmented reality using tactile apparent movement.

关键词： Human-centered computing Human-centered computing Human computer interaction (HCI)

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Integrating Machine Learning and Social Sensing in Smart City Digital Twin for Citizen Feedback 25

Integrating Machine Learning and Social Sensing in Smart Cit...

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25th IEEE international Conferences on high performance computing and Communications, 9th international Conference on Data Science and Systems, 21st IEEE international Conference on Smart City and 9th IEEE international Conference on Dependability in Sensor, Cloud and Big Data Systems and Applications, HPCC/DSS/SmartCity/DependSys 2023

作者： Kumi, Sandra Lomotey, Richard K. Deters, Ralph University of Saskatchewan Department of Computer Science SK Canada The Pennsylvania State University Information Sciences and Technology PA United States

ISBN: (纸本)9798350330014

Smart City Digital Twin (SCDT), a virtual representation of a physical city, is an emerging technology for optimizing urban services and enhancing urban planning and decision-making. The integration of Machine Learning (ML) and social sensing provides valuable insights into public feedback to policymakers and for informed decision-making and responsive urban governance. This study aims to explore the use of social media data and topic modeling algorithms in the context of SCDT to highlight the concerns of citizens in Saskatoon, Canada. In this work, we use the Uniform Manifold Approximation and Projection (UMAP) and K-means clustering algorithm in the BERTopic architecture to extract 30 topics from comments collected through the Saskatoon subreddit posts. The topics were then merged into 15 themes to discover the concerns. A pretrained transformer model, SiEBERT was used to determine the sentiments of the Reddit comments. The research findings highlighted concerns such as - unreliable public transit, high cost of living, long wait times in emergency rooms, shortage of family doctors, drug addiction, and lack of mental awareness. © 2023 IEEE.

关键词： Sentiment analysis

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On the performance of Machine Learning at the Network Edge to Detect Industrial IoT Faults 21

On the Performance of Machine Learning at the Network Edge t...

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21st IEEE international symposium on Network computing and Applications, NCA 2022

作者： Santo, Yuri Dalmazo, Bruno L. Immich, Roger Riker, Andre Federal University of Pará Brazil Federal University of Rio Grande Brazil Federal University of Rio Grande do Norte Brazil

ISBN: (纸本)9798350397307

Industrial Internet-of-Things (IoT) massively deploys intelligent computing in industrial production and manufacturing environments seeking automation, reliability, and control. Machine Learning models provide intelligent decisions to drive manufacturing systems to the next level of productivity, efficiency, and safety. One of the critical challenges that must be faced is the deployment of Machine Learning models at the network edge to detect data anomalies caused by Industrial IoT hardware failures, since industrial IoT devices are prone to errors and failures. These anomalies can harm the industrial IoT system by producing false alarms, consuming network resources, and affecting productivity. Because of that, it is critical to rely on low latency and high precision detection systems to verify the data received from industrial IoT devices. In light of this, we assessed key performance indicators of five machine learning models running at edge computing, to provide in-depth discussions. The performance results were obtained from an oil refinery scenario using a real industrial IoT dataset. The performance was measured in terms of (a) Accuracy, (b) Precision, (c) Recall, (d) F1 score, (e) Training time, and (f) Response time. © 2022 IEEE.

关键词： Edge computing

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SELFWATTS: On-the-fly Selection of performance Events to Optimize Software-defined Power Meters 21

SELFWATTS: On-the-fly Selection of Performance Events to Opt...

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21st IEEE/ACM international symposium on Cluster, Cloud and Internet computing (CCGrid)

作者： Fieni, Guillaume Rouvoy, Romain Seiturier, Lionel Univ Lille INRIA Lille France IUF Lille France

ISBN: (纸本)9781728195865

Fine-grained power monitoring of software-defined infrastructures is unavoidable to maximize the power usage efficiency of data centers. However, the design of the underlying power models that estimate the power consumption of the monitored software components keeps being a long and fragile process that remains tightly coupled to the host machine and prevents a wider adoption by the industry beyond the rich literature on this topic. To overcome these limitations, this paper introduces SELFWATTS: a lightweight power monitoring system that explores and selects the relevant performance events to automatically optimize the power models to the underlying architecture. Unlike state-of-the-art techniques, SELFWATTS does not require any a priori training phase or specific hardware to configure the power models and can be deployed on a wide range of machines, including heterogeneous environments.

关键词： Meters Training Data centers Power demand computer architecture Production Containers

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Dynamic Function Exchange in FPGA to Redefine RISC-V Multicore architectures at Runtime 21st

Dynamic Function Exchange in FPGA to Redefine RISC-V Multi...

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21st international symposium on Applied Reconfigurable computing, ARC 2025

作者： Alves, Téo Sobrino Bonato, Vanderlei Institute of Mathematical and Computing Sciences The University of São Paulo São Paulo São Carlos Brazil

ISBN: (纸本)9783031879944

Dynamic Partial Reconfiguration is a powerful feature available in some FPGAs that enables the reconfiguration of specific regions within the FPGA fabric without halting the whole system. This capability opens new opportunities for more efficient utilization of the available FPGA resources since the hardware can be configured dynamically to better fit the demands of varying workloads. In this work, we investigate the Dynamic Partial Reconfiguration available from Xilinx/AMD FPGAs as Dynamic Function Exchange in multicore RISC-V systems, focusing on maximizing area utilization while minimizing execution time for a set of testbenches. This approach leverages the modularity of the RISC-V architecture that goes beyond the traditional customization provided by the RISC-V processor extensions. As a result for a testbench composed of CNN, Linked List, and Simplex Method, we could notice an improvement from 0.15% to 6% in execution time by dynamically reconfiguring the RISC-V in relation to the number of cores and configurations of each core regarding cache size and availability of FPU. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2025.

关键词： Reconfigurable hardware

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Make LLM Inference Affordable to Everyone: Augmenting GPU Memory with NDP-DIMM 31

Make LLM Inference Affordable to Everyone: Augmenting GPU Me...

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31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Liu, Lian Zhao, Shixin Li, Bing Ren, Haimeng Xu, Zhaohui Wang, Mengdi Li, Xiaowei Han, Yinhe Wang, Ying Institute of Computing Technology Chinese Academic of Sciences China University of Chinese Academy of Sciences China Zhongguancun Laboratory China Institute of Microelectronics Chinese Academy of Sciences China ShanghaiTech University School of Information Science and Technology China

ISBN: (纸本)9798331506476

The billion-scale Large Language Models (LLMs) necessitate deployment on expensive server-grade GPUs with large-storage HBMs and abundant computation capability. As LLM-assisted services become popular, achieving cost-effective LLM inference on budget-friendly hardware becomes the current trend. This has sparked extensive research into relocating LLM parameters from expensive GPUs to external host memory. However, the restricted bandwidth between the host and GPU memory limits the inference performance of existing solutions. This work introduces Hermes, a budget-friendly system that leverages the near-data processing units (NDP) within commodity DRAM DIMMs to enhance the performance of a single consumer-grade GPU, achieving efficient LLM inference. We recognize that the inherent activation sparsity in LLMs naturally divides weight parameters into two categories, termed 'hot' and 'cold' neurons, respectively. Hot neurons, which consist of only approximately 20% of all weight parameters, account for 80% of the total computational load. In contrast, cold neurons make up the other 80% of parameters but are responsible for just 20% of the computational workload. Leveraging this observation, we propose a heterogeneous computing strategy: mapping hot neurons to a single computation-efficient GPU without large-capacity HBMs, while offloading cold neurons to NDP-DIMMs, which offer large memory size but limited computation capabilities. In addition, the dynamic nature of activation sparsity necessitates a real-time partition of hot and cold neurons and adaptive remapping of cold neurons across multiple NDP-DIMM modules. To tackle these issues, we introduce a lightweight predictor that ensures optimal real-time neuron partition and adjustment between GPU and NDP-DIMMs. Furthermore, we utilize a window-based online scheduling mechanism to maintain load balance among multiple NDP-DIMM modules. In summary, Hermes facilitates the deployment of LLaMA2-70B on consumer-grade hardware

关键词： Budget control

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EIF: A Mediated Pass-Through Framework for Inference as a Service 21

EIF: A Mediated Pass-Through Framework for Inference as a Se...

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21st IEEE international symposium on Parallel and Distributed Processing with Applications, 13th IEEE international Conference on Big Data and Cloud computing, 16th IEEE international Conference on Social computing and Networking and 13th international Conference on Sustainable computing and Communications, ISPA/BDCloud/SocialCom/SustainCom 2023

作者： Gao, Yiming Wang, Zhen Wu, Weili Lam, Herman University of Florida Department of Electrical & Computer Engineering GainesvilleFL United States The University of Texas at Dallas Department of Electrical & Computer Engineering RichardsonTX75080 United States The University of Texas at Dallas Department of Computer Science RichardsonTX75080 United States

ISBN: (纸本)9798350329223

In order to effectively provide INaaS (Inference-as-a-Service) for AI applications in resource-limited cloud environments, two major challenges must be overcome: achieving low latency and providing multi-tenancy. This paper presents EIF (Efficient INaaS Framework), which uses a heterogeneous CPU-FPGA architecture to provide three methods to address these challenges (1) spatial multiplexing via software-hardware co-design virtualization techniques, (2) temporal multiplexing that exploits the sparsity of neural-net models, and (3) streaming-mode inference which overlaps data transfer and computation. The prototype EIF is implemented on an Intel PAC (shared-memory CPU-FPGA) platform. For evaluation, 12 types of DNN models were used as benchmarks, with different size and sparsity. Based on these experiments, we show that in EIF, the temporal multiplexing technique can improve the user density of an AI Accelerator Unit from 2 × to 6 × , with marginal performance degradation. In the prototype system, the spatial multiplexing technique supports eight AI Accelerators Unit on one FPGA. By using a streaming mode based on a Mediated Pass-Through architecture, EIF can overcome the FPGA on-chip memory limitation to improve multi-tenancy and optimize the latency of INaaS. To further enhance INaaS, EIF utilizes the MapReduce function to provide a more flexible QoS. Together with the temporal/spatial multiplexing techniques, EIF can support 48 users simultaneously on a single FPGA board in our prototype system. In all tested benchmarks, cold-start latency accounts for only approximately 5% of the total response time. © 2023 IEEE.

关键词： Field programmable gate arrays (FPGA)

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