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high-performance and Scalable Design of MPI-3 RMA on Xeon Phi Clusters 21st

High-Performance and Scalable Design of MPI-3 RMA on Xeon Ph...

引用

21st international Conference on Parallel and Distributed computing (Euro-Par)

作者： Li, Mingzhe Hamidouche, Khaled Lu, Xiaoyi Lin, Jian Panda, Dhabaleswar K. (DK) Ohio State Univ Dept Comp Sci & Engn Columbus OH 43210 USA

ISBN: (纸本)9783662480960;9783662480953

Intel Many Integrated Core (MIC) architectures have been playing a key role in modern supercomputing systems due to the features of high performance and low power consumption. This makes them become an attractive choice to accelerate HPC applications. MPI-3 RMA is an important part of the MPI-3 standard. It provides one-sided semantics that reduce the synchronization overhead and allow overlapping of communication with computation. This makes the RMA model the first target for developing scalable applications with irregular communication patterns. However, an efficient runtime support for MPI-3 RMA with simultaneous use of both processors and co-processors is still not well exploited. In this paper, we propose high-performance and scalable runtime-level designs for MPI-3 RMA involving both the host and Xeon Phi processors. We incorporate our designs into the popular MVAPICH2 MPI library. To the best of our knowledge, this is the first research work that proposes high-performance runtime designs for MPI-3 RMA on Intel Xeon Phi clusters. Experimental evaluations indicate a reduction of 5X in the uni-directional MPI Put and MPI Get latency for 4 MB messages between two Xeon Phis, compared to an out-of-the-box version of MVAPICH2. Application evaluations in the symmetric mode show performance improvements of 25% at the scale of 1,024 processes.

关键词： Semantics

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Event-based scheduling for energy-efficient QoS (eQoS) in mobile Web applications

Event-based scheduling for energy-efficient QoS (eQoS) in mo...

引用

IEEE symposium on high-performance computer architecture

作者： Yuhao Zhu Matthew Halpern Vijay Janapa Reddi Department of Electrical and Computer Engineering The University of Texas at Austin

Mobile Web applications have become an integral part of our society. They pose a high demand for application quality of service (QoS). However, the energy-constrained nature of mobile devices makes optimizing for QoS difficult. Prior art on energy efficiency optimizations has only focused on the trade-off between raw performance and energy consumption, ignoring the application QoS characteristics. In this paper, we propose the concept of energy-efficient QoS (eQoS) to capture the trade-off between QoS and energy consumption. Given the fundamental event-driven nature of mobile Web applications, we further propose event-based scheduling as an optimization framework for eQoS. The event-based scheduling automatically reasons about users' QoS requirements, and accurately slacks the events' execution time to save energy without violating end users' experience. We demonstrate a working prototype using the Google Chromium and V8 framework on the Samsung Exynos 5410 SoC (used in the Galaxy S4 smartphone). Based on real hardware and software measurements, we achieve 41.2% energy saving with only 0.4% of QoS violations perceptible to end users.

关键词： Quality of service Mobile communication Energy consumption Delays Optimization Google Multicore processing

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NDA: Near-DRAM acceleration architecture leveraging commodity DRAM devices and standard memory modules

NDA: Near-DRAM acceleration architecture leveraging commodit...

引用

IEEE symposium on high-performance computer architecture

作者： Amin Farmahini-Farahani Jung Ho Ahn Katherine Morrow Nam Sung Kim University of Wisconsin Madison Seoul National University

Energy consumed for transferring data across the processor memory hierarchy constitutes a large fraction of total system energy consumption, and this fraction has steadily increased with technology scaling. In this paper, we propose near-DRAM acceleration (NDA) architectures, which process data using accelerators 3D-stacked on DRAM devices comprising off-chip main memory modules. NDA transfers most data through high-bandwidth and low-energy 3D interconnects between accelerators and DRAM devices instead of low-bandwidth and high-energy off-chip interconnects between a processor and DRAM devices, substantially reducing energy consumption and improving performance. Unlike previous near-memory processing architectures, NDA is built upon commodity DRAM devices; apart from inserting through-silicon vias (TSVs) to 3D-interconnect DRAM devices and accelerators, NDA requires minimal changes to the commodity DRAM device and standard memory module architectures. This allows NDA to be more easily adopted in both existing and emerging systems. Our experiments demonstrate that, on average, our NDA-based system consumes 46% (68%) lower (data transfer) energy at 1.67× higher performance than a system that integrates the same accelerator logic within the processor itself.

关键词： Random access memory Microarchitecture computer architecture Through-silicon vias Data transfer Bandwidth performance evaluation

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Application-Oriented Sensor Network architecture for Dependable structural Health Monitoring

Application-Oriented Sensor Network Architecture for Dependa...

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Pacific Rim international symposium on Dependable computing

作者： Md Zakirul Alam Bhuiyany Guojun Wang Jie Wu Xing Xiaofei Xiangyong Liu Temple University Philadelphia PA US School of Computer Science and Education Software Guangzhou University Guangzhou School of Information Science and Engineering. Central South University Changsha Hunan P. R. China Department of Computer and Information Sciences Temple University Philadelphia PA USA

Wireless sensor networks (WSNs) are being deployed for structural health monitoring (SHM) applications at an increasing rate. A WSN is often organized into groups or clusters for distributed monitoring purposes. However, we discover that the dependability (in terms of the monitoring ability/quality and low false alarm rate) is greatly affected by such grouping schemes, as they do not satisfy application-specific monitoring aspects. We present an SHM application oriented network architecture (SHMnet) and analyze health event monitoring performance with it. We propose a substructure-oriented sensor organization (SOSO), considering the formation of engineering structures and finding that a large physical structure consists of a number of substructures. We enable deployed sensors to be organized into groups (unlike dynamic clusters/trees) in such a way that each group of sensors can monitor a substructure independently. We evaluate SHMnet via simulations using real data traces. The evaluation results, compared to existing work, show that SHMnet achieves at least five times the energy saving (including the energy for communication) in WSNs and dependability in terms of high ability of monitoring and low false alarm rate.

关键词： Wireless sensor networks Monitoring Data communication computer science Organizations Wireless communication

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GPU voltage noise: Characterization and hierarchical smoothing of spatial and temporal voltage noise interference in GPU architectures

GPU voltage noise: Characterization and hierarchical smoothi...

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IEEE symposium on high-performance computer architecture

作者： Jingwen Leng Yazhou Zu Vijay Janapa Reddi Department of Electrical and Computer Engineering The University of Texas at Austin

Energy efficiency is undoubtedly important for GPU architectures. Besides the traditionally explored energy-efficiency optimization techniques, exploiting the supply voltage guard-band remains a promising yet unexplored opportunity. Our hardware measurements show that up to 23% of the nominal supply voltage can be eliminated to improve CPU energy efficiency by as much as 25%. The key obstacle for exploiting this opportunity lies in understanding the characteristics and root causes of large voltage droops in GPU architectures and subsequently smoothing them away without severe performance penalties. The CPU's manycore nature complicates the voltage noise phenomenon, and its distinctive architecture features from the CPU necessitate a CPU-specific voltage noise analysis. In this paper, we make the following contributions. First, we provide a voltage noise categorization framework to identify, characterize, and understand voltage noise in the manycore CPU architecture. Second, we perform a microarchitecture-level voltage-droop root-cause analysis for the two major droop types we identify, namely the local first-order droop and the global second-order droop. Third, on the basis of our categorization and characterization, we propose a hierarchical voltage smoothing mechanism that mitigates each type of voltage droop. Our evaluation shows it can reduce up to 31% worst-case droop, which translates to 11.8% core-level and 7.8% processor-level energy reduction.

关键词： Noise Graphics processing units Smoothing methods Impedance Voltage measurement computer architecture System-on-chip

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Prediction-based superpage-friendly TLB designs

Prediction-based superpage-friendly TLB designs

引用

IEEE symposium on high-performance computer architecture

作者： Misel-Myrto Papadopoulou Xin Tong André Seznec Andreas Moshovos Dept. of Electrical and Computer Engineering University of Toronto Toronto Canada IRISA/INRIA Rennes France

This work demonstrates that a set of commercial and scale-out applications exhibit significant use of superpages and thus suffer from the fixed and small superpage TLB structures of some modern core designs. Other processors better cope with superpages at the expense of using power-hungry and slow fully-associative TLBs. We consider alternate designs that allow all pages to freely share a single, power-efficient and fast set-associative TLB. We propose a prediction-guided multi-grain TLB design that uses a superpage prediction mechanism to avoid multiple lookups in the common case. In addition, we evaluate the previously proposed skewed TLB [1] which builds on principles similar to those used in skewed associative caches [2]. We enhance the original skewed TLB design by using page size prediction to increase its effective associativity. Our prediction-based multi-grain TLB design delivers more hits and is more power efficient than existing alternatives. The predictor uses a 32-byte prediction table indexed by base register values.

关键词： Registers Program processors Indexing Hardware computers Data structures

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Bamboo ECC: strong, safe, and flexible codes for reliable computer memory

Bamboo ECC: Strong, safe, and flexible codes for reliable co...

引用

IEEE symposium on high-performance computer architecture

作者： Jungrae Kim Michael Sullivan Mattan Erez Department of Electrical and Computer Engineering The University of Texas at Austin

Growing computer system sizes and levels of integration have made memory reliability a primary concern, necessitating strong memory error protection. As such, large-scale systems typically employ error checking and correcting codes to trade redundant storage and bandwidth for increased reliability. While stronger memory protection will be needed to meet reliability targets in the future, it is undesirable to further increase the amount of storage and bandwidth spent on redundancy. We propose a novel family of single-tier ECC mechanisms called Bamboo ECC to simultaneously address the conflicting requirements of increasing reliability while maintaining or decreasing error protection overheads. Relative to the state-of-the-art single-tier error protection, Bamboo ECC codes have superior correction capabilities, all but eliminate the risk of silent data corruption, and can also increase redundancy at a fine granularity, enabling more adaptive graceful downgrade schemes. These strength, safety, and flexibility advantages translate to a significantly more reliable memory system. To demonstrate this, we evaluate a family of Bamboo ECC organizations in the context of conventional 72b and 144b DRAM channels and show the significant error coverage and memory lifespan improvements of Bamboo ECC relative to existing SEC-DED, chipkill-correct and double-chipkill-correct schemes.

关键词： Error correction codes Redundancy DRAM chips Error correction Decoding

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GPGPU performance and power estimation using machine learning

GPGPU performance and power estimation using machine learnin...

引用

IEEE symposium on high-performance computer architecture

作者： Gene Wu Joseph L. Greathouse Alexander Lyashevsky Nuwan Jayasena Derek Chiou Electrical and Computer Engineering The University of Texas at Austin AMD Research Advanced Micro Devices Inc.

Graphics Processing Units (GPUs) have numerous configuration and design options, including core frequency, number of parallel compute units (CUs), and available memory bandwidth. At many stages of the design process, it is important to estimate how application performance and power are impacted by these options. This paper describes a GPU performance and power estimation model that uses machine learning techniques on measurements from real GPU hardware. The model is trained on a collection of applications that are run at numerous different hardware configurations. From the measured performance and power data, the model learns how applications scale as the GPU's configuration is changed. Hardware performance counter values are then gathered when running a new application on a single GPU configuration. These dynamic counter values are fed into a neural network that predicts which scaling curve from the training data best represents this kernel. This scaling curve is then used to estimate the performance and power of the new application at different GPU configurations. Over an 8× range of the number of CUs, a 3.3× range of core frequencies, and a 2.9× range of memory bandwidth, our model's performance and power estimates are accurate to within 15% and 10% of real hardware, respectively. This is comparable to the accuracy of cycle-level simulators. However, after an initial training phase, our model runs as fast as, or faster than the program running natively on real hardware.

关键词： Kernel Hardware Training Radiation detectors Graphics processing units Predictive models Engines

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CAFO: Cost aware flip optimization for asymmetric memories

CAFO: Cost aware flip optimization for asymmetric memories

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IEEE symposium on high-performance computer architecture

作者： Rakan Maddah Seyed Mohammad Seyedzadeh Rami Melhem Computer Science Department University of Pittsburgh

Phase Change Memory (PCM) and spin-transfer torque random access memory (stT-RAM) are emerging as new memory technologies to replace DRAM and NAND flash that are impeded by physical limitations. Programming PCM cells degrades their endurance while programming stT-RAM cells incurs a high bit error rate. Accordingly, several schemes have been proposed to service write requests while programing as few memory cells as possible. Nevertheless, those schemes did not address the asymmetry in programming memory cells that characterizes both PCM and stT-RAM. For instance, writing a bit value of 0 on PCM cells is more detrimental to endurance than 1 while writing a bit value of 1 on stT-RAM cells is more prone to error than 0. In this paper, we propose CAFO as a new cost aware flip reduction scheme. Essentially, CAFO encompasses a cost model that computes the cost of servicing write requests through assigning different costs to each cell that requires programming. Subsequently, CAFO encodes the data to be written into a form that incurs less cost through its cost aware encoding module. Overall, CAFO is capable of cutting down the write cost by up to 65% more than existing schemes.

关键词： Phase change materials Writing Vectors Encoding Resistance Random access memory Programming

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Event-Action Mappings for Parallel Tools Infrastructures 21st

Event-Action Mappings for Parallel Tools Infrastructures

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21st international Conference on Parallel and Distributed computing (Euro-Par)

作者： Hilbrich, Tobias Schulz, Martin Brunst, Holger Protze, Joachim de Supinski, Bronis R. Mueller, Matthias S. Tech Univ Dresden D-01062 Dresden Germany Lawrence Livermore Natl Lab Livermore CA 94551 USA Rhein Westfal TH Aachen D-52056 Aachen Germany JARA High Performance Comp D-52062 Aachen Germany

ISBN: (纸本)9783662480960;9783662480953

The development of applications for high performance computing (HPC) systems is a challenging task. Development steps such as optimization, tuning, porting, and debugging often motivate the use of tools, many of which operate at application runtime. Current trends in the HPC community, such as increasing compute core counts and the advent of new programming paradigms challenge the development of applications, as well as the development of runtime tools. Parallel tools infrastructures can help to simplify the development and adaption of runtime tools by reducing development time and increasing applicability. They can provide reusable tool components, communication services, and abstractions for scalable tools, which preserve lessons learned from existing tools projects. This paper defines an abstraction for a highly integrated infrastructure, which we implement in a prototype that targets MPI applications. Our abstraction enables an incorporation of common tasks such as instrumentation, i.e., observing application behavior, with existing concepts for tool communication, while at the same time enabling scalability. A formal description of our abstraction allows us to highlight its design and to differentiate it from alternatives, so tool developers have a clear understanding of the high-level approach that our infrastructure follows. Existing prototype tools that are based on this infrastructure demonstrate applicability at 1,024 and 16,384 processes respectively.

关键词： Abstracting

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