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检索条件"任意字段=21st International Symposium on Computer Architecture and High Performance Computing"

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Parallel AMG solver for three dimensional unstructured grids using GPU 21

Parallel AMG solver for three dimensional unstructured grids...

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2014 21st international Conference on high performance computing, HiPC 2014

作者： Tej, K. Ravi Sivadasan, Naveen Sharma, Vatsalya Banerjee, Raja Dept. of Computer Science and Engineering Indian Institute of Technology Hyderabad Hyderabad India Dept. of Mechanical Engineering Indian Institute of Technology Hyderabad Hyderabad India

ISBN: (纸本)9781479959761

Graphics Processing Units (GPUs) have evolved over the years from being graphics accelerator to scalable coprocessor. We implement an algebraic multigrid solver for three dimensional unstructured grids using GPU. Such a solver has extensive applications in Computational Fluid Dynamics (CFD). Using a combination of vertex coloring, optimized memory representations, multi-grid and improved coarsening techniques, we obtain considerable speedup in our parallel implementation. Our solver provides significant acceleration for solving pressure Poisson equations, which is the most time consuming part while solving Navier-stokes equations. In our experimental study, we solve pressure Poisson equations for flow over lid driven cavity and for laminar flow past square cylinder. Our implementation achieves 915 times speed up for the lid driven cavity problem on a grid of size 2.6 million and a speed up of 1020 times for the laminar flow past square cylinder problem on a grid of size 1.7 million, compared to serial non-multigrid implementations. For our implementation, we used NVIDIA's CUDA programming model. © 2014 IEEE.

关键词： Graphics processing unit

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XG-PON Optical Network Unit Downstream FEC Design Based on Truncated Reed-Solomon Code 21

XG-PON Optical Network Unit Downstream FEC Design Based on T...

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2014 21st IEEE international Conference on Electronics, Circuits and Systems (ICECS)

作者： Georgis, Georgios Tzeranis, Charalambos Reisis, Dionysios Synnefakis, George Univ Athens Fac Phys Elect Lab Athens Greece InAccess Networks SA R&D Ctr Athens Greece

ISBN: (纸本)9781479942428

The XG-PON standard for Passive Optical Networks (PONS) requires the utilization of a Reed-Solomon block code at a 10Gbps downstream rate, dictating low latency and high throughput processing, no word interleaving and no stall between codewords. The current paper presents in detail a parallel architecture which decodes the RS(248,216) shortened code in the XG-PON ONT/ONU receiver. Based on a modified implementation of the Degree-Computationless Modified Euclidean (DCME) algorithm, the designed Key Equation Solver (KES) and its control unit allow for both solving the key equation and computing the number of the errors detected, in 31 clock cycles. Validating the proposed design on a Xilinx Kintex 7 FPGA and comparing to a pipelined serial DCME implementation reveals a reduction of 48% in the number of slices occupied and 6 times regarding the latency induced. Our implementation achieves a throughput of 16Gbps on the specified device thus meeting the XG-PON downstream FEC requirements with relatively low effort. The results could be adapted for a multitude of optical communication standards based on RS codes due to the 64-bit pipelined architecture and the FPGA-transparent HDL design.

关键词： Reed-Solomon codes decoding field programmable gate arrays interleaved codes optical receivers parallel architectures passive optical networks pipeline processing DCME algorithm FPGA-transparent HDL design KES control unit RS(248 216) shortened code decoding XG-PON ONT receiver XG-PON ONU receiver XG-PON optical network unit downstream FEC design Xilinx Kintex 7 FPGA bit error rate codewords degree-computationless modified Euclidean algorithm error detection high throughput processing key equation solver low latency optical communication standard parallel architecture passive optical network terminal pipelined architecture truncated Reed-Solomon block code word interleaving Clocks computer architecture Decoding Forward error correction Optical network units Polynomials

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Local characteristics of minority examples in pre-processing of imbalanced data

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21st international symposium on Methodologies for Intelligent Systems, ISMIS 2014

作者： stefanowski, Jerzy Napierala, Krystyna Trzcielińska, Malgorzata Institute of Computing Science Poznań University of Technology 60-965 Poznań Poland

ISBN: (纸本)9783319083254

Informed pre-processing methods for improving classifiers learned from class-imbalanced data are considered. We discuss different ways of analyzing the characteristics of local distributions of examples in such data. Then, we experimentally compare main informed pre-processing methods and show that identifying types of minority examples depending on their k nearest neighbourhood may help in explaining differences in performance of these methods. Finally, we exploit the information about the local neighbourhood to modify the oversampling ratio in a SMOTE-related method. © 2014 Springer international Publishing.

关键词： Processing

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An adaptive zero-copy strategy for ubiquitous high performance computing 14

An adaptive zero-copy strategy for ubiquitous high performan...

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21st European MPI Users' Group Meeting, EuroMPI/ASIA 2014

作者： Chien, Ting-Hsuan Chen, Chia-Jung Chang, Rong-Guey Dept. of Computer Science and Information Engineering Advanced Institute for Manufacturing with High-tech Innovations National Chung Cheng University Chia-Yi Taiwan

ISBN: (纸本)9781450328753

Using a heterogeneous platform has became a common approach to improve performance. This trend leads to critical problems of synchronization and superfluous memory copy construct, thus a memory model can be built to overcome this performance bottleneck via data exchange. Consequently, keeping the benefits of service consolidation while not losing performance and IO efficiency has become a crucial issue. In this paper, we present an adaptive strategy to solve the issue above in an efficient way. We first identify the critical overheads on Linux and and then presents a clever software zero-copy strategy to construct a prototype. Finally, we can optimize the work and leverage the hardware features to reduce the overhead of data copy. The result shows that the proposed prototype is an adaptive approach to perform service consolidation. © ACM 2014.

关键词： Ubiquitous computing

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Trajectory Pattern Mining over a Cloud-based Framework for Urban computing 16

Trajectory Pattern Mining over a Cloud-based Framework for U...

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16th IEEE Int Conf on high performance computing and Communications/11th IEEE Int Conf on Embedded Software and Systems\6th Int symposium on Cyberspace Safety and Security

作者： Altomare, Albino Cesario, Eugenio Comito, Carmela Marozzo, Fabrizio Talia, Domenico ICAR CNR Arcavacata Di Rende CS Italy Univ Calabria DIMES I-87030 Commenda Di Rende Italy

ISBN: (纸本)9781479961238

The increasing pervasiveness of mobile devices along with the use of technologies like GPS, Wifi networks, RFID, and sensors, allows for the collections of large amounts of movement data. This amount of information can be analyzed to extract descriptive and predictive models that can be properly exploited to improve urban life. This paper presents a workflow-based parallel approach for discovering patterns and rules from trajectory data, executed on a Cloud-based framework for urban computing. Experimental evaluation shows that, due to complexity and large data involved in the application scenario, the trajectory pattern mining process takes advantage from the scalable execution environment offered by a Cloud architecture.

关键词： trajectory data mining trajectory Mobile devices Prediction models Frameworks Town life

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Power Consumption Analysis of Parallel Algorithms on GPUs 16

Power Consumption Analysis of Parallel Algorithms on GPUs

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16th IEEE Int Conf on high performance computing and Communications/11th IEEE Int Conf on Embedded Software and Systems\6th Int symposium on Cyberspace Safety and Security

作者： Magoules, Frederic Ahamed, Abal-Kassim Cheik Desmaison, Alban Lechenet, Jean-Christophe Mayer, Francois Ben Salem, Haifa Zhu, Thomas Ecole Cent Paris CUDA Res Ctr Paris France

ISBN: (纸本)9781479961238

Due to their highly parallel multi-cores architecture, GPUs are being increasingly used in a wide range of computationally intensive applications. Compared to CPUs, GPUs can achieve higher performances at accelerating the programs' execution in an energy-efficient way. Therefore GPGPU computing is useful for high performance computing applications and in many scientific research fields. In order to bring further performance improvements, GPU clusters are increasingly adopted. The energy consumed by GPUs cannot be neglected. Therefore, an energy-efficient time scheduling of the programs that are going to be executed by the parallel GPUs based on their deadline as well as the assigned priorities could be deployed to face their energetic avidity. For this reason, we present in this paper a model enabling the measure of the power consumption and the time execution of some elementary operations running on a single GPU using a new developed energy measurement protocol. Consequently, using our methodology, energy needs of a program could be predicted, allowing a better task scheduling.

关键词： Energy Measuring Device Energy Consumption Green computing Linear Algebra Operation Prediction Algorithm Task Scheduling Algorithm GPU Parallel computing Gravity equation

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Optimizing a calibration software for radio astronomy 16

Optimizing a calibration software for radio astronomy

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16th IEEE Int Conf on high performance computing and Communications/11th IEEE Int Conf on Embedded Software and Systems\6th Int symposium on Cyberspace Safety and Security

作者： Madougou, Souley Varbanescu, Ana L. van Nieuwpoort, Rob Univ Amsterdam IvI Amsterdam Netherlands Netherlands eSci Ctr Amsterdam Netherlands

ISBN: (纸本)9781479961238

With the turn to multicore in chip design and manufacturing, both consumer and high performance applications can benefit from ubiquitous hardware parallelism. However, the performance improvement to be achieved is not always in the orders of magnitude range. In this paper, we present the challenging example of designing a parallel version of a model fitting algorithm used in calibrating telescope observation data in radio astronomy. The complexity of the application, together with the limited opportunities for code modification, bound the performance gain that any parallel system could achieve. However, we show how classical bound-and-bottleneck analysis and optimization using multicore architectures help achieving up to 2.3x "wallclock" speedup compared to the original sequential implementation. We further discuss the reasons for this limitation, and suggest possible solutions to address it.

关键词： code optimization model fitting multicore architecture parallel computing radio astronomy radio astronomy code optimization mode matching PARALLEL PROCESSING (computerS) Multi-core processors chip scale packaging parallel system

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Online performance Analysis: An Event-based Workflow Design Towards Exascale 16

Online Performance Analysis: An Event-based Workflow Design ...

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16th IEEE Int Conf on high performance computing and Communications/11th IEEE Int Conf on Embedded Software and Systems\6th Int symposium on Cyberspace Safety and Security

作者： Wagner, Michael Hilbrich, Tobias Brunst, Holger Tech Univ Dresden Ctr Informat Serv & High Performance Comp ZIH D-01062 Dresden Germany

ISBN: (纸本)9781479961238

Today, it is commonly accepted that speedup and efficiency are not granted automatically when developing or porting software for high performance computing (HPC) platforms. The reasons are manifold and actively investigated in the community. Software monitors are essential for these studies as they provide the raw performance data to be analyzed. We propose an online monitoring workflow for event-based performance analysis that takes into account the significant changes in system architecture towards the development of exascale supercomputers. Critical properties are: communication across large numbers of processing elements, limited I/O capabilities, and a decreasing memory-per- core ratio. We present a hierarchical data management and steering workflow that directly couples the application, measurement, and analysis processes, thus eliminating the need for extensive communication and buffering. The workflow is closely integrated with the native system communication API to enable best communication across processing elements. The memory issue is addressed with a new lossy hierarchical data compression technique for in-memory storage, intended for small, fixed-size buffers. Further, we abandon secondary storage to avoid potential I/O challenges. We demonstrate the feasibility of our design with a prototype implementation that features services for data collection, analysis, and runtime compression. Our evaluation extrapolates results obtained with the NAS Parallel Benchmarks at up to 2,048 processes to an exascale workflow.

关键词： GTI OTFX Online performance analysis event tracing online tracing Workflow Event-based data compression technology AUXILIARY stORAGE Communication Research IO high performance computing Data management Speeding

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21st Century computer architecture Keynote at 2014 international Conference on Supercomputing (ICS) 14

21st Century Computer Architecture Keynote at 2014 Internati...

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28th ACM international Conference on Supercomputing (ICS)

作者： Hill, Mark D. Univ Wisconsin Dept Comp Sci Madison WI 53706 USA

ISBN: (纸本)9781450326421

This talk has two parts. The first part will discuss possible directions for computer architecture research, including architecture as infrastructure, energy first, impact of new technologies, and cross-layer opportunities. This part is based on a 2012 computing Community Consortium (CCC) whitepaper effort led by Hill, as well as other recent National Academy and ISAT studies. See: http ://***/ccc/docs/init/*** The second part of the talk will discuss examples of cross layer research advocated in the first part. First, our analysis shows that many "big-memory" server workloads, such as databases, in-memory caches, and graph analytics, pay a high cost for page-based virtual memory: up to 50% of execution time wasted. Via small changes to the operating system (Linux) and hardware (x86-64 MMU), this work reduces execution time these workloads waste to less than 0.5%. The key idea is to map part of a process's linear virtual address space with a new incarnation of segmentation, while providing compatibility by mapping the rest of the virtual address space with paging. Second, we will briefly discuss memory consistency models for graphic processing units (GPUs) and other accelerators that support synchronization on a subset of threads called "scopes."

关键词： computer systems architecture programming methods performance energy new technology

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Research on Mahalanobis Distance Algorithm Optimization Based on OpenCL 16

Research on Mahalanobis Distance Algorithm Optimization Base...

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16th IEEE Int Conf on high performance computing and Communications/11th IEEE Int Conf on Embedded Software and Systems\6th Int symposium on Cyberspace Safety and Security

作者： Xie, Qingchun Zhang, Yunquan Jia, Haipeng Lu, Yongquan Commun Univ China High Performance Comp Ctr Beijing 100024 Peoples R China Chinese Acad Sci Inst Software Lab Parallel Comp Beijing 100190 Peoples R China Chinese Acad Sci Inst Comp Technol State Key Lab Comp Architecture Beijing 100190 Peoples R China

ISBN: (纸本)9781479961238

Mahalanobis distance algorithms has been widely used in machine learning and classification algorithms, and it has an important practical significance in improving the performance of some applications through GPU, especially in some applications with high real-time demand. However, due to the complexity of the GPU hardware architectures, how to complete the algorithm optimization and achieve high performance portability on different GPU platforms is still a hard work. The redundant calculation of traditional Mahalanobis distance algorithm is very large and is hard to implement parallel. In this paper, we not only throw light on the universal ways to properly map mature algorithms to GPU devices to implement the Mahalanobis distance, such as fixed number of workgroups and vectorization, but also put forward five valuable methods of performance optimization on heterogeneous computing platforms, such as two-dimension NDRange workgroup arrangement, Uberkernel, binary reduction with the help of LDS register in one workgroup. Furthermore, We also demonstrate the high performance of our implementation by comparing it with a well-optimized CPU version from OpenCV library. Experimental results show that speedup reaches up 10.59 times on NVIDIA GPU C2050, 8.55 times on AMD HD5850 and 16.08 times on HD7970. The last experimental results verified the effectiveness of optimization methods which we proposed.

关键词： OpenCL Heterogeneous computing GPU Mahalanobis Parallel Optimization

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