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检索条件"任意字段=21st International Symposium on Computer Architecture and High Performance Computing"

共 1767 条记录，以下是141-150 订阅

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LIMOCE: Live Migration of Containers in the Edge 21

LIMOCE: Live Migration of Containers in the Edge

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21st IEEE/ACM international symposium on Cluster, Cloud and Internet computing (CCGrid)

作者： Das, Rohit Sidhanta, Subhajit IIT Bhilai Sejbahar India

ISBN: (纸本)9781728195865

Being comprised of resource-constrained edge devices, live migration is a necessary feature in edge clusters for migrating state of an entire machine in case of machine failures and network partitions without disrupting continued availability of services. While most of the prior work in this area has provided solutions for live migration on clusters comprised of resource-rich servers or fog servers with high computing power, there is a general lack of research in live migration on the low-end ARM devices comprised in edge clusters. To that end, we propose a lightweight algorithm for performing live migration on resource constrained edge clusters. We provide an open source implementation of the above algorithm for migrating containers in Linux. We demonstrate that our algorithm outperforms state-of-the-art live migration algorithms on resource constrained edge clusters with network partitions and device failures.

关键词： performance evaluation Cloud computing Image edge detection Linux Computational modeling Clustering algorithms Containers

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An evaluation of fault-tolerant hypercube architectures for onboard computing

An evaluation of fault-tolerant hypercube architectures for ...

引用

21st international symposium on Fault-Tolerant computing

作者： Peterson, J.C. Tuazon, J.O. Upchurch, E.T. Jet Propulsion Lab California Inst of Technol Pasadena CA USA

ISBN: (纸本)0818621508

Four hypercube architectures that are designed to use hardware resources more efficiently and that produce computers with high throughput and high reliability are evaluated. Spare nodes in three of the architectures are configured so that the entire computer has the topology of an incomplete hypercube. Here, the nodes of an incomplete hypercube are capable of providing different levels of fault detection, hardware reconfiguration, and routing. In the other architecture, the hypercube topology uses conventional switches capable only of establishing connections. End-of-mission dependability models and performance simulation models were developed. Results of performance degradation studies of the four architectures under reconfiguration in terms of throughput, response time, and communication utilization are presented for three workloads. The evaluations addressed performance-related dependability based on hardware failures and reconfiguration using hardware.

关键词： computer Systems, Digital

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A high Throughput No-stall Golomb-Rice Hardware Decoder

A High Throughput No-Stall Golomb-Rice Hardware Decoder

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21st Annual international IEEE symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Moussalli, Roger Najjar, Walid Luo, Xi Khan, Amna Univ Calif Riverside Dept Comp Sci & Engn Riverside CA 92521 USA

ISBN: (纸本)9780769549699;9781467360050

Integer compression techniques can generally be classified as bit-wise and byte-wise approaches. Though at the cost of a larger processing time, bit-wise techniques typically result in a better compression ratio. The Golomb-Rice (GR) method is a bit-wise lossless technique applied to the compression of images, audio files and lists of inverted indices. However, since GR is a serial algorithm, decompression is regarded as a very slow process;to the best of our knowledge, all existing software and hardware native (non-modified) GR decoding engines operate bit-serially on the encoded stream. In this paper, we present (1) the first no-stall hardware architecture, capable of decompressing streams of integers compressed using the GR method, at a rate of several bytes (multiple integers) per hardware cycle;(2) a novel GR decoder based on the latter architecture is further detailed, operating at a peak rate of one integer per cycle. A thorough design space exploration study on the resulting resource utilization and throughput of the aforementioned approaches is presented. Furthermore, a performance study is provided, comparing software approaches to implementations of the novel hardware decoders. While occupying 10% of a Xilinx V6LX240T FPGA, the no-stall architecture core achieves a sustained throughput of over 7 Gbps.

关键词： FPGA Golomb-Rice compression decompression inverted index

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GridCopy: Moving data fast on the grid

GridCopy: Moving data fast on the grid

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21st international Parallel and Distributed Processing symposium, IPDPS 2007

作者： Kettimuthu, Rajkumar Allcock, William Liming, Lee Navarro, John-Paul Foster, Ian Mathematics and Computer Science Division Argonne National Laboratory Argonne IL 60439 Computation Institute University of Chicago Chicago IL 60637 Department of Computer Science University of Chicago Chicago IL 60637

ISBN: (纸本)1424409101

An important type of communication in grid and distributed computing environments is bulk data transfer. GridFTP has emerged as a de facto standard for secure, reliable, high-performance data transfer across resources on the Grid. GridCopy provides a simple GridFTP client interface to users and extensible configuration that can be changed dynamically by administrators to make efficient data movement in the Grid easier for users. © 2007 IEEE.

关键词： Grid computing

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Proceedings of the 21st ACM international Conference on computing Frontiers, CF 2024

Proceedings of the 21st ACM International Conference on Comp...

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21st ACM international Conference on computing Frontiers, CF 2024

ISBN: (纸本)9798400705977

The proceedings contain 45 papers. The topics discussed include: Denseflex: a low rank factorization methodology for adaptable dense layers in DNNs;a lightweight architecture for real-time neuronal-spike classification;PEARL: enabling portable, productive, and high-performance deep reinforcement learning using heterogeneous platforms;mini-batching with fused training and testing for data streams processing on the edge;energy-aware IoT deployment planning;register blocking: an analytical modelling approach for affine loop kernels;hardware support for balanced co-execution in heterogeneous processors;HLS taking flight: toward using high-level synthesis techniques in a space-borne instrument;an ANN-guided multi-objective framework for power-performance balancing in HPC systems;and clustering and allocation of spiking neural networks on crossbar-based neuromorphic architecture.

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Detecting I/O Access Patterns of HPC Workloads at Runtime 31

Detecting I/O Access Patterns of HPC Workloads at Runtime

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31st international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Bez, Jean Luca Boito, Francieli Zanon Nou, Ramon Miranda, Alberto Cortes, Toni Navaux, Philippe O. A. Univ Fed Rio Grande do Sul Inst Informat Porto Alegre RS Brazil Univ Grenoble Alpes INRIA CNRS Grenoble INPLIG F-38000 Grenoble France BSC Barcelona Spain Univ Politecn Cataluna Barcelona Spain

ISBN: (纸本)9781728141947

In this paper, we seek to guide optimization and tuning strategies by identifying the application's I/O access pattern. We evaluate three machine learning techniques to automatically detect the I/O access pattern of HPC applications at runtime: decision trees, random forests, and neural networks. We focus on the detection using metrics from file-level accesses as seen by the clients, I/O nodes, and parallel file system servers. We evaluated these detection strategies in a case study in which the accurate detection of the current access pattern is fundamental to adjust a parameter of an I/O scheduling algorithm. We demonstrate that such approaches correctly classify the access pattern, regarding file layout and spatiality of accesses - into the most common ones used by the community and by I/O benchmarking tools to test new I/O optimization - with up to 99% precision. Furthermore, when applied to our study case, it guides a tuning mechanism to achieve 99% of the performance of an Oracle solution.

关键词： high-performance computing parallel I/O access pattern detection I/O forwarding classification

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Analyzing a Five-year Failure Record of a Leadership-class Supercomputer 31

Analyzing a Five-year Failure Record of a Leadership-class S...

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31st international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Rojas, Elvis Meneses, Esteban Jones, Terry Maxwell, Don Natl Univ Costa Rica Costa Rica Inst Technol Heredia Costa Rica Costa Rica Inst Technol Costa Rica Natl High Technol Ctr San Jose Costa Rica Oak Ridge Natl Lab Oak Ridge TN USA

ISBN: (纸本)9781728141947

Extreme-scale computing systems are required to solve some of the grand challenges in science and technology. From astrophysics to molecular biology, supercomputers are an essential tool to accelerate scientific discovery. However, large computing systems are prone to failures due to their complexity. It is crucial to develop an understanding of how these systems fail to design reliable supercomputing platforms for the future. This paper examines a five-year failure and workload record of a leadership-class supercomputer. To the best of our knowledge, five years represents the vast majority of the lifespan of a supercomputer. This is the first time such analysis is performed on a top 10 modern supercomputer. We performed a failure categorization and found out that: i) most errors are GPU-related, with roughly 37% of them being double-bit errors on the cards;ii) failures are not evenly spread across the physical machine, with room temperature presumably playing a major role;and iii) software errors of the system bring down several nodes concurrently. Our failure rate analysis unveils that: i) the system consistently degrades, being at least twice as reliable at the beginning, compared to the end of the period;ii) Weibull distribution closely fits the mean-time-between-failure data;and iii) hardware and software errors show a markedly different pattern. Finally, we correlated failure and workload records to reveal that: i) failure and workload records are weakly correlated, except for certain types of failures when segmented by the hours of the day;ii) several categories of failures make jobs crash within the first minutes of execution;and iii) a significant fraction of failed jobs exhaust the requested time with a disregard of when the failure occurred during execution.

关键词： Fault tolerance resilience failure analysis high performance computing

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Superpixel Accelerator for computer Vision Applications on Arria 10 SoC 21

Superpixel Accelerator for Computer Vision Applications on A...

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21st IEEE international symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)

作者： Akagic, Amila Buza, Emir Turcinhodzic, Razija Haseljic, Hana Noda, Hiroyuki Amano, Hideharu Univ Sarajevo Fac Elect Engn Dept Comp Sci & Informat Sarajevo Bosnia & Herceg Keio Univ Sch Sci & Technol Dept Informat & Comp Sci Tokyo Japan

ISBN: (纸本)9781538657546

Superpixel segmentation is a very popular image segmentation technique used in various computer vision tasks. Recently, a number of superpixel algorithms have been proposed in literature. One such algorithm is considered as the-state-of-the-art in superpixel segmentation: Simple Linear Iterative Clustering or SLIC. However, its original implementation has a long execution time on high performance processors designed within the common mobile and enterprise applications, as well on high-end processors such as Intel Xeon. Overall, the execution time for single-threaded implementation is considered critical for real-time or near real-time applications. In this paper, we explore the possibility of accelerating parts of the SLIC image segmentation critical for performance, by designing the image segmentation accelerator for Intel's Arria 10 SoC. We propose a novel architecture to enable hardware acceleration by addressing the problem of hardware/software partitioning to minimize the overall program latency.

关键词： Image segmentation Clustering algorithms Image color analysis Task analysis computer vision Real-time systems Visualization

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Design and implementation of CNN custom processor based on risc-v architecture 21

Design and implementation of CNN custom processor based on r...

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21st IEEE international Conference on high performance computing and Communications, 17th IEEE international Conference on Smart City and 5th IEEE international Conference on Data Science and Systems, HPCC/SmartCity/DSS 2019

作者： Li, Zhenhao Hu, Wei Chen, Shuang College of Computer Science and Technology Wuhan University of Science and Technology China Hubei Province Key Laboratory of Intelligent Information Processing Real-time Industrial System China

ISBN: (纸本)9781728120584

With the rapid development of CNN(convolutional neural networks), the traditional CPU platform can not make full use of the parallelism of CNN. We decide to adopt a new and popular processor architecture: the risc-v architecture for experimental design. In this paper, a new convolutional neural network processor is designed based on risc-v architecture. The processor can take advantage of the parallelism of CNN and is more flexible. This paper completely designed a CNN processor based on the risc-v architecture. The processor uses a classic five-stage pipeline structure, and implements instruction buffer memory and data buffer memory, and adds peripherals such as FLASH, SRAM, and SDRAM. And, this paper designed custom instructions. Given the convolution operation frequently occurring in CNN, vector store instruction, vector load instruction, vector addition instruction, and convolution operation instruction are designed to accelerate the execution of the convolution process. The design has passed the simulation experiment. It can not only complete the general instructions but also run the custom instructions. The final simulation test verified the correctness of the design. © 2019 IEEE.

关键词： Convolution

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Image Segmentation Using Hardware Forest Classifiers

Image Segmentation Using Hardware Forest Classifiers

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21st Annual international IEEE symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Pittman, Neil Forin, Alessandro Criminisi, Antonio Shotton, Jamie Mahram, Atabak Microsoft Res Redmond WA 98052 USA Microsoft Res Cambridge England Boston Univ Boston MA 02215 USA

ISBN: (纸本)9780769549699;9781467360050

Image segmentation is the process of partitioning an image into segments or subsets of pixels for purposes of further analysis, such as separating the interesting objects in the foreground from the un-interesting objects in the background. In many image processing applications, the process requires a sequence of computational steps on a per pixel basis, thereby binding the performance to the size and resolution of the image. As applications require greater resolution and larger images the computational resources of this step can quickly exceed those of available CPUs, especially in the power and thermal constrained areas of consumer electronics and mobile. In this work, we use a hardware tree-based classifier to solve the image segmentation problem. The application is background removal (BGR) from depth-maps obtained from the Microsoft Kinect sensor. After the image is segmented, subsequent steps then classify the objects in the scene. The approach is flexible: to address different application domains we only need to change the trees used by the classifiers. We describe two distinct approaches and evaluate their performance using the commercial-grade testing environment used for the Microsoft Xbox gaming console.

关键词： NUI FPGA Smart Cameras computer Vision Kinect

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