Fully autonomous driving is one if not the killer application for the upcoming decade of real-time systems. However, in the presence of increasingly sophisticated attacks by highly skilled and well equipped adversaria...
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ISBN:
(纸本)9781538658475
Fully autonomous driving is one if not the killer application for the upcoming decade of real-time systems. However, in the presence of increasingly sophisticated attacks by highly skilled and well equipped adversarial teams, autonomous driving must not only guarantee timeliness and hence safety. It must also consider the dependability of the software concerning these properties while the system is facing attacks. For distributed systems, fault-and-intrusion tolerance toolboxes already offer a few solutions to tolerate partial compromise of the system behind a majority of healthy components operating in consensus. In this paper, we present a concept of an intrusion-tolerant architecture for autonomous driving. In such a scenario, predictability and recovery challenges arise from the inclusion of increasingly more complex software on increasingly less predictable hardware. We highlight how an intrusion tolerant design can help solve these issues by allowing timeliness to emerge from a majority of complex components being fast enough, often enough while preserving safety under attack through pre-computed fail safes.
Multiprocessor system-on-chip such as embedded GPUs are becoming very popular in safety-critical applications, such as autonomous and semi-autonomous vehicles. However, these devices can suffer from the effects of sof...
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ISBN:
(数字)9781665488020
ISBN:
(纸本)9781665488020
Multiprocessor system-on-chip such as embedded GPUs are becoming very popular in safety-critical applications, such as autonomous and semi-autonomous vehicles. However, these devices can suffer from the effects of soft-errors, such as those produced by radiation effects. These effects are able to generate unpredictable misbehaviors. Fault tolerance oriented to multi-threaded software introduces severe performance degradations due to the redundancy, voting and correction threads operations. In this paper, we propose a new fault injection environment for NVIDIA GPGPU devices and a fault tolerance approach based on error detection and correction threads executed during data transfer operations on embedded GPUs. The fault injection environment is capable of automatically injecting faults into the instructions at SASS level by instrumenting the CUDA binary executable file. The mitigation approach is based on concurrent error detection threads running simultaneously with the memory stream device to host data transfer operations. With several benchmark applications, we evaluate the impact of soft-errors classifying Silent Data Corruption, Detection, Unrecoverable Error and Hang. Finally, the proposed mitigation approach has been validated by soft-error fault injection campaigns on an NVIDIA Pascal architecture GPU controlled by Quad-Core A57 ARM processor (JETSON TX2) demonstrating an advantage of more than 37% with respect to state of the art solution.
This paper presents the system architecture of the @neurIst project, which aims at supporting the research and treatment of cerebral aneurysms by bringing together heterogeneous data, computing and complex processing ...
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ISBN:
(纸本)9780769531656
This paper presents the system architecture of the @neurIst project, which aims at supporting the research and treatment of cerebral aneurysms by bringing together heterogeneous data, computing and complex processing services. The architecture is generic enough to adapt it to the treatment of other diseases beyond cerebral aneurysms. The paper describes the generic requirements of the system and presents the architecture, applications and middle-ware technologies used to realise the system and highlights the innovations in @neurIst.
This conference proceedings contains 60 papers. The following topics are dealt with: failures in real systems;test generation;system architecture;signature analysis;fault analysis and self checking;hypercube architect...
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ISBN:
(纸本)0818621508
This conference proceedings contains 60 papers. The following topics are dealt with: failures in real systems;test generation;system architecture;signature analysis;fault analysis and self checking;hypercube architectures;system diagnosis;software techniques;multiprocessor systems;control flow monitoring;distributed systems;error control and coding;experimental software validation;reconfiguration strategies;and real-time systems.
An important type of communication in grid and distributed computing environments is bulk data transfer. GridFTP has emerged as a de facto standard for secure, reliable, high-performance data transfer across resources...
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This work presents a customizable software framework that supports the analysis of correlations between genotype and phenotype within an integrated database in the context of metabolic disorders. The basis for the exa...
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ISBN:
(纸本)9780769531656
This work presents a customizable software framework that supports the analysis of correlations between genotype and phenotype within an integrated database in the context of metabolic disorders. The basis for the examination of relations between genotypes and phenotypes is the information from different life science data sources, merged by a mediator-based system in an integrated database. A graphical web interface enables user queries to the integrated data and the trace of connections to corresponding data objects in different information domains. As a result of this work, a web-based prototype of the system is presented. In the context of an example scenario, the framework was used to integrate clinical and molecular biology data for rare metabolic diseases. The framework offers software tools to integrate almost any life science data and to prepare the content for user-specific presentation.
Multithread programming tools become popular for exploitation of highperformance processing with the dissemination of multicore processors. In this context, it is also popular to exploit compiler optimization to impr...
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ISBN:
(纸本)9781538648193
Multithread programming tools become popular for exploitation of highperformance processing with the dissemination of multicore processors. In this context, it is also popular to exploit compiler optimization to improve the performance at execution time. In this work, we evaluate the performance achieved by the use of flags -O1, -O2, and -O3 of two C compilers (GCC and ICC) associated with five different APIs: Pthreads, C++11, OpenMP, Cilk Plus, and TBB. The experiments were performed on two distinct but compatible architectures (Intel Xeon and AMD Opteron). In our experiments, the use of optimization improves the performance independently from the API. We observe that the application scheduling performed by the programming interfaces providing an application level scheduler has more impact on the final performance than the optimizations.
In this work, we propose an application composition system (ACS) that allows design-time exploration and automatic run-time optimizations so that we relieve application programmers and compiler writers from the challe...
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Integer compression techniques can generally be classified as bit-wise and byte-wise approaches. Though at the cost of a larger processing time, bit-wise techniques typically result in a better compression ratio. The ...
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ISBN:
(纸本)9780769549699;9781467360050
Integer compression techniques can generally be classified as bit-wise and byte-wise approaches. Though at the cost of a larger processing time, bit-wise techniques typically result in a better compression ratio. The Golomb-Rice (GR) method is a bit-wise lossless technique applied to the compression of images, audio files and lists of inverted indices. However, since GR is a serial algorithm, decompression is regarded as a very slow process;to the best of our knowledge, all existing software and hardware native (non-modified) GR decoding engines operate bit-serially on the encoded stream. In this paper, we present (1) the first no-stall hardware architecture, capable of decompressing streams of integers compressed using the GR method, at a rate of several bytes (multiple integers) per hardware cycle;(2) a novel GR decoder based on the latter architecture is further detailed, operating at a peak rate of one integer per cycle. A thorough design space exploration study on the resulting resource utilization and throughput of the aforementioned approaches is presented. Furthermore, a performancestudy is provided, comparing software approaches to implementations of the novel hardware decoders. While occupying 10% of a Xilinx V6LX240T FPGA, the no-stall architecture core achieves a sustained throughput of over 7 Gbps.
A new high-performancecomputerarchitecture aimed at the computationally intensive applications of biomedical volume data processing is proposed. It features reconfigurable computing elements and a novel memory archi...
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A new high-performancecomputerarchitecture aimed at the computationally intensive applications of biomedical volume data processing is proposed. It features reconfigurable computing elements and a novel memory architecture.
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