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检索条件"任意字段=21st International Symposium on Computer Architecture and High Performance Computing"

共 1770 条记录，以下是11-20 订阅

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Hydra: Scale-out FHE Accelerator architecture for Secure Deep Learning on FPGA 31

Hydra: Scale-out FHE Accelerator Architecture for Secure Dee...

引用

31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Yang, Yinghao Xu, Xicheng Zhang, Haibin Song, Jie Tang, Xin Lu, Hang Li, Xiaowei Institute of Computing Technology CAS State Key Laboratory of Processors Beijing China University of Chinese Academy of Sciences Beijing China Zhongguancun Laboratory Beijing China

ISBN: (纸本)9798331506476

Deep learning, including Convolutional Neural Network (CNN) and Large Language Model (LLM), under Fully Homomorphic Encryption (FHE) is very computationally intensive because of the burdensome computations like ciphertext convolution and matrix multiplication, non-linear layers, and bootstrapping. Existing FHE accelerators focus on the high throughput computational units, stacking parallelized clusters to maximize ciphertext inference performance. Nevertheless, this design philosophy cannot leverage the substantial parallelism at the application level and is not scalable for further performance enhancement by simply adding additional compute nodes to cope with the ever-increasing model sizes in the future. In this paper, we propose the high-performance FHE acceleration architecture in a 'scale-out' manner for secure deep learning, termed as Hydra. It supports the multi-server scaling and arbitrary computational nodes theoretically, each handling a portion of the deep learning model governed by the central scheduling mechanism on the host server. Hydra exhibits excellent scalability and delivers outstanding performance across a range of compute resource sizes. We highlight the following results: (1) up to 74 × and 160 × speedup over the SOTA single card accelerator Poseidon and FAB;(2) outperforms 8-card FAB-2 by 12 × to 21 × for FHE-based CNNs and LLMs;(3) outperforms SOTA ASIC accelerators, CraterLake and SHARP, by 8.1 × and 2.5 × for LLM OPT-6.7B, and achieves comparable or superior energy efficiency under the same chip technology. © 2025 IEEE.

关键词： Convolutional neural networks

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Multi-Dimensional Vector ISA Extension for Mobile In-Cache computing 31

Multi-Dimensional Vector ISA Extension for Mobile In-Cache C...

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31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Khadem, Alireza Fujiki, Daichi Chen, Hilbert Gu, Yufeng Talati, Nishil Mahlke, Scott Das, Reetuparna University of Michigan United States Institute of Science Tokyo Japan

ISBN: (纸本)9798331506476

In-cache computing technology transforms existing caches into long-vector compute units and offers low-cost alternatives to building expensive vector engines for mobile CPUs. Unfortunately, existing long-vector Instruction Set architecture (ISA) extensions, such as RISC-V Vector Extension (RVV) and Arm Scalable Vector Extension (SVE), provide only onedimensional strided and random memory accesses. While this is sufficient for typical vector engines, it fails to effectively utilize the large Single Instruction, Multiple Data (SIMD) widths of incache vector engines. This is because mobile data-parallel kernels expose limited parallelism across a single dimension. Based on our analysis of mobile vector kernels, we introduce a long-vector Multi-dimensional Vector ISA Extension (MVE) for mobile in-cache computing. MVE achieves high SIMD resource utilization and enables flexible programming by abstracting cache geometry and data layout. The proposed ISA features multi-dimensional strided and random memory accesses and efficient dimension-level masked execution to encode parallelism across multiple dimensions. Using a wide range of data-parallel mobile workloads, we demonstrate that MVE offers significant performance and energy reduction benefits of 2.9 × and 8.8 ×, on average, compared to the SIMD units of a commercial mobile processor, at an area overhead of 3.6%. © 2025 IEEE.

关键词： Vectors

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AccelES: Accelerating Top-K SpMV for Embedding Similarity via Low-bit Pruning 31

AccelES: Accelerating Top-K SpMV for Embedding Similarity vi...

引用

31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Zhai, Jiaqi Shi, Xuanhua Huang, Kaiyi Ye, Chencheng Hu, Weifang He, Bingsheng Jin, Hai Huazhong University of Science and Technology National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Wuhan430074 China National University of Singapore School of Computing 119077 Singapore

ISBN: (纸本)9798331506476

In the realm of recommendation systems, achieving real-time performance in embedding similarity tasks is often hindered by the limitations of traditional Top-K sparse matrix-vector multiplication (SpMV) methods, which suffer from high latency due to inefficient memory access patterns. This paper identifies these critical gaps and introduces AccelES, a novel approach that significantly enhances the efficiency of Top-K SpMV. Our method employs a two-stage calculation scheme: the first stage utilizes a compact, low-bit dataset to quickly identify the most relevant entries, while the second stage performs full-precision calculations solely on this pruned subset, thereby minimizing computational overhead. Furthermore, AccelES incorporates innovative matrix representations, Ultra-CSR and Random-CSR, which optimize memory bandwidth utilization. Experimental results demonstrate that AccelES accelerates performance, surpassing state-of-the-art FPGA, GPU, and CPU solutions by factors of 3.4×, 2.5×, and 153.3×, respectively, under controlled conditions. These advancements not only enhance processing speed but also significantly improve real-time performance in recommendation systems, establishing AccelES as a pivotal contribution to the field of Top-K sparse matrix-vector multiplication. © 2025 IEEE.

关键词： Embeddings

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IoT-Based Service Allocation in Edge computing Using Game Theory 21st

IoT-Based Service Allocation in Edge Computing Using Game Th...

引用

21st international Conference on Distributed computing and Intelligent Technology

作者： Agrawal, Kushagra Goktas, Polat Sahaol, Biswajit Swain, Sujata Bandyopadhyay, Anjan KIT Deemed Be Univ Sch Comp Engn Bhubaneswar India Univ Coll Dublin Sch Comp Sci Dublin Ireland

ISBN: (纸本)9783031814037;9783031814044

The rapid growth of the Internet of Things (IoT) has created a pressing need for efficient service allocation methods to manage the multitude of connected devices. Edge computing has become essential to fulfill the low-latency and high-bandwidth demands of IoT applications. This paper investigates the use of game theory as a framework for optimizing service allocation in edge computing environments. By treating the interactions between IoT devices and edge servers as a strategic game, we propose strategies to achieve optimal allocation and resource utilization. Our approach tackles key challenges such as minimizing latency, improving energy efficiency, and balancing load. Experimental results indicate that game-theoretic methods greatly improve the performance and scalability of IoT systems in edge computing, positioning them a promising solution for future applications.

关键词： Edge computing Internet of Things (IoT) Game Theory

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An Analysis of Different Text Representation Schemes for an Immune Clustering Algorithm 21st

An Analysis of Different Text Representation Schemes for an ...

引用

21st international symposium on Distributed computing and Artificial Intelligence

作者： Ferraria, Matheus A. Balbi, Pedro P. de Castro, Leandro N. Univ Presbiteriana Mackenzie FCI PPGEEC Programa Pos Grad Engn Eletrica & Comp Sao Paulo SP Brazil State Univ Campinas Unicamp Sch Technol Grad Program Technol Sao Paulo SP Brazil Florida Gulf Coast Univ Human Ctr Artificial Intelligence & Nat Comp Res Ft Myers FL 33965 USA

ISBN: (纸本)9783031820724;9783031820731

This research investigates the challenges and effectiveness of various text representation methods (standard vector, grammar-based, and distributed), when applied to clustering short texts. The study explores Bag-of-Words for standard vector, Linguistic Inquiry and Word Count (LIWC), Part-of-Speech Tagging (POS-Tagging), and the Medical Research Council Psycholinguistic Database (MRC) for grammar-based, and Word2Vec, fastText, Doc2Vec, and SentenceBERT for distributed representations. Utilizing the aiNet bio-inspired clustering algorithm, the results reveal surprising findings, with grammar-based representations demonstrating competitive performance despite their simplicity, while standard vectors exhibit known challenges like high dimensionality. The study contributes insights into the properties of different text representations, providing a foundation for optimizing their application in clustering tasks with short and informal texts.

关键词： Clustering Information retrieval Natural computing NLP Text Mining

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NVMePass: A Lightweight, high-performance and Scalable NVMe Virtualization architecture with I/O Queues Passthrough 31

NVMePass: A Lightweight, High-performance and Scalable NVMe ...

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31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Chen, Yiquan Jin, Zhen Wang, Yijing Chen, Yi Xu, Jiexiong Yu, Hao Chen, Jinlong Lin, Wenhai Fang, Kanghua Zhang, Keyao Wei, Chengkun Liu, Qiang Xie, Yuan Chen, Wenzhi Zhejiang University China Alibaba Group China University of Michigan United States HKUST Hong Kong

ISBN: (纸本)9798331506476

Most data-intensive applications currently run on NVMe storage, and virtualization is essential in cloud computing. Existing NVMe virtualization technologies include software-based and hardware-assisted. Virtio suffers from severe performance degradation, and polling-based solutions consume too many valuable CPU resources. Hardware-assisted solutions provide high performance and no CPU usage but have the challenges of developing dedicated *** this paper, we propose NVMePass, a novel software-hardware co-design NVMe passthrough virtualization architecture designed to achieve high performance and no CPU overhead while maintaining high scalability. The key ideas of NVMePass are NVMe I/O queues passthrough for VMs and a mechanism to ensure security. The NVMePass supports DMA and interrupts remapping for VMs without hypervisor involvement, eliminating virtualization overhead and providing near-native performance. Isolation is achieved by I/O queues and logical block address resources exclusively allocated to VMs. We propose NVMe Resource Domain (NRD) and implement it in the NVMe controller to intercept illegal I/O requests. Thus, isolation and security are fully achieved. Results from our experiments show that NVMePass can provide comparable performance to VFIO, with an IOPS of {1 0 0. 1% - 1 0 0. 5%} of VFIO. Furthermore, compared to SPDK-Vhost, NVMePass achieves {4 0. 0%} lower latency when running 150 VMs, and NVMePass has an improvement of {6 8. 0%} OPS performance in a real-world application when running 100 VMs. © 2025 IEEE.

关键词： Software design

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HSMU-SpGEMM: Achieving high Shared Memory Utilization for Parallel Sparse General Matrix-Matrix Multiplication on Modern GPUs 31

HSMU-SpGEMM: Achieving High Shared Memory Utilization for Pa...

引用

31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Wu, Min Luo, Huizhang Li, Fenfang Zhang, Yiran Tang, Zhuo Li, Kenli Zhang, Jeff Liu, Chubo Hunan University Changsha China Arizona State University Tempe United States

ISBN: (纸本)9798331506476

Sparse general matrix-matrix multiplication (SpGEMM) is a core primitive for numerous scientific applications. Traditional hash-based approaches fail to strike a balance between reducing hash collisions and efficiently utilizing fast shared memory, which significantly undermines the performance of executing SpGEMM on GPUs. To address this issue, this paper introduces a novel accumulator design that achieves high shared memory utilization on modern GPUs. For the proposed high shared memory utilization algorithm, i.e., HSMU-SpGEMM1, we further optimize different symbolic stages. Our evaluations with four state-of-the-art hash-based SpGEMM libraries (Nsparse, spECK, OpSparse, and NVIDIA's cuSPARSE) on three NVIDIA GPUs (Ampere, Ada Lovelace, Turing) demonstrate significant performance benefits from HSMU-SpGEMM.1HSMU-SpGEMM is available at https://***/wuminqaq/HSMUSpGEMM © 2025 IEEE.

关键词： Graphics processing unit

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Proceedings - 2024 IEEE 36th international symposium on computer architecture and high-performance computing, SBAC-PAD 2024

Proceedings - 2024 IEEE 36th International Symposium on Comp...

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36th IEEE international symposium on computer architecture and high-performance computing, SBAC-PAD 2024

ISBN: (纸本)9798350356168

The proceedings contain 21 papers. The topics discussed include: S-Clflush: securing against flush-based cache timing side-channel attacks;TangramFP: energy-efficient, bit-parallel, multiply-accumulate for deep neural networks;analyzing HPC monitoring data with a view towards efficient resource utilization;DYAD: locality-aware data management for accelerating deep learning training;IDS-DEEP: a strategy for selecting the best IDS for drones with heterogeneous embedded platforms;memory sandbox: a versatile tool for analyzing and optimizing HBM performance in FPGA;DeVAS: decoupled virtual address spaces;towards performance portability of an oil and gas application on heterogeneous architectures;and JANUS: a simple and efficient speculative defense using reinforcement learning.

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OASIS: Object-Aware Page Management for Multi-GPU Systems 31

OASIS: Object-Aware Page Management for Multi-GPU Systems

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31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Wang, Yueqi Li, Bingyao Ziad, Mohamed Tarek Ibn Eeckhout, Lieven Yang, Jun Jaleel, Aamer Tang, Xulong University of Pittsburgh United States NVIDIA United States Ghent University Belgium

ISBN: (纸本)9798331506476

The ever-growing need for high-performance computing has driven the popularity of employing multi-GPU systems. Modern multi-GPU systems employ unified virtual memory (UVM) to manage page placement and migration. However, the page management in UVM is application object agnostic. In this paper, we characterize the page access behaviors in relation to the application objects, and reveal that the beneficial page management policy varies according to (i) the different data objects within the same application, and (ii) the different execution phases of the same object. This motivates the need for dynamic and proactive page management in multi-GPU systems. To this end, we propose OASIS, which dynamically identifies object patterns during the execution and proactively determines the appropriate page management policies for these objects at runtime. Experimental results show that OASIS improves the performance over uniformly adopting on-touch migration, access counter-based migration, and duplication by an average of {6 4%}, {3 5%}, and {4 2%}, respectively. Moreover, OASIS achieves a {1 2%} performance improvement over the state-of-the-art technique (i.e., GRIT) while having significantly lower design complexity. © 2025 IEEE.

关键词： computer graphics equipment

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Gemina: A Coordinated and high-performance Memory Deduplication Engine 31

Gemina: A Coordinated and High-Performance Memory Deduplicat...

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31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Zhang, Zhehua Wu, Suzhen You, Wenyan Du, Chunfeng Mao, Bo Xiamen University Xiamen Key Laboratory of Intelligent Storage and Computing School of Informatics Fujian Xiamen China

ISBN: (纸本)9798331506476

Memory deduplication is widely used to effectively reduce the memory footprint in operating systems, while huge pages are employed to enhance access performance by increasing TLB hit rates. Unfortunately, duplicate huge pages are very rare in memory, leading to most huge pages being split into base pages during deduplication, which degrades access performance by up to {4 3%}. Although asynchronous huge page promotion attempts to elevate multiple base pages to huge pages to maximize performance, deduplication disrupts the uniformity of page attributes, limiting the effectiveness of such promotions. To address this problem, we designed Gemina, a new memory deduplication scheme that coordinates huge page management. Gemina employs a fine-grained detector to distinguish pages, redundancy and hotness, a distributor to process pages conservatively and avoid frequent switches, and an adapter to organize memory for fast conversion. This approach balances the trade-off between performance and space efficiency in memory management. Experimental evaluations show that, compared to the naive KSM-based deduplication scheme, Gemina can achieve 96.1% of the memory savings of KSM while also improving memory access performance by {4 3. 1%} in random access. © 2025 IEEE.

关键词： Memory management

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