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检索条件"任意字段=21st International Symposium on Computer Architecture and High Performance Computing"

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Ad-hoc Lab computer Network Configuration using Remote Resources 21

Ad-hoc Lab Computer Network Configuration using Remote Resou...

引用

21st IEEE international symposium for Design and Technology in Electronic Packaging (SIITME)

作者： Balan, T. C. Robu, D. N. Sandu, F. Transilvania Univ Brasov Dept Elect & Comp Brasov Romania

ISBN: (纸本)9781509003327

For the university computer labs there is a real challenge for the fixed infrastructure to keep the pace with the increased demand for computational resources. The complexity of the computer architecture is given by the high number of complex software tools, the virtual machines, the different operating systems and the great range of different classes with laboratory lessons, especially for computer engineering students. One solution would be the use of private university-owned Cloud but not all universities can afford a modern thin-client solution. This paper presents an intermediate non-expensive step towards working with distributed resources for computer laboratories, a remote boot system, using Clonezilla and Diskless Remote Boot in Linux - DRBL, methods implemented and tested in a demo system.

关键词： Clonezilla DRBL Laboratory Network Educational Network Introduction

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An Allreduce Algorithm and Network Co-design for Large-Scale Training of Distributed Deep Learning 21

An Allreduce Algorithm and Network Co-design for Large-Scale...

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21st IEEE/ACM international symposium on Cluster, Cloud and Internet computing (CCGrid)

作者： Nguyen, Truong Thao Wahib, Mohamed AIST Tokyo Tech Real World Big Data Computat Open Meguro Ku 2-12-1 W8-92 Ookayama Tokyo 1528550 Japan RIKEN CCS Chuo Ku 7-1-26 Minatojima Minami Machi Kobe Hyogo 6500047 Japan

ISBN: (纸本)9781728195865

Distributed training of Deep Neural Networks (DNNs) on high-performance computing (HPC) systems is becoming increasingly common. HPC systems dedicated entirely or mainly to Deep Learning (DL) workloads are becoming a reality. The collective communication overhead for calculating the average of weight gradients, e.g., an Allreduce operations, is one of the main factors limiting the scaling of data parallelism training. Several active efforts across different layers of the training stack including the training algorithms, parallelism strategy, communication algorithms, and system design have been proposed to cope with this communication challenge when scaling distributed training of DNNs. However, even with those methods, communication still becomes a bottleneck with the steady increase in model sizes, e.g.,100-10,000s MB, and the number of compute nodes, e.g., 1,000-10,000s of GPUs. In this work, we investigate the benefits of co-design of Allreduce algorithms and the network system. We propose to replace the Fat-tree network topology with a variant of Distributed Loop Network topology that guarantees a fixed routing paths length between any pairs of computing nodes for the communication pattern of halving-doubling Allreduce algorithm. We also propose a technique to eliminate/mitigate the network contention.

关键词： Interconnection networks high performance computing (HPC) Distributed Deep Learning Allreduce

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DejaVu: Transparent user-level checkpointing, migration, and recovery for distributed systems

DejaVu: Transparent user-level checkpointing, migration, and...

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21st international Parallel and Distributed Processing symposium, IPDPS 2007

作者： Ruscio, Joseph F. Heffner, Michael A. Varadarajan, Srinidhi Computing Systems Research Laboratory Department of Computer Science Virginia Tech VA 24061 United States

ISBN: (纸本)1424409101

In this paper, we present a new fault tolerance system called DejaVu for transparent and automatic checkpointing, migration, and recovery of parallel and distributed applications. DejaVu provides a transparent parallel checkpointing and recovery mechanism that recovers from any combination of systems failures without any modification to parallel applications or the OS. It uses a new runtime mechanism for transparent incremental checkpointing that captures the least amount of state needed to maintain global consistency and provides a novel communication architecture that enables transparent migration of existing MPI codes, without source-code modifications. performance results from the production-ready implementation show less than 5% overhead in real-world parallel applications with large memory footprints. © 2007 IEEE.

关键词： Fault tolerant computer systems

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Latency-Optimized Networks for Clustering FPGAs

Latency-Optimized Networks for Clustering FPGAs

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21st Annual international IEEE symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Bunker, Trevor Swanson, steven Univ Calif San Diego San Diego CA 92103 USA

ISBN: (纸本)9780769549699;9781467360050

The data-intensive applications that will shape computing in the coming decades require scalable architectures that incorporate scalable data and compute resources and can support random requests to unstructured (e. g., logs) and semi-structured (e.g., large graph, XML) data sets. To explore the suitability of FPGAs for these computations, we are constructing an FPGA-based system with a memory capacity of 512 GB from a collection of 32 Virtex-5 FPGAs spread across 8 enclosures. This paper describes our work in exploring alternative interconnect technologies and network topologies for FPGA-based clusters. The diverse interconnects combine inter-enclosure high-speed serial links and wide, single-ended intra-enclosure on-board traces with network topologies that balance network diameter, network throughput, and FPGA resource usage. We discuss the architecture of high-radix routers in FPGAs that optimize for the asymmetry between the inter-and intra-enclosure links. We analyze the various interconnects that aim to efficiently utilize the prototype's total switching capacity of 2.43 Tb/s. The networks we present have aggregate throughputs up to 51.4 GB/s for random traffic, diameters as low as 845 nanoseconds, and consume less than 12% of the FPGAs' logic resources.

关键词： FPGA high-radix router low latency network high-speed serial data-intensive applications

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10-Gigabit iWARP Ethernet: Comparative performance analysis with InfiniBand and myrinet-10G

10-Gigabit iWARP Ethernet: Comparative performance analysis ...

引用

21st international Parallel and Distributed Processing symposium, IPDPS 2007

作者： Rashti, Mohammad J. Afsahi, Ahmad Department of Electrical and Computer Engineering Queen's University Kingston Ont. K7L 3N6 Canada

ISBN: (纸本)1424409101

iWARP is a set of standards enabling Remote Direct Memory Access (RDMA) over Ethernet. iWARP supporting RDMA and OS bypass, coupled with TCP/IP Offload Engines, can fully eliminate the host CPU involvement in an Ethernet environment. With the iWARP standard and the introduction of 10-Gigabit Ethernet, there is now an alternative path to the proprietary interconnects for high-performance computing, while maintaining compatibility with existing Ethernet infrastructure and protocols. Recently, NetEffect Inc. has introduced an iWARPenabled 10-Gigabit Ethernet Channel Adapter. In this paper we assess the potential of such an interconnect for high-performance computing by comparing its performance with two leading cluster interconnects, InfiniBand and Myrinet-10G. The results show that the NetEffect i WARP implementation achieves an unprecedented latency for Ethernet, and saturates 87% of the available bandwidth. It also scales better with multiple connections. At the MPI level, iWARP performs better than InfiniBand in queue usage and buffer re-use. © 2007 IEEE.

关键词： Ethernet

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The coast-to-coast seminar and remote mathematical collaboration

The coast-to-coast seminar and remote mathematical collabora...

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21st international symposium on high performance computing Systems and Applications, HPCS 2007

作者： Borwein, Jonathan M. Langstroth, David Macklem, Mason Wilson, Scott Jungic, Veselin Dalhousie University Faculty of Computing Science 6050 University Avenue Halifax NS Canada Simon Fraser University 8888 University Drive Burnaby BC Canada

We describe a shared Simon Fraser University (West-Grid) and Dalhousie (ACEnet) seminar series which is now two years old, and is gradually expanding to include other Canadian universities. More generally we discuss c... 详细信息

ISBN: (纸本)0769528139

关键词： computer supported cooperative work

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CRAC: A grid environment to solve scientific applications with asynchronous iterative algorithms

CRAC: A grid environment to solve scientific applications wi...

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21st international Parallel and Distributed Processing symposium, IPDPS 2007

作者： Couturier, Raphaël Domas, stéphane IUT de Belfort-Montbéliard Rue Engel Gros 90016 Belfort Cedex France

ISBN: (纸本)1424409101

This paper presents CRAC, an environment dedicated to design efficient asynchronous iterative algorithms for a grid architecture. Those algorithms are particularly suited for grid architecture since they naturally allow to overlap communications by computations. Each processor computes its iterations freely without any synchronization with its neighbors. All the characteristics of CRAC are described. A real application using four distant clusters, with a total of 120 processors, shows the interest of this environment and of asynchronous algorithms. © 2007 IEEE.

关键词： Grid computing

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C-MAP: Improving the effectiveness of mapping method for CGRA by reducing NoC congestion 21

C-MAP: Improving the effectiveness of mapping method for CGR...

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21st IEEE international Conference on high performance computing and Communications, 17th IEEE international Conference on Smart City and 5th IEEE international Conference on Data Science and Systems, HPCC/SmartCity/DSS 2019

作者： An, Shuqian Zhang, Mingzhe Ye, Xiaochun Wang, Da Zhang, Hao Fan, Dongrui Tang, Zhimin University of Chinese Academy of Sciences Beijing China State Key Laboratory of Computer Architecture ICT CAS Beijing China

ISBN: (纸本)9781728120584

The Coarse-Grained Reconfigurable architecture (CGRA) is considered as one of the most potential candidates for big data applications, which provides significant throughput improvement and high energy efficiency. Unlike the dynamic issue superscalar method in conventional processors, the CGRA architecture uses the static placement dynamic issue (SPDI) execution method in which the compiler decides how to map the instructions onto the distributed processing elements (PEs) and the PEs executes one instruction when the required data is ready. Since the dataflow of the program is determined in the logical view, an improper mapping of instructions may leads to more network congestion and hurts the performance. Furthermore, the exploration for most optimized mapping in CGRA is proved to a NPC problem and can hardly be achieved in limited time. In this paper, we propose a novel mapping algorithm named Congestion-MAP (C-MAP). C-Map improves the effectiveness of CGRA mapping in the perspective of reducing network congestion and enhancing the continuity of the data-flow. Furthermore, C-Map also accelerates the mapping optimization for CGRA by using network analysis method, which supports the fast comparison of mapping plan and parallel exploration. Additionally, with C-Map, we also analyze the impact of several key considerations in CGRA instruction mapping, such as NoC workload reduction and workload balance. The experiment result shows that C-Map improves the performance by 2.2× as a geometric mean. © 2019 IEEE.

关键词： Network-on-chip

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Speculative flow control for high-radix datacenter interconnect routers

Speculative flow control for high-radix datacenter interconn...

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21st international Parallel and Distributed Processing symposium, IPDPS 2007

作者： Minkenberg, Cyriel Gusat, Mitchell IBM Research GmbH Zurich Research Laboratory Säumerstrasse 4 8803 Rüschlikon Switzerland

ISBN: (纸本)1424409101

high-radix switches are desirable building blocks for large computer interconnection networksb because they are more suitable to convert chip I/O bandwidth into low latency and low cost than low-radix switches [10]. Unfortunately, most existing switch architectures do not scale well to a large number of ports. For example, the complexity of the buffered crossbar architecture scales quadratically with the number of ports. Compounded with support for long round-trip times and many virtual channels, the overall buffer requirements limit the feasibility of such switches to modest port counts. Compromising on the buffer sizing leads to a drastic increase in latency and reduction in throughput, as long as traditional credit flow control is employed at the link level. We propose a novel link-level flow control protocol that enables high-performance scalable routers based on the increasingly popular buffered crossbar architecture to scale to higher port counts without sacrificing performance. By combining credited and speculative transmission, this scheme achieves reliable delivery, low latency, and high throughput, even with crosspoint buffers that are significantly smaller than the round-trip time. ©2007 IEEE.

关键词： Routers

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Evaluating the performance of adaptive fault-tolerant routing algorithms for wormhole-switched mesh interconnect networks

Evaluating the performance of adaptive fault-tolerant routin...

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21st international Parallel and Distributed Processing symposium, IPDPS 2007

作者： Safaei, F. Khonsari, A. Fathy, M. Shantia, A.H. Ould-Khaoua, M. IPM School of Computer Science Tehran Iran Dept. of Electrical and Computer Engineering University of Tehran Tehran Iran Dept. of Computer Engineering Iran University of Science and Technology Tehran Iran Islamic Azad University North Branch Tehran Iran Dept. of Computing Science University of Glasgow United Kingdom

ISBN: (纸本)1424409101

One of the fundamental problems in parallel computing is how to efficiently perform routing in a faulty network each component of which fails with some probability. This paper presents a comparative performance study of ten prominent adaptive faulttolerant routing algorithms in wormhole-switched 2-D mesh interconnect networks. These networks carry a routing scheme suggested by Boppana and Chalasani 11] as an instance of a fault-tolerant method. The suggested scheme is widely used in the literature to achieve high adaptivity and support inter-processor communications in parallel computer systems due to its ability to preserve both communication performance and fault-tolerant demands in these networks. The performance measures studied are the throughput, average message latency and average usage of virtual channels per node. Results obtained through simulation suggest two classes of presented routing schemes as high performance candidate in most faulty networks. ©2007 IEEE.

关键词： Interconnection networks

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