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检索条件"任意字段=21st International Symposium on Computer Architecture and High Performance Computing"

共 1770 条记录，以下是21-30 订阅

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Proceedings - 2021 IEEE 33rd international symposium on computer architecture and high performance computing, SBAC-PAD 2021

Proceedings - 2021 IEEE 33rd International Symposium on Comp...

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33rd IEEE international symposium on computer architecture and high performance computing, SBAC-PAD 2021

ISBN: (纸本)9781665443012

The proceedings contain 21 papers. The topics discussed include: a low-power hardware accelerator for ORB feature extraction in self-driving cars;improving phased transactional memory via commit throughput and capacity estimation;design and evaluation of associative processing kernels;a task-based execution engine for distributed operating systems tailored to lightweight manycores with limited on-chip memory;sparsity-aware power gating for tensor cores;employing simulation to facilitate the design of dynamic binary translators;register flush-free runahead execution for modern vector processors;and shelf schedules for independent moldable tasks to minimize the energy consumption.

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architecture for Virtual Machine Resource Optimisation Using Explainable AI Algorithms 21st

Architecture for Virtual Machine Resource Optimisation Usin...

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21st international symposium on Distributed computing and Artificial Intelligence, DCAI 2024

作者： Villareal, Wilson Andrés Zabala González-Briones, Alfonso Carchi State Polytechnic University Tulcán040101 Ecuador BISITE Research Group Department of Computer Science and Automatics Faculty of Sciences University of Salamanca Salamanca Spain

ISBN: (纸本)9783031809453

The growing demand for online services and resource-intensive applications has led to the need to optimise the allocation of resources on virtual machines. Traditional methods based on manual allocation are insufficient in the face of the complexity and scale of modern virtualised environments. In this context, it is proposed to develop an architecture based on explainable artificial intelligence algorithms to dynamically optimise resource allocation in virtual machines. The objective is to improve the efficiency and performance of virtualised servers. It is expected to obtain a modular architecture that integrates different techniques of explainable artificial intelligence, contributing to the advancement of knowledge in the management of virtualised systems. The research will provide a solution for the optimisation of resources in virtual machines, improving efficiency and transparency in decision-making. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2025.

关键词： Adversarial machine learning

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Zebra: Efficient Redundant Array of Zoned Namespace SSDs Enabled by Zone Random Write Area (ZRWA) 31

Zebra: Efficient Redundant Array of Zoned Namespace SSDs Ena...

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31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Jiang, Tianyang Zhang, Guangyan Liao, Xiaojian Zhou, Yuqi Huawei Technologies Co. Ltd. China BNRist Tsinghua University Department of Computer Science and Technology China Beihang University China China University of Geosciences China

ISBN: (纸本)9798331506476

Zoned Namespace (ZNS) SSDs have emerged as a promising solution for eliminating device-level garbage collection and achieving predictable performance through the zone abstraction, which supports append-only writes. However, integrating ZNS SSDs into RAID configurations presents challenges, particularly concerning partial parity updates (PPUs) due to the no-overwrite property of ZNS SSDs. Existing solutions introduce dedicated metadata zones to manage PPUs, but these zones become performance bottlenecks, especially under high PPU *** this paper, we introduce Zebra, a novel architecture for ZNS RAID that leverages the Zone Random Write Area (ZRWA) feature of modern ZNS SSDs. Our key insight is that the SSD's write buffer (or ZRWA) in front of each zone is ideal for PPUs that exhibit a repeated sequential overwrite I/O pattern. By ensuring that the parity chunk fits within the ZRWA window, Zebra enables efficient PPUs within the ZRWA. Combined with a set of techniques, Zebra ensures both high performance and reliability. We evaluate Zebra on both large-zone and small-zone ZNS SSDs, two typical ZNS models. Our experiments with micro and application benchmarks show that Zebra improves the throughput by 1.1×-4.2× compared to RAIZN, a state-of-the-art ZNS RAID system. © 2025 IEEE.

关键词： Zinc Selenide

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DynamoLLM: Designing LLM Inference Clusters for performance and Energy Efficiency 31

DynamoLLM: Designing LLM Inference Clusters for Performance ...

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31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： stojkovic, Jovan Zhang, Chaojie Goiri, Inigo Torrellas, Josép Choukse, Esha University of Illinois at Urbana-Champaign United States Microsoft Azure Research - Systems United States

ISBN: (纸本)9798331506476

The rapid evolution and widespread adoption of generative large language models (LLMs) have made them a pivotal workload in various applications. Today, LLM inference clusters receive a large number of queries with strict Service Level Objectives (SLOs). To achieve the desired performance, these models execute on power-hungry GPUs, causing inference clusters to consume large amounts of energy and, consequently, result in substantial carbon emissions. Fortunately, we find that there is an opportunity to improve energy efficiency by exploiting the heterogeneity in inference compute properties and the fluctuations in inference workloads. However, the diversity and dynamicity of these environments create a large search space, where different system configurations (e.g., number of instances, model parallelism, and GPU frequency) translate into different energy-performance trade-offs. To address these challenges, we propose DynamoLLM, the first energy-management framework for LLM inference environments. DynamoLLM automatically and dynamically reconfigures the inference cluster to optimize for energy of LLM serving under the services' performance SLOs. We show that at a service level, on average, DynamoLLM conserves 52% of the energy and 38% of the operational carbon emissions, and reduces the cost to the customer by 61%, while meeting the latency SLOs. © 2025 IEEE.

关键词： computer graphics equipment

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CROSS: Compiler-Driven Optimization of Sparse DNNs Using Sparse/Dense Computation Kernels 31

CROSS: Compiler-Driven Optimization of Sparse DNNs Using Spa...

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31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Liu, Fangxin Huang, Shiyuan Yang, Ning Wang, Zongwu Li, Haomin Jiang, Li Shanghai Jiao Tong University Department of Computer Science and Engineering China Shanghai Qi Zhi Institute China

ISBN: (纸本)9798331506476

As deep learning models continue to grow larger and more complex, exploiting sparsity is becoming one of the most critical areas for enhancing efficiency and scalability. Several methods for leveraging sparsity have been proposed to more effectively balance the trade-off between compression ratio and accuracy. While these methods offer algorithmic advantages, they also introduce significant hardware overhead due to index-based encoding and decoding. In this paper, we propose CROSS, an end-to-end compilation optimization technique to achieve sparse DNN acceleration using GPU computation kernels. The key insight behind CROSS is to exploit parameter distribution locality and reconcile the 'sparse' DNN computation with the high-performance 'dense' computation kernels. Specifically, we perform an in-depth analysis of sparse operations in mainstream DNN computing frameworks. We then decompose the sparse workload into multiple components to create highly efficient, specialized operators with different sparsity levels. Additionally, we introduce a novel sparse graph translation technique to facilitate computation kernel processing of the sparse workload. The resulting CROSS framework can accommodate various sparsity patterns and optimization techniques, delivering an average 2.03 × speedup on inference latency compared to seven state-of-the-art solutions with smaller memory footprints across various models and datasets. © 2025 IEEE.

关键词： Program compilers

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DAPPER: A performance-Attack-Resilient Tracker for RowHammer Defense 31

DAPPER: A Performance-Attack-Resilient Tracker for RowHammer...

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31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Woo, Jeonghyun Nair, Prashant J. The University of British Columbia Department of Electrical and Computer Engineering Canada

ISBN: (纸本)9798331506476

RowHammer vulnerabilities pose a significant threat to modern DRAM-based systems, where rapid activation of DRAM rows can induce bit-flips in neighboring rows. To mitigate this, state-of-the-art host-side RowHammer mitigations typically rely on shared counters or tracking structures. While these optimizations benefit benign applications, they are vulnerable to performance Attacks (Perf-Attacks), where adversaries exploit shared structures to reduce DRAM bandwidth for co-running benign applications by increasing DRAM accesses for RowHammer counters or triggering repetitive refreshes required for the early reset of structures, significantly degrading performance. In this paper, we propose secure hashing mechanisms to thwart adversarial attempts to capture the mapping of shared structures. We propose DAPPER, a novel low-cost tracker resilient to Perf-Attacks even at ultra-low RowHammer thresholds. We first present a secure hashing template in the form of DAPPER-S. We then develop Dapper-H, an enhanced version of DapperS, incorporating double-hashing, novel reset strategies, and mitigative refresh techniques. Our security analysis demonstrates the effectiveness of DAPPER-H against both RowHammer and Perf-Attacks. Experiments with 57 workloads from SPEC2006, SPEC2017, TPC, Hadoop, MediaBench, and YCSB show that, even at an ultra-low RowHammer threshold of 500, DapperH incurs only a 0.9% slowdown in the presence of Perf-Attacks while using only 96 KB of SRAM per 32GB of DRAM memory. © 2025 IEEE.

关键词： static random access storage

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EXION: Exploiting Inter-and Intra-Iteration Output Sparsity for Diffusion Models 31

EXION: Exploiting Inter-and Intra-Iteration Output Sparsity ...

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31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Heo, Jaehoon Putra, Adiwena Yoon, Jieon Yune, Sungwoong Lee, Hangyeol Kim, Ji-Hoon Kim, Joo-Young KAIST Daejeon Korea Republic of

ISBN: (纸本)9798331506476

Over the past few years, diffusion models have emerged as novel solutions in AI industries, offering the capability to generate diverse, multi-modal outputs such as images, videos, and motions from input prompts (i.e., text). Despite their impressive capabilities, diffusion models face significant challenges in computing, including excessive latency and energy consumption due to the numerous iterations in model architecture. Although prior works specialized in transformer acceleration can be applied to diffusion models, given that transformers are key components, the problem of the iterative nature of diffusion models still needs to be *** this paper, we present EXION, the first software-hardware co-designed diffusion accelerator that solves the computation challenges of excessive iterations by exploiting the unique inter-and intra-iteration output sparsity in diffusion models. To this end, we propose two software-level optimizations in EXION. First, we introduce the FFN-Reuse algorithm that identifies and skips redundant computations in FFN layers across different iterations (i.e., inter-iteration sparsity). Second, we use a modified eager prediction method that employs two-step leading-one detection to accurately predict the attention score in diffusion models, skipping unnecessary computations within an iteration (i.e., intra-iteration sparsity). We also introduce a novel data compaction mechanism named ConMerge, which can enhance hardware utilization by condensing and merging large and sparse matrices into small and compact forms. Finally, EXION has a dedicated hardware architecture that supports the above sparsity-inducing algorithms, translating high output sparsity into improved energy efficiency and performance. To verify the feasibility of the EXION accelerator, we first demonstrate that it has no impact on accuracy in various types of multi-modal diffusion models, including text-to-motion, -audio, -image, and -video. We then instantiate EXION in b

关键词： computer software reusability

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CORDOBA: Carbon-Efficient Optimization Framework for computing Systems 31

CORDOBA: Carbon-Efficient Optimization Framework for Computi...

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31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Elgamal, Mariam Carmean, Doug Ansari, Elnaz Zed, Okay Peri, Ramesh Manne, Srilatha Gupta, Udit Wei, Gu-Yeon Brooks, David Hills, Gage Wu, Carole-Jean Harvard University United States Meta United States

ISBN: (纸本)9798331506476

The world's push toward an environmentally sustainable society is highly dependent on the semiconductor industry. Despite existing carbon modeling efforts to quantify carbon footprint of computing systems, optimizing carbon footprint in large design spaces-while also considering trade-offs in power, performance, and area-is especially challenging. To address this need, we present CORDOBA, a carbon-aware optimization framework that optimizes carbon efficiency. We quantify carbon efficiency using the total Carbon Delay Product metric (tCDP): the product of total carbon and application execution time. We justify why tCDP is an effective metric for quantifying carbon efficiency. We use CORDOBA to explore the large design space for carbonefficient specialized hardware, and identify distinct carbonefficient optimal designs across operational use (eliminating up to {9 8%} of the design space) despite uncertainty in carbon footprint parameters. We quantify opportunities to improve tCDP for real system case studies: (a) optimizing hardware provisioning from 8 to 4 cores in real system CPUs improves tCDP by 1.25 ×;and (b) leveraging advanced three-dimensional (3D) integration techniques (3D stacking of separately-fabricated logic and memory chips) improves tCDP by 6.9 × versus conventional systems. © 2025 IEEE.

关键词： carbon footprint carbon-aware optimization carbon-efficient computing metrics

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NeuVSA: A Unified and Efficient Accelerator for Neural Vector Search 31

NeuVSA: A Unified and Efficient Accelerator for Neural Vecto...

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31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Yuan, Ziming Dai, Lei Li, Wen Zhang, Jie Liang, Shengwen Wang, Ying Liu, Cheng Li, Huawei Li, Xiaowei Guo, Jiafeng Wang, Peng Chen, Renhai Zhang, Gong Shanxi University School of Computer and Information Technology China Peking University School of Computer Science China Institute of Computing Technology CAS State Key Lab of Processors China University of Chinese Academy of Sciences China Zhongguancun National Laboratory Beijing China Institute of Computing Technology CAS Key Lab of Network Data Science and Technology China Huawei Technologies Co. Ltd. China

ISBN: (纸本)9798331506476

Neural Vector Search (NVS) has exhibited superior search quality over traditional key-based strategies for information retrieval tasks. An effective NVS architecture requires high recall, low latency, and high throughput to enhance user experience and cost-efficiency. However, implementing NVS on existing neural network accelerators and vector search accelerators is sub-optimal due to the separation between the embedding stage and vector search stage at both algorithm and architecture levels. Fortunately, we unveil that Product Quantization (PQ) opens up an opportunity to break separation. However, existing PQ algorithms and accelerators still focus on either the embedding stage or the vector search stage, rather than both simultaneously. Simply combining existing solutions still follows the beaten track of separation and suffers from insufficient parallelization, frequent data access conflicts, and the absence of scheduling, thus failing to reach optimal recall, latency, and throughput. To this end, we propose a unified and efficient NVS accelerator dubbed NeuVSA based on algorithm and architecture co-design philosophy. Specifically, on the algorithm level, we propose a learned PQ-based unified NVS algorithm that consolidates two separate stages into the same computing and memory access paradigm. It integrates an end-to-end joint training strategy to learn the optimal codebook and index for enhanced recall and reduced PQ complexity, thus achieving smoother acceleration. On the architecture level, we customize a homogeneous NVS accelerator based on the unified NVS algorithm. Each sub-accelerator is optimized to exploit all parallelism exposed by unified NVS, incorporating a structured index assignment strategy and an elastic on-chip buffer to alleviate buffer conflicts for reduced latency. All sub-accelerators are coordinated using a hardware-aware scheduling strategy for boosted throughput. Experimental results show that the joint training strategy improves recall

关键词： Network embeddings

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GoPIM: GCN-Oriented Pipeline Optimization for PIM Accelerators 31

GoPIM: GCN-Oriented Pipeline Optimization for PIM Accelerato...

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31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Yang, Siling He, Shuibing Wang, Wenjiong Yin, Yanlong Wu, Tong Chen, Weijian Zhang, Xuechen Sun, Xian-He Feng, Dan The State Key Laboratory of Blockchain and Data Security Zhejiang University China Zhejiang Lab China Institute of Blockchain and Data Security China Zhejiang Key Laboratory of Big Data Intelligent Computing China Washington State University Vancouver United States Illinois Institute of Technology United States Huazhong University of Science and Technology China Wuhan National Laboratory for Optoelectronics China

ISBN: (纸本)9798331506476

Graph convolutional networks (GCNs) are popular for a variety of graph learning tasks. ReRAM-based processing-in-memory (PIM) accelerators are promising to expedite GCN training owing to their in-situ computing capability. However, existing accelerators can be severely underutilized even with pipelines, due to the oversight of the skewed execution times of various GCN stages and the ignorance of skewed degrees of graph vertices. In this work, we propose GOPIM, a GCN-oriented pipeline optimization for PIM accelerators to expedite GCN training. First, GOPIM proposes an ML-based scheme that allocates crossbar resources to the most needed stages to streamline the overall pipeline. Second, GOPIM utilizes a selective vertex updating technique that evenly distributes vertices on crossbars by interleaved mapping. These techniques collectively reduce the overall execution time without losing much accuracy. We also provide a practical architecture design for GOPIM. Our experimental results show that, GoPIM achieves up to 191 × speedup and 16.1 × energy saving, compared to the state-of-the-art work. © 2025 IEEE.

关键词： Graph neural networks

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