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检索条件"任意字段=21st International Symposium on Computer Architecture and High Performance Computing"

共 1760 条记录，以下是21-30 订阅

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HSMU-SpGEMM: Achieving high Shared Memory Utilization for Parallel Sparse General Matrix-Matrix Multiplication on Modern GPUs 31

HSMU-SpGEMM: Achieving High Shared Memory Utilization for Pa...

引用

31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Wu, Min Luo, Huizhang Li, Fenfang Zhang, Yiran Tang, Zhuo Li, Kenli Zhang, Jeff Liu, Chubo Hunan University Changsha China Arizona State University Tempe United States

ISBN: (纸本)9798331506476

Sparse general matrix-matrix multiplication (SpGEMM) is a core primitive for numerous scientific applications. Traditional hash-based approaches fail to strike a balance between reducing hash collisions and efficiently utilizing fast shared memory, which significantly undermines the performance of executing SpGEMM on GPUs. To address this issue, this paper introduces a novel accumulator design that achieves high shared memory utilization on modern GPUs. For the proposed high shared memory utilization algorithm, i.e., HSMU-SpGEMM1, we further optimize different symbolic stages. Our evaluations with four state-of-the-art hash-based SpGEMM libraries (Nsparse, spECK, OpSparse, and NVIDIA's cuSPARSE) on three NVIDIA GPUs (Ampere, Ada Lovelace, Turing) demonstrate significant performance benefits from HSMU-SpGEMM.1HSMU-SpGEMM is available at https://***/wuminqaq/HSMUSpGEMM © 2025 IEEE.

关键词： Graphics processing unit

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AccelES: Accelerating Top-K SpMV for Embedding Similarity via Low-bit Pruning 31

AccelES: Accelerating Top-K SpMV for Embedding Similarity vi...

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31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Zhai, Jiaqi Shi, Xuanhua Huang, Kaiyi Ye, Chencheng Hu, Weifang He, Bingsheng Jin, Hai Huazhong University of Science and Technology National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Wuhan430074 China National University of Singapore School of Computing 119077 Singapore

ISBN: (纸本)9798331506476

In the realm of recommendation systems, achieving real-time performance in embedding similarity tasks is often hindered by the limitations of traditional Top-K sparse matrix-vector multiplication (SpMV) methods, which suffer from high latency due to inefficient memory access patterns. This paper identifies these critical gaps and introduces AccelES, a novel approach that significantly enhances the efficiency of Top-K SpMV. Our method employs a two-stage calculation scheme: the first stage utilizes a compact, low-bit dataset to quickly identify the most relevant entries, while the second stage performs full-precision calculations solely on this pruned subset, thereby minimizing computational overhead. Furthermore, AccelES incorporates innovative matrix representations, Ultra-CSR and Random-CSR, which optimize memory bandwidth utilization. Experimental results demonstrate that AccelES accelerates performance, surpassing state-of-the-art FPGA, GPU, and CPU solutions by factors of 3.4×, 2.5×, and 153.3×, respectively, under controlled conditions. These advancements not only enhance processing speed but also significantly improve real-time performance in recommendation systems, establishing AccelES as a pivotal contribution to the field of Top-K sparse matrix-vector multiplication. © 2025 IEEE.

关键词： Embeddings

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IoT-Based Service Allocation in Edge computing Using Game Theory 21st

IoT-Based Service Allocation in Edge Computing Using Game Th...

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21st international Conference on Distributed computing and Intelligent Technology

作者： Agrawal, Kushagra Goktas, Polat Sahaol, Biswajit Swain, Sujata Bandyopadhyay, Anjan KIT Deemed Be Univ Sch Comp Engn Bhubaneswar India Univ Coll Dublin Sch Comp Sci Dublin Ireland

ISBN: (纸本)9783031814037;9783031814044

The rapid growth of the Internet of Things (IoT) has created a pressing need for efficient service allocation methods to manage the multitude of connected devices. Edge computing has become essential to fulfill the low-latency and high-bandwidth demands of IoT applications. This paper investigates the use of game theory as a framework for optimizing service allocation in edge computing environments. By treating the interactions between IoT devices and edge servers as a strategic game, we propose strategies to achieve optimal allocation and resource utilization. Our approach tackles key challenges such as minimizing latency, improving energy efficiency, and balancing load. Experimental results indicate that game-theoretic methods greatly improve the performance and scalability of IoT systems in edge computing, positioning them a promising solution for future applications.

关键词： Edge computing Internet of Things (IoT) Game Theory

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OASIS: Object-Aware Page Management for Multi-GPU Systems 31

OASIS: Object-Aware Page Management for Multi-GPU Systems

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31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Wang, Yueqi Li, Bingyao Ziad, Mohamed Tarek Ibn Eeckhout, Lieven Yang, Jun Jaleel, Aamer Tang, Xulong University of Pittsburgh United States NVIDIA United States Ghent University Belgium

ISBN: (纸本)9798331506476

The ever-growing need for high-performance computing has driven the popularity of employing multi-GPU systems. Modern multi-GPU systems employ unified virtual memory (UVM) to manage page placement and migration. However, the page management in UVM is application object agnostic. In this paper, we characterize the page access behaviors in relation to the application objects, and reveal that the beneficial page management policy varies according to (i) the different data objects within the same application, and (ii) the different execution phases of the same object. This motivates the need for dynamic and proactive page management in multi-GPU systems. To this end, we propose OASIS, which dynamically identifies object patterns during the execution and proactively determines the appropriate page management policies for these objects at runtime. Experimental results show that OASIS improves the performance over uniformly adopting on-touch migration, access counter-based migration, and duplication by an average of {6 4%}, {3 5%}, and {4 2%}, respectively. Moreover, OASIS achieves a {1 2%} performance improvement over the state-of-the-art technique (i.e., GRIT) while having significantly lower design complexity. © 2025 IEEE.

关键词： computer graphics equipment

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Gemina: A Coordinated and high-performance Memory Deduplication Engine 31

Gemina: A Coordinated and High-Performance Memory Deduplicat...

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31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Zhang, Zhehua Wu, Suzhen You, Wenyan Du, Chunfeng Mao, Bo Xiamen University Xiamen Key Laboratory of Intelligent Storage and Computing School of Informatics Fujian Xiamen China

ISBN: (纸本)9798331506476

Memory deduplication is widely used to effectively reduce the memory footprint in operating systems, while huge pages are employed to enhance access performance by increasing TLB hit rates. Unfortunately, duplicate huge pages are very rare in memory, leading to most huge pages being split into base pages during deduplication, which degrades access performance by up to {4 3%}. Although asynchronous huge page promotion attempts to elevate multiple base pages to huge pages to maximize performance, deduplication disrupts the uniformity of page attributes, limiting the effectiveness of such promotions. To address this problem, we designed Gemina, a new memory deduplication scheme that coordinates huge page management. Gemina employs a fine-grained detector to distinguish pages, redundancy and hotness, a distributor to process pages conservatively and avoid frequent switches, and an adapter to organize memory for fast conversion. This approach balances the trade-off between performance and space efficiency in memory management. Experimental evaluations show that, compared to the naive KSM-based deduplication scheme, Gemina can achieve 96.1% of the memory savings of KSM while also improving memory access performance by {4 3. 1%} in random access. © 2025 IEEE.

关键词： Memory management

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Evaluation Model and performance Analysis of NIC Aggregations in Containerized Private Clouds 35

Evaluation Model and Performance Analysis of NIC Aggregation...

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35th IEEE international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Maliszewski, Anderson M. Griebler, Dalvan Roloff, Eduardo Righi, Rodrigo da Rosa Navaux, Philippe O. A. Fed Univ Rio Grande Sul UFRGS Informat Inst Porto Alegre RS Brazil Tres de Maio Fac SETREM Lab Adv Res Cloud Comp LARCC Tres De Maio Brazil Pontifical Catholica Univ Rio Grande Sul PUCRS Sch Technol Porto Alegre RS Brazil Univ Vale Rio Sinos UNISINOS Software Innovat Lab SoftwareLab Sao Leopoldo Brazil

ISBN: (纸本)9798350381603

The availability of computational resources changed significantly due to cloud computing. In addition, we have witnessed efforts to execute high-performance computing (HPC) applications in the cloud attracted by the advantages of cost savings and scalable/elastic resource allocation. Allocating more powerful hardware and exclusivity allocating resources such as memory, storage, and CPU can improve performance in the cloud. For network interconnection, significant noise, and other inferences are generated by several simultaneous instances (multitenants) communicating using the same network. As increasing the network bandwidth may be an alternative, we designed an evaluation model, and performance analysis of NIC aggregation approaches in containerized private clouds. The experiments using NAS Parallel Benchmarks revealed that NIC aggregation approach outperforms the baseline up to similar to 98% of the executions with applications characterized by intensive network use. Also, the Balance Round-Robin aggregation mode performed better than the 802.3ad aggregation mode in most assessments.

关键词： Cloud computing Private Cloud high performance computing Network performance NIC Aggregation performance Analysis

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NVMePass: A Lightweight, high-performance and Scalable NVMe Virtualization architecture with I/O Queues Passthrough 31

NVMePass: A Lightweight, High-performance and Scalable NVMe ...

引用

31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Chen, Yiquan Jin, Zhen Wang, Yijing Chen, Yi Xu, Jiexiong Yu, Hao Chen, Jinlong Lin, Wenhai Fang, Kanghua Zhang, Keyao Wei, Chengkun Liu, Qiang Xie, Yuan Chen, Wenzhi Zhejiang University China Alibaba Group China University of Michigan United States HKUST Hong Kong

ISBN: (纸本)9798331506476

Most data-intensive applications currently run on NVMe storage, and virtualization is essential in cloud computing. Existing NVMe virtualization technologies include software-based and hardware-assisted. Virtio suffers from severe performance degradation, and polling-based solutions consume too many valuable CPU resources. Hardware-assisted solutions provide high performance and no CPU usage but have the challenges of developing dedicated *** this paper, we propose NVMePass, a novel software-hardware co-design NVMe passthrough virtualization architecture designed to achieve high performance and no CPU overhead while maintaining high scalability. The key ideas of NVMePass are NVMe I/O queues passthrough for VMs and a mechanism to ensure security. The NVMePass supports DMA and interrupts remapping for VMs without hypervisor involvement, eliminating virtualization overhead and providing near-native performance. Isolation is achieved by I/O queues and logical block address resources exclusively allocated to VMs. We propose NVMe Resource Domain (NRD) and implement it in the NVMe controller to intercept illegal I/O requests. Thus, isolation and security are fully achieved. Results from our experiments show that NVMePass can provide comparable performance to VFIO, with an IOPS of {1 0 0. 1% - 1 0 0. 5%} of VFIO. Furthermore, compared to SPDK-Vhost, NVMePass achieves {4 0. 0%} lower latency when running 150 VMs, and NVMePass has an improvement of {6 8. 0%} OPS performance in a real-world application when running 100 VMs. © 2025 IEEE.

关键词： Software design

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computer architecture and Chip Design for DIKWP Artificial Consciousness 25

Computer Architecture and Chip Design for DIKWP Artificial C...

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25th IEEE international Conferences on high performance computing and Communications, 9th international Conference on Data Science and Systems, 21st IEEE international Conference on Smart City and 9th IEEE international Conference on Dependability in Sensor, Cloud and Big Data Systems and Applications, HPCC/DSS/SmartCity/DependSys 2023

作者： Wu, Kunguang Duan, Yucong Chen, Liang Li, Yingbo Qi, Qi School of Computer Science and Technology Hainan University Dikwp Research Group China Hainan Meteorological Service Center Haikou China

ISBN: (纸本)9798350330014

Artificial intelligence systems are associated with inherent risks, such as uncontrollability and lack of interpretability. To address these risks, we need to develop artificial intelligence systems that are interpretable, trustworthy, responsible, and thinking and behavior consistent, which we refer to as artificial consciousness (AC) systems. Consequently, we propose and define the concepts and implementation of a computer architecture, chips, runtime environment, and the DIKWP language. Furthermore, we have overcome the limitations of traditional programming languages, computer architectures, and software-hardware implementations when creating AC systems. Our proposed software and hardware integration platform will make it easier to build and operate AC software systems based on DIKWP theories. © 2023 IEEE.

关键词： computer architecture

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CereSZ: Enabling and Scaling Error-bounded Lossy Compression on Cerebras CS-2 24

CereSZ: Enabling and Scaling Error-bounded Lossy Compression...

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33rd international symposium on high-performance Parallel and Distributed computing (HPDC)

作者： Song, Shihui Huang, Yafan Jiang, Peng Yu, Xiaodong Zheng, Weijian Di, Sheng Cao, Qinglei Feng, Yunhe Xie, Zhen Cappello, Franck Univ Iowa Iowa City IA USA Stevens Inst Technol Hoboken NJ USA Argonne Natl Lab Lemont IL USA St Louis Univ St Louis MO USA Univ North Texas Denton TX USA Binghamton Univ Binghamton NY USA

ISBN: (纸本)9798400704130

Today's scientific applications running on supercomputers produce large volumes of data, leading to critical data storage and communication challenges. To tackle the challenges, error-bounded lossy compression is commonly adopted since it can reduce data size drastically within a user-defined error threshold. Previous work has shown that compression techniques can significantly reduce the storage and I/O overhead while retaining good data quality. However, the existing compressors are mainly designed for CPU and GPU. As new AI chips are being incorporated into supercomputers and increasingly used for accelerating scientific computing, there is a growing demand for efficient data compression on the new architecture. In this paper, we propose an efficient lossy compressor, CereSZ, based on the Cerebras CS-2 system. The compression algorithm is mapped onto Cerebras using both data parallelism and pipeline parallelism. In order to achieve a balanced workload on each processing unit, we propose an algorithm to evenly distribute the pipeline stages. Our experiments with six scientific datasets demonstrate that CereSZ can achieve a throughput from 227.93 GB/s to 773.8 GB/s, 2.43x to 10.98x faster than existing GPU compressors.

关键词： Error-bounded Lossy Compression AI-Optimized architecture Parallel computing Scientific Simulation high-speed Compressor

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PNS Lock: A Portable NUMA-Aware Lock with a standard Interface 1

PNS Lock: A Portable NUMA-Aware Lock with a Standard Interfa...

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1st international symposium on Parallel computing and Distributed Systems, PCDS 2024

作者： Gandham, Brahmaiah Alapati, Praveen Ecole Centrale School of Engineering Mahindra University Computer Science and Engineering Hyderabad India

ISBN: (纸本)9798350349658

In shared memory programming, there is a need for synchronization primitives that are suitable for modern hardware to achieve high performance and reduce contention. This paper introduces a novel lock with a standard interface, namely, the PNS Lock. It is a lock for Non-Uniform Memory Access (NUMA) architectures and uses one queue for each NUMA node. PNS lock uses atomic operation for lock handovers between NUMA nodes. This design helps to get better performance by minimizing cross-node communication and contention. PNS lock intelligently adapts to the underlying system topology. This paper discusses the design of a PNS lock and compares it's performance by considering the state-of-the-art synchronization objects. PNS lock also provides a standard interface and ensures seamless integration with existing multi-threaded applications. From the experimental evaluation, it is observed that PNS lock helps to enhance the performance and increases the cache hit rate. This synchronization primitive, PNS lock is a great tool for the developers in NUMA environments. © 2024 IEEE.

关键词： Memory architecture

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