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检索条件"任意字段=21st International Symposium on Computer Architecture and High Performance Computing"

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MeHyper: Accelerating Hypergraph Neural Networks by Exploring Implicit Dataflows 31

MeHyper: Accelerating Hypergraph Neural Networks by Explorin...

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31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Zhao, Wenju Yao, Pengcheng Chen, Dan Zheng, Long Liao, Xiaofei Wang, Qinggang Ma, Shaobo Li, Yu Liu, Haifeng Xiao, Wenjing Sun, Yufei Zhu, Bing Jin, Hai Xue, Jingling Huazhong University of Science and Technology National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Wuhan430074 China National University of Singapore School of Computing 119077 Singapore Guangxi University School of Computer Electronics and Information NanNing530004 China University of New South Wales School of Computer Science and Engineering SydneyNSW2052 Australia

ISBN: (纸本)9798331506476

Hypergraph Neural Networks (HGNNs) are increasingly utilized to analyze complex inter-entity relationships. Traditional HGNN systems, based on a hyperedge-centric dataflow model, independently process aggregation tasks for hyperedges and vertices, leading to significant computational redundancy. This redundancy arises from recalculating shared information across different tasks. For the first time, we identify and harness implicit dataflows (i.e., dependencies) within HGNNs, introducing the microedge concept to effectively capture and reuse intricate shared information among aggregation tasks, thereby minimizing redundant computations. We have developed a new microedge-centric dataflow model that processes shared information as fine-grained microedge aggregation tasks. This dataflow model is supported by the Read-Process-Activate-Generate execution model, which aims to optimize parallelism among these tasks. Furthermore, our newly developed MeHyper, a microedge-centric HGNN accelerator, incorporates a decoupled pipeline for improved computational parallelism and a hierarchical feature management strategy to reduce off-chip memory accesses for large volumes of intermediate feature vectors generated. Our evaluation demonstrates that MeHyper substantially outperforms the leading CPUbased system PyG-CPU and the GPU-based system HyperGef, delivering performance improvements of 1,032.23 × and 10.51 ×, and energy efficiencies of 1,169.03 × and 9.96 ×, respectively. © 2025 IEEE.

关键词： Redundancy

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LSQCA: Resource-Efficient Load/store architecture for Limited-Scale Fault-Tolerant Quantum computing 31

LSQCA: Resource-Efficient Load/Store Architecture for Limite...

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31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Kobori, Takumi Suzuki, Yasunari Ueno, Yosuke Tanimoto, Teruo Todo, Synge Tokunaga, Yuuki The University of Tokyo Japan NTT Corporation Japan RIKEN Japan Kyushu University Japan

ISBN: (纸本)9798331506476

Current fault-tolerant quantum computer (FTQC) architectures utilize several encoding techniques to enable reliable logical operations with restricted qubit connectivity. However, such logical operations demand additional memory overhead to ensure fault tolerance. Since the main obstacle to practical quantum computing is the limited qubit count, our primary mission is to design floorplans that can reduce memory overhead without compromising computational capability. Despite extensive efforts to explore FTQC architectures, even the current state-of-the-art floorplan strategy devotes 50% of memory space to this overhead, not to data storage, to guarantee unit-time random access to all logical qubits. In this paper, we propose an FTQC architecture based on a novel floorplan strategy, Load/store Quantum computer architecture (LSQCA), which can achieve almost 100% memory density. The idea behind our architecture is to separate the whole memory regions into small computational space called Computational Registers (CR) and space-efficient memory space called Scan-Access Memory (SAM). We define an instruction set for these abstract structures and provide concrete designs named point-SAM and line-SAM architectures. With this design, we can improve the memory density by allowing variable-latency memory access while concealing the latency with other bottlenecks. We also propose optimization techniques to exploit properties of quantum programs observed in our static analysis, such as access locality in memory reference timestamps. Our numerical results indicate that LSQCA successfully leverages this idea. In a resource-restricted situation, a specific benchmark shows that we can achieve approximately 90% memory density with 5% increase in the execution time compared to a conventional floorplan, which achieves at most 50% memory density for unit-time random access. Our design is defined as an abstract form, making this principle ubiquitous and applicable to a wide range of quant

关键词： Qubits

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Marching Page Walks: Batching and Concurrent Page Table Walks for Enhancing GPU Throughput 31

Marching Page Walks: Batching and Concurrent Page Table Walk...

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31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Lee, Jiwon Ko, Gun Yoon, Myung Kuk Jeong, Ipoom Oh, Yunho Ro, Won Woo Ewha Womans University Department of Computer Science and Engineering Seoul Korea Republic of Yonsei University Department of System Semiconductor Engineering Seoul Korea Republic of Yonsei University Department of Electrical and Electronic Engineering Seoul Korea Republic of Korea University School of Electrical Engineering Seoul Korea Republic of

ISBN: (纸本)9798331506476

Virtual memory, with the support of address translation hardware, is a key technique in expanding programmability and memory management in GPUs. However, the nature of the GPU execution model heavily pressures its translation hardware, particularly due to a discrepancy in the behavior of page table walkers and thousands of concurrently running threads. In GPU workloads, multiple threads simultaneously access a number of pages necessitating a substantial number of translations whereas each walker handles only a single walk request at a time. Such a limitation significantly increases the queueing latency of walk requests, which we observe as a major bottleneck for servicing page table walks in GPUs. To tackle this challenge, we investigate a design of page walkers that facilitates multiple walk requests to be handled together in batches. Then, we make the following observations: 1) allowing a page walker to issue beyond a single memory request significantly improves the throughput of walkers, and 2) GPU applications tend to concurrently access pages in wide address ranges. By leveraging the above implications, we propose Marching Page Walks (MPW) that effectively mitigate the contention in GPU page table walkers. MPW scans pending walk requests to identify ones that can be grouped together. Then, MPW batches these requests and concurrently handles them by issuing multiple memory instructions. Experiments show that MPW reduces the queueing latency of page walks by 86.7% and improves GPU performance by 55.6% over the baseline design. © 2025 IEEE.

关键词： Graphics processing unit

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To Cross, or Not to Cross Pages for Prefetching? 31

To Cross, or Not to Cross Pages for Prefetching?

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31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Vavouliotis, Georgios Torrents, Marti Grot, Boris Kalaitzidis, Kleovoulos Peled, Leeor Casas, Marc Barcelona Supercomputing Center Spain Computing Systems Lab Huawei Zurich Research Center Switzerland University of Edinburgh United Kingdom Boole Lab Huawei Tel-Aviv Research Center Israel Universitat Politecnica de Catalunya Spain

ISBN: (纸本)9798331506476

Despite processor vendors reporting that cache prefetchers operating with virtual addresses are permitted to cross page boundaries, academia is focused on optimizing cache prefetching for patterns within page boundaries. This work reveals that page-cross prefetching at the first-level data cache (L1D) is seldom beneficial across different execution phases and workloads while showing that state-of-the-art L1D prefetchers are not very accurate at prefetching across page boundaries. In response, we propose M O K A, a holistic framework for designing Page-Cross Filters, i.e., microarchitectural schemes that ensure effective and accurate prefetching across page boundaries. MOKA combines (i) hashed perceptron predictors that use prefetcher-independent program features, (ii) predictors that adapt decisions based on the system state (e.g., TLB pressure), and (iii) a scheme to dynamically optimize predictions across different execution phases and workload types. We use the MOKA framework to prototype a Page-Cross Filter, named DRIPPER, for three relevant L1D prefetchers (Berti [60], IPCP [61], BOP [57]). We show that DRIPPER accurately enables pagecross prefetching only when it is beneficial for performance. For instance, Berti [60] (state-of-the-art prefetcher) combined with DRIPPER improves single-core geomean performance over Berti that always permits page-cross prefetches and Berti that always discards page-cross prefetches by {1.7%}({1. 2%}) and {2.5%}({2.1%}) across 218 seen (178 unseen) workloads, respectively. Across 300 8 -core mixes, the corresponding geomean speedups are 2.0% and 3.3%. Finally, we show that DRIPPER provides consistent benefits when both 4KB pages and 2MB large pages are used. © 2025 IEEE.

关键词： Virtual addresses

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InstAttention: In-storage Attention Offloading for Cost-Effective Long-Context LLM Inference 31

InstAttention: In-Storage Attention Offloading for Cost-Effe...

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31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Pan, Xiurui Li, Endian Li, Qiao Liang, Shengwen Shan, Yizhou Zhou, Ke Luo, Yingwei Wang, Xiaolin Zhang, Jie Peking University China University of Electronic Science and Technology of China China Institute of Computing Technology Chinese Academy of Sciences China Huawei Cloud China Wuhan National Laboratory for Optoelectronics Huazhong University of Science and Technology China

ISBN: (纸本)9798331506476

The widespread of Large Language Models (LLMs) marks a significant milestone in generative AI. Nevertheless, the increasing context length and batch size in offline LLM inference escalate the memory requirement of the key-value (KV) cache, which imposes a huge burden on the GPU VRAM, especially for resource-constrained scenarios (e.g., edge computing). Several cost-effective solutions leverage host memory or SSDs to reduce storage costs for offline inference scenarios and improve the throughput. Nevertheless, they suffer from significant performance penalties imposed by intensive KV cache accesses due to limited PCIe bandwidth. To address these issues, we propose InstAttention, a novel LLM inference system that offloads the most performance-critical computation (i.e., attention in decoding phase) and data (i.e., KV cache) parts to Computational storage Drives (CSDs), which minimize the enormous KV transfer overheads. InstAttention designs a dedicated flashaware in-storage attention engine with KV cache management mechanisms to exploit the high internal bandwidths of CSDs instead of being limited by the PCIe bandwidth. The optimized P2P transmission between GPU and CSDs further reduces data migration overheads. Experimental results demonstrate that for a 13B model using an NVIDIA A6000 GPU, InstAttention improves throughput for long-sequence inference by up to 11.1 ×, compared to existing SSD-based solutions such as FlexGen. © 2025 IEEE.

关键词： computer graphics equipment

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HT-NoC: Reconfigurable high Throughput Network-on-Chip for AI Dataflow Accelerators 21st

HT-NoC: Reconfigurable High Throughput Network-on-Chip for ...

引用

21st international symposium on Applied Reconfigurable computing, ARC 2025

作者： Zhiri, Mohamed Amine Krichene, Hana Sandionigi, Chiara Pillement, Sébastien Université Paris-Saclay CEA LIST Palaiseau91120 France Université Grenoble Alpes CEA LIST Grenoble38000 France Nantes Université CNRS IETR UMR 6164 Nantes44000 France

ISBN: (纸本)9783031879944

Fully Connected (FC) layers are a bottleneck for many Deep Neural Networks (DNN) algorithms due to their high bandwidth requirements, which makes their hardware acceleration particularly challenging. In this paper, we address this challenge from a communication-centric approach. We propose HT-NoC (high Throughput Network-on-Chip), a reconfigurable NoC to accelerate FC layers. HT-NoC features reconfigurable router connections that adapt to varying data traffic patterns. This enables the utilization of available unused bandwidth and router resources to transport more packets simultaneously. Compared to a baseline mesh NoC, HT-NoC achieves a 4× reduction in latency and a 2.7× decrease in energy consumption in the propagation of time-consuming FC layer weight parameters. HT-NoC also achieves favorable performance for some Convolution (CONV) layers. When integrated into an AI dataflow accelerator, HT-NoC achieves a 3× speedup in executing Feed Forward Network (FFN) blocks in Transformers, outperforming state-of-the-art (SoA) systolic array (SA) based accelerators. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2025.

关键词： Systolic arrays

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MLPerf Power: Benchmarking the Energy Efficiency of Machine Learning Systems from μWatts to MWatts for Sustainable AI 31

MLPerf Power: Benchmarking the Energy Efficiency of Machine ...

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31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Tschand, Arya Rajan, Arun Tejusve Raghunath Idgunji, Sachin Ghosh, Anirban Holleman, Jeremy Kiraly, Csaba Ambalkar, Pawan Borkar, Ritika Chukka, Ramesh Cockrell, Trevor Curtis, Oliver Fursin, Grigori Hodak, Miro Kassa, Hiwot Lokhmotov, Anton Miskovic, Dejan Pan, Yuechao Manmathan, Manu Prasad Raymond, Liz John, Tom st. Suresh, Arjun Taubitz, Rowan Zhan, Sean Wasson, Scott Kanter, David Reddi, Vijay Janapa Meta United States Harvard University United States NVIDIA United States UNC Charlotte / Syntiant United States Codex Dell United States Intel United States SMC Japan FlexAI / cTuning AMD United States KRAI Google United States Decompute GATE Overflow India MLCommons

ISBN: (纸本)9798331506476

Rapid adoption of machine learning (ML) technologies has led to a surge in power consumption across diverse systems, from tiny IoT devices to massive datacenter clusters. Benchmarking the energy efficiency of these systems is crucial for optimization, but presents novel challenges due to the variety of hardware platforms, workload characteristics, and system-level interactions. This paper introduces MLPerf® Power, a comprehensive benchmarking methodology with capabilities to evaluate the energy efficiency of ML systems at power levels ranging from microwatts to megawatts. Developed by a consortium of industry professionals from more than 20 organizations, coupled with insights from academia, MLPerf Power establishes rules and best practices to ensure comparability across diverse architectures. We use representative workloads from the MLPerf benchmark suite to collect {1, 8 4 1} reproducible measurements from 60 systems across the entire range of ML deployment scales. Our analysis reveals trade-offs between performance, complexity, and energy efficiency across this wide range of systems, providing actionable insights for designing optimized ML solutions from the smallest edge devices to the largest cloud infrastructures. This work emphasizes the importance of energy efficiency as a key metric in the evaluation and comparison of the ML system, laying the foundation for future research in this critical area. We discuss the implications for developing sustainable AI solutions and standardizing energy efficiency benchmarking for ML systems. © 2025 IEEE.

关键词： computer architecture energy efficiency machine learning mlperf sustainable ai

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LAD: Efficient Accelerator for Generative Inference of LLM with Locality Aware Decoding 31

LAD: Efficient Accelerator for Generative Inference of LLM w...

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31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Wang, Haoran Li, Yuming Xu, Haobo Wang, Ying Liu, Liqi Yang, Jun Han, Yinhe Institute of Computing Technology Chinese Academy of Sciences China University of Chinese Academy of Sciences China

ISBN: (纸本)9798331506476

Large Language Models (LLMs) have emerged as the cornerstone of content generation applications due to their ability to capture relations between newly generated token and the full preceding context. However, this ability stems from the attention mechanism for decoding that retains the entire generation history as key value cache (KV cache). As the generated sequence lengthens, the KV cache expands, causing a substantial memory access bottleneck. In advanced LLM generation systems running on GPUs, the attention mechanism for decoding accounts for more than 50% of the total inference time when the KV cache length reaches 4096. To address this issue, this paper introduces LAD (Locality Aware Decoding), an LLM generation accelerator with algorithm-hardware enhancements that significantly decrease KV cache access, resulting in considerable speedups and energy savings. A key insight underlying LAD is that when the attention score for a specific position remains fixed over the next several decoding steps, it is unnecessary to repeatedly retrieve the associated key and value at each step to reproduce the computation. Our analysis reveals that numerous positions exhibit notable numerical locality in attention scores through multiple decoding steps. Leveraging these insights, we have designed an innovative attention decoding computation method that decreases the frequency of accessing the key and value for positions demonstrating good locality, all while maintaining decoding accuracy. Extensive experiments show that LAD generates sequences with an average ROUGE-1 similarity of 97% compared to those generated by the original model. When the length of KV cache exceeds 2048, the high configuration of LAD accelerator achieves on average (geomean) 10.7 × speedup and 52.4 × energy efficiency for the attention mechanism compared to the A100 GPU. For end-to-end model inference, it also achieves on average 2.3 × speedup and 13.4 × energy efficiency. © 2025 IEEE.

关键词： Program processors

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PROCA: Programmable Probabilistic Processing Unit architecture with Accept/Reject Prediction & Multicore Pipelining for Causal Inference 31

PROCA: Programmable Probabilistic Processing Unit Architectu...

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31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Fu, Yihan Fan, Anjunyi Yue, Wenshuo Zhao, Hongxiao Shi, Daijing Wu, Qiuping Li, Jiayi Zhang, Xiangyu Tao, Yaoyu Yang, Yuchao Yan, Bonan Independent Researcher United States Peking University Beijing Advanced Innovation Center for Integrated Circuits School of Integrated Circuits Beijing China Peking University School of Electronic and Computer Engineering Shenzhen China Chinese Institute for Brain Research Beijing China

ISBN: (纸本)9798331506476

Causal inference is an important field in data science and cognitive artificial intelligence. It requires the construction of complex probabilistic models to describe the causal relationships between random variables. Probabilistic models rely on probabilistic programming as a flexible framework. However, the computing speed of probabilistic programming is often hindered by the extensive use of Markov chain Monte Carlo (MCMC) algorithms, even though they are powerful in Bayesian inference. To accelerate MCMC, this work presents PROCA, a programmable MCMC-based probabilistic processing unit architecture. PROCA exploits processing-in-memory function units to generate new samples of Markov chains. PROCA is programmable to execute the computation for arbitrary forms of posterior distribution formulas that software probabilistic programming frameworks support. We develop a novel accept/reject prediction methodology to accelerate the sequential MCMC computation, thereby introducing efficient multi-core pipelining methods. We implement and validate the PROCA architecture with commercial process development kits. The implementation is evaluated based on 9 representative benchmarks, covering PyMC official tutorial probabilistic problems, single-variable probabilistic problems, and real-world causal inference problems. Our comprehensive experiments demonstrate that PROCA achieves a speedup of 172~4871 × compared to Intel Xeon Gold CPU, 42 ∼ 1058 × compared to NVIDIA A100 GPU, and 1.765 × over state-of-the-art MCMC accelerators, respectively. PROCA achieves comparable statistical robustness to the software probabilistic programming frameworks. Compared with state-of-the-art MCMC domain-specific accelerators, our design boosts the energy efficiency by 9.47 ×. © 2025 IEEE.

关键词： Markov chains

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Piccolo: Large-Scale Graph Processing with Fine-Grained in-Memory Scatter-Gather 31

Piccolo: Large-Scale Graph Processing with Fine-Grained in-M...

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31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Shin, Changmin Song, Jaeyong Jang, Hongsun Kim, Dogeun Sung, Jun Kwon, Taehee Ju, Jae Hyung Liu, Frank Choi, Yeonkyu Lee, Jinho Seoul National University Department of Electrical and Computer Engineering Korea Republic of Old Dominion Univeristy School of Data Science United States Samsung Electronics Korea Republic of

ISBN: (纸本)9798331506476

Graph processing requires irregular, fine-grained random access patterns incompatible with contemporary off-chip memory architecture, leading to inefficient data access. This inefficiency makes graph processing an extremely memory-bound application. Because of this, existing graph processing accelerators typically employ a graph tiling-based or processing-in-memory (PIM) approach to relieve the memory bottleneck. In the tiling-based approach, a graph is split into chunks that fit within the on-chip cache to maximize data reuse. In the PIM approach, arithmetic units are placed within memory to perform operations such as reduction or atomic addition. However, both approaches have several limitations, especially when implemented on current memory standards (i.e., DDR). Because the access granularity provided by DDR is much larger than that of the graph vertex property data, much of the bandwidth and cache capacity are wasted. PIM is meant to alleviate such issues, but it is difficult to use in conjunction with the tiling-based approach, resulting in a significant disadvantage. Furthermore, placing arithmetic units inside a memory chip is expensive, thereby supporting multiple types of operation is thought to be impractical. To address the above limitations, we present Piccolo, an end-to-end efficient graph processing accelerator with fine-grained in-memory random scatter-gather. Instead of placing expensive arithmetic units in off-chip memory, Piccolo focuses on reducing the off-chip traffic with non-arithmetic function-in-memory of random scatter-gather. To fully benefit from in-memory scatter-gather, Piccolo redesigns the cache and miss-handling architecture (MHA) of the accelerator such that it can enjoy both the advantage of tiling and in-memory operations. Piccolo achieves a maximum speedup of 3.28 × and a geometric mean speedup of 1.62 ×, along with up to 59.7% reduction in energy consumption across various and extensive benchmarks. © 2025 IEEE.

关键词： Memory architecture

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