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检索条件"任意字段=21st International Symposium on Computer Architecture and High Performance Computing"

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BitMoD: Bit-serial Mixture-of-Datatype LLM Acceleration 31

BitMoD: Bit-serial Mixture-of-Datatype LLM Acceleration

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31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Chen, Yuzong Abouelhamayed, Ahmed F. Dai, Xilai Wang, Yang Andronic, Marta Constantinides, George A. Abdelfattah, Mohamed S. Cornell University Computer Systems Lab United States Systems and Networking Research Group Microsoft Research United States Imperial College London Department of Electrical and Electronic Engineering United Kingdom

ISBN: (纸本)9798331506476

Large language models (LLMs) have demonstrated remarkable performance across various machine learning tasks. Yet the substantial memory footprint of LLMs significantly hinders their deployment. In this paper, we improve the accessibility of LLMs through BitMoD1, an algorithm-hardware co-design solution that enables efficient LLM acceleration at low weight precision. On the algorithm side, BitMoD introduces fine-grained data type adaptation that uses a different numerical data type to quantize a group of (e.g., 128) weights. Through the careful design of these new data types, BitMoD is able to quantize LLM weights to very low precision (e.g., 4 bits and 3 bits) while maintaining high accuracy. On the hardware side, BitMoD employs a bitserial processing element to easily support multiple numerical precisions and data types;our hardware design includes two key innovations: First, it employs a unified representation to process different weight data types, thus reducing the hardware cost. Second, it adopts a bit-serial dequantization unit to rescale the per-group partial sum with minimal hardware overhead. Our evaluation on six representative LLMs demonstrates that BitMoD significantly outperforms state-of-the-art LLM quantization and acceleration methods. For discriminative tasks, BitMoD can quantize LLM weights to 4 -bit with © 2025 IEEE.

关键词： Integrated circuit design

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Warped-Compaction: Maximizing GPU Register File Bandwidth Utilization via Operand Compaction 31

Warped-Compaction: Maximizing GPU Register File Bandwidth Ut...

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31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Jeong, Eunbi Jeong, Ipoom Yoon, Myung Kuk Kim, Nam Sung Ewha Womans University Department of Computer Science and Engineering Seoul Korea Republic of Yonsei University Department of System Semiconductor Engineering Seoul Korea Republic of Yonsei University Department of Electrical and Electronic Engineering Seoul Korea Republic of University of Illinois Urbana-Champaign Urbana United States

ISBN: (纸本)9798331506476

The GPU has been successfully used for diverse emerging compute-intensive applications, including imaging, computer vision, and more recently, deep learning, to name a few. To offer high performance for such applications, it is provisioned with massive Register Files (RFs) to exploit high Thread-Level Parallelism (TLP). As RFs are designed to store thousands of contexts and provide very high bandwidth for uninterrupted supply of operands to hundreds of compute units for high TLP, they have become one of the most power-hungry components in the GPU. Meanwhile, faced with the end of Dennard scaling, it is more important than ever to innovate the microarchitecture of (power-constrained) GPUs to continuously improve the performance of future compute-intensive *** this work, we propose a GPU microarchitecture, WarpedCompaction, designed to utilize given RFs more efficiently, instead of relying on larger-capacity and/or higher-bandwidth RFs to further improve GPU performance. Specifically, first, we reverse-engineer the latest GPU's RF organization through microbenchmarking. This uncovers that each sub-core within a streaming multiprocessor contains only two dual-ported RF banks, and accesses to these banks are arbitrated solely based on register IDs. We also reveal that, despite the modest configurations, RF banks are largely underutilized, staying inactive for 33.5% of the time. Second, we observe that previously proposed RF optimization techniques, data forwarding and dead register elimination, cannot address this underutilization problem. This is mainly due to the (R1) insufficient RF access requests from a limited number of Operand Collector Units (OCUs) and (R2) inefficient operand distribution by the conventional RF bank arbitration. Third, we present two architectural solutions to tackle the observed inefficiency: (S1) OCU sharing and (S2) skewed arbitrator. Building on enhanced OCU early allocation for partially ready instructions and operand forwardin

关键词： Compaction

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Make LLM Inference Affordable to Everyone: Augmenting GPU Memory with NDP-DIMM 31

Make LLM Inference Affordable to Everyone: Augmenting GPU Me...

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31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Liu, Lian Zhao, Shixin Li, Bing Ren, Haimeng Xu, Zhaohui Wang, Mengdi Li, Xiaowei Han, Yinhe Wang, Ying Institute of Computing Technology Chinese Academic of Sciences China University of Chinese Academy of Sciences China Zhongguancun Laboratory China Institute of Microelectronics Chinese Academy of Sciences China ShanghaiTech University School of Information Science and Technology China

ISBN: (纸本)9798331506476

The billion-scale Large Language Models (LLMs) necessitate deployment on expensive server-grade GPUs with large-storage HBMs and abundant computation capability. As LLM-assisted services become popular, achieving cost-effective LLM inference on budget-friendly hardware becomes the current trend. This has sparked extensive research into relocating LLM parameters from expensive GPUs to external host memory. However, the restricted bandwidth between the host and GPU memory limits the inference performance of existing solutions. This work introduces Hermes, a budget-friendly system that leverages the near-data processing units (NDP) within commodity DRAM DIMMs to enhance the performance of a single consumer-grade GPU, achieving efficient LLM inference. We recognize that the inherent activation sparsity in LLMs naturally divides weight parameters into two categories, termed 'hot' and 'cold' neurons, respectively. Hot neurons, which consist of only approximately 20% of all weight parameters, account for 80% of the total computational load. In contrast, cold neurons make up the other 80% of parameters but are responsible for just 20% of the computational workload. Leveraging this observation, we propose a heterogeneous computing strategy: mapping hot neurons to a single computation-efficient GPU without large-capacity HBMs, while offloading cold neurons to NDP-DIMMs, which offer large memory size but limited computation capabilities. In addition, the dynamic nature of activation sparsity necessitates a real-time partition of hot and cold neurons and adaptive remapping of cold neurons across multiple NDP-DIMM modules. To tackle these issues, we introduce a lightweight predictor that ensures optimal real-time neuron partition and adjustment between GPU and NDP-DIMMs. Furthermore, we utilize a window-based online scheduling mechanism to maintain load balance among multiple NDP-DIMM modules. In summary, Hermes facilitates the deployment of LLaMA2-70B on consumer-grade hardware

关键词： Budget control

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Criticality-Aware Instruction-Centric Bandwidth Partitioning for Data Center Applications 31

Criticality-Aware Instruction-Centric Bandwidth Partitioning...

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31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Zhu, Liren Li, Liujia Wu, Jianyu Yao, Yiming Shi, Zhan Zhang, Jie Wang, Zhenlin Wang, Xiaolin Luo, Yingwei Zhou, Diyu Huawei Hisilicon China Peking University National Key Laboratory for Multimedia Information Processing School of Computer Science China Zhongguancun Laboratory China Michigan Technological University United States

ISBN: (纸本)9798331506476

To reduce operational costs, modern data centers co-locate high-priority latency-critical (LC) tasks and low-priority best-effort (BE) tasks on the same physical node to increase resource utilization. However, such co-location leads to contention for memory bandwidth, resulting in priority inversion, where BE tasks severely slow down LC tasks. This priority inversion often leads to violations of the quality of service (QoS) requirements for LC tasks, defeating the purpose of co-location. Prior approaches to this issue either fail to enforce the QoS requirements for LC tasks or underutilize memory *** present Pivot, a novel bandwidth partitioning system that overcomes the limitations of prior approaches based on two key insights. First, memory accesses from LC tasks must be prioritized across all the components on the memory path rather than a single component, as done in prior work. Second, only the scheduling of a selective portion of performance-critical loads (i.e., those causing a long stall on the re-order buffer), instead of all memory accesses from LC tasks, should be prioritized. To leverage these insights, Pivot overcomes the key challenge of accurately identifying performance-critical loads while incurring minimal runtime overhead by proposing a two-phase profiling technique. Our extensive evaluation shows that Pivot improves effective machine utilization by up to {3 4. 5%} while increasing the throughput of the BE applications by up to 2.76 × compared to state-of-the-art approaches. © 2025 IEEE.

关键词： Buffer storage

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Real-Time Multi-object Tracking Using YOLOv8 and SORT on a SoC FPGA 21st

Real-Time Multi-object Tracking Using YOLOv8 and SORT on a...

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21st international symposium on Applied Reconfigurable computing, ARC 2025

作者： Danilowicz, Michal Kryjak, Tomasz Embedded Vision Systems Group Computer Vision Laboratory Department of Automatic Control and Robotics AGH University of Science and Technology Krakow Poland

ISBN: (纸本)9783031879944

Multi-object tracking (MOT) is one of the most important problems in computer vision and a key component of any vision-based perception system used in advanced autonomous mobile robotics. Therefore, its implementation on low-power and real-time embedded platforms is highly desirable. Modern MOT algorithms should be able to track objects of a given class (e.g. people or vehicles). In addition, the number of objects to be tracked is not known in advance, and they may appear and disappear at any time, as well as be obscured. For these reasons, the most popular and successful approaches have recently been based on the tracking paradigm. Therefore, the presence of a high quality object detector is essential, which in practice accounts for the vast majority of the computational and memory complexity of the whole MOT system. In this paper, we propose an FPGA (Field-Programmable Gate Array) implementation of an embedded MOT system based on a quantized YOLOv8 detector and the SORT (Simple Online Realtime Tracker) tracker. We use a modified version of the FINN framework to utilize external memory for model parameters and to support operations necessary required by YOLOv8. We discuss the evaluation of detection and tracking performance using the COCO and MOT15 datasets, where we achieve 0.21 mAP and 38.9 MOTA respectively. As the computational platform, we use an MPSoC system (Zynq UltraScale+ device from AMD/Xilinx) where the detector is deployed in reprogrammable logic and the tracking algorithm is implemented in the processor system. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2025.

关键词： System-on-chip

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GSArch: Breaking Memory Barriers in 3D Gaussian Splatting Training via Architectural Support 31

GSArch: Breaking Memory Barriers in 3D Gaussian Splatting Tr...

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31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： He, Houshu Li, Gang Liu, Fangxin Jiang, Li Liang, Xiaoyao Song, Zhuoran Shanghai Jiao Tong University Department of Computer Science and Engineering Shanghai China Institute of Automation Chinese Academy of Sciences Beijing China

ISBN: (纸本)9798331506476

3D Gaussian Splatting (3DGS) introduces a novel methodology for representing scenes with anisotropic 3D Gaussian primitives, achieving exceptional quality and rendering speed in neural scene representation (NSR). However, the insufficient training speed of 3DGS limits its applicability in tasks that require online learning to perceive dynamic environments, such as autonomous driving and embodied intelligence. Although recent work, GSCore, has introduced a specialized accelerator for the rendering process of 3DGS, it overlooks the time-consuming backward propagation during 3DGS *** this paper, we propose GSArch, a hardware architecture designed to overcome memory barriers and boost the efficiency of 3DGS training. Through a thorough characterization of 3DGS training, we identify three root causes of inefficiency: redundant data loading from off-chip memory, time-consuming atomic write operations, and severe bank conflicts during on-chip buffer reading. To address these challenges, GSArch introduces three architectural innovations. First, acknowledging that Gaussians vary in shape and often span multiple pixels, with larger Gaussians causing more repetitive data loading, GSArch employs hybrid memory management. This approach categorizes Gaussians into 'hot' and 'cold' ones, storing hot Gaussians in a fast but small on-chip buffer to reduce redundant loading while minimizing hardware costs. Second, GSArch leverages the informativeness variability of Gaussians' gradients to filter out low-contribution gradients, significantly reducing atomic operations. Lastly, a rearrangement unit is designed to pack conflicting memory read requests into non-conflicting bundles. Our evaluation results demonstrate that GSArch achieves up to 6.49 × and 15.42 × speedups compared to Nvidia A100 and Jetson AGX Xavier, respectively, with substantially lower energy consumption and negligible image quality loss. © 2025 IEEE.

关键词： Gaussian distribution

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Dynamic Function Exchange in FPGA to Redefine RISC-V Multicore architectures at Runtime 21st

Dynamic Function Exchange in FPGA to Redefine RISC-V Multi...

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21st international symposium on Applied Reconfigurable computing, ARC 2025

作者： Alves, Téo Sobrino Bonato, Vanderlei Institute of Mathematical and Computing Sciences The University of São Paulo São Paulo São Carlos Brazil

ISBN: (纸本)9783031879944

Dynamic Partial Reconfiguration is a powerful feature available in some FPGAs that enables the reconfiguration of specific regions within the FPGA fabric without halting the whole system. This capability opens new opportunities for more efficient utilization of the available FPGA resources since the hardware can be configured dynamically to better fit the demands of varying workloads. In this work, we investigate the Dynamic Partial Reconfiguration available from Xilinx/AMD FPGAs as Dynamic Function Exchange in multicore RISC-V systems, focusing on maximizing area utilization while minimizing execution time for a set of testbenches. This approach leverages the modularity of the RISC-V architecture that goes beyond the traditional customization provided by the RISC-V processor extensions. As a result for a testbench composed of CNN, Linked List, and Simplex Method, we could notice an improvement from 0.15% to 6% in execution time by dynamically reconfiguring the RISC-V in relation to the number of cores and configurations of each core regarding cache size and availability of FPU. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2025.

关键词： Reconfigurable hardware

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VQ-LLM: high-performance Code Generation for Vector Quantization Augmented LLM Inference 31

VQ-LLM: High-performance Code Generation for Vector Quantiza...

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31st IEEE international symposium on high performance computer architecture, HPCA 2025

作者： Liu, Zihan Luo, Xinhao Guo, Junxian Ni, Wentao Zhou, Yangjie Guan, Yue Guo, Cong Cui, Weihao Feng, Yu Guo, Minyi Zhu, Yuhao Zhang, Minjia Jin, Chen Leng, Jingwen Shanghai Jiao Tong University China Shanghai Qi Zhi Institute China Duke University United States National University of Singapore Singapore University of Rochester United States University of Illinois Urbana-Champaign United States Magik Compute

ISBN: (纸本)9798331506476

Vector quantization (VQ), which treats a vector as a compression unit, gains increasing research interests for its potential to accelerate large language models (LLMs). Compared to conventional element-wise quantization methods, VQ algorithms can compress weight and KV cache tensors in LLMs with a greater ratio while maintaining the high model accuracy. However, translating a VQ algorithm's memory reduction into the actual latency improvement is challenging. We profile and analyze the current approach of integrating VQ into computation kernels and show that its major inefficiency lies in the poor access efficiency of codebooks in VQ algorithms and uncoordinated computation dataflow. Meanwhile, the diversity of VQ algorithms (e.g., different vector sizes and entry counts) and LLMs, computation kernels (e.g matrix-matrix/vector multiplication and attention computation) makes it impractical to manually craft efficient kernel implementations for each specific case. In this work, we design and implement VQ-LLM, an efficient fused VQ kernel generation framework. We first introduce a software abstraction called codebook cache to optimize codebook access efficiency and support the integration of VQ with various computations. The codebook cache adaptively stores different entries across the GPU's memory hierarchy, including off-chip global memory, on-chip shared memory, and registers. Centered around the codebook cache, we design an efficient computation engine that optimizes memory traffic during computations involving codebooks. This compute engine adopts the codebook-centric dataflow and fusion optimizations. Additionally, we provide adaptive heuristics to tailor parameter selection in our optimizations to diverse VQ configurations. Our optimizations achieve the latency reduction of {6 4. 3 6%} to {9 9. 1%} compared to existing open-source implementations. A final comparison with state-of-the-art element-wise quantization methods like AWQ and QoQ shows that our VQ-LLM is

关键词： Vectors

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Ultra-Low Latency and Extreme-Throughput Echo state Neural Networks on FPGA 21st

Ultra-Low Latency and Extreme-Throughput Echo State Neural ...

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21st international symposium on Applied Reconfigurable computing, ARC 2025

作者： Jafari, Atousa Platzner, Marco Computer Science Department Paderborn University Paderborn Germany

ISBN: (纸本)9783031879944

Echo state networks, as a popular form of reservoir computing models, are recurrent neural networks that consist of three layers, and only the output layer needs to be trained. Compared to other recurrent neural network models, echo state networks offer comparable performance for many tasks but lead to reduced computational requirements, making them highly suitable for resource-constrained edge implementations. In this paper, we present and compare two streamlining dataflow accelerators for echo state networks on FPGA. Our accelerators rely on a direct logic implementation style with fully unrolled computations and are fully quantized to avoid floating-point calculations. After proposing a taxonomy of DNN implementation styles on FPGA, we present a tool flow to automatically create such FPGA accelerators for echo state networks. We then discuss two accelerator versions, one employing DSP blocks available in FPGAs and the other one converting multiplications into add/shift operations mapped solely to LUTs. We evaluate our accelerators on three time-series forecasting tasks and report the achieved accuracy as well as the resource requirements, the latency, the throughput, and the required energy. Our designs achieve extreme-throughput and ultra-low latency, reaching up to 100 Megasamples/s and 9.5 ns, respectively, which significantly outperforms related FPGA-based implementations. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2025.

关键词： Recurrent neural networks

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Hardware-Accelerated Event-Graph Neural Networks for Low-Latency Time-Series Classification on SoC FPGA 21st

Hardware-Accelerated Event-Graph Neural Networks for Low-La...

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21st international symposium on Applied Reconfigurable computing, ARC 2025

作者： Nakano, Hiroshi Blachut, Krzysztof Jeziorek, Kamil Wzorek, Piotr Dampfhoffer, Manon Mesquida, Thomas Nishi, Hiroaki Kryjak, Tomasz Dalgaty, Thomas Graduate School of Science and Technology Keio University Tokyo Japan Embedded Vision Systems Group Computer Vision Laboratory AGH University of Krakow Krakow Poland CEA-List Université Grenoble Alpes Grenoble France

ISBN: (纸本)9783031879944

As the quantities of data recorded by embedded edge sensors grow, so too does the need for intelligent local processing. Such data often comes in the form of time-series signals, based on which real-time predictions can be made locally using an AI model. However, a hardware-software approach capable of making low-latency predictions with low power consumption is required. In this paper, we present a hardware implementation of an event-graph neural network for time-series classification. We leverage an artificial cochlea model to convert the input time-series signals into a sparse event-data format that allows the event-graph to drastically reduce the number of calculations relative to other AI methods. We implemented the design on a SoC FPGA and applied it to the real-time processing of the Spiking Heidelberg Digits (SHD) dataset to benchmark our approach against competitive solutions. Our method achieves a floating-point accuracy of 92.7% on the SHD dataset for the base model, which is only 2.4% and 2% less than the state-of-the-art models with over 10× and 67× fewer model parameters, respectively. It also outperforms FPGA-based spiking neural network implementations by 19.3% and 4.5%, achieving 92.3% accuracy for the quantised model while using fewer computational resources and reducing latency. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2025.

关键词： event-based audio processing FPGA graph convolutional neural networks dynamic audio sensor artificial cochlea

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