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检索条件"任意字段=21st International Symposium on Computer Architecture and High Performance Computing"

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Accelerating the LOBPCG method on sunway taihulight 21

Accelerating the LOBPCG method on sunway taihulight

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21st IEEE international Conference on high performance computing and Communications, 17th IEEE international Conference on Smart City and 5th IEEE international Conference on Data Science and Systems, HPCC/SmartCity/DSS 2019

作者： Yu, Tianyu Zhao, Yonghua Zhao, Lian Computer Network Information Center Chinese Academy of Sciences University of Chinese Academy of Sciences Beijing China Computer Network Information Center Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781728120584

LOBPCG is a numerical eigensolver which can be parallelly implemented. In this paper, methods of optimization suitable for Sunway TaihuLight are discussed cover the main computations of LOBPCG. Two-level parallel architecture is proposed and followed by the introduction of a communication-avoiding parallel algorithm of sparse matrix-vector product. The algorithm not only overlaps computation and MPI communication but also overlaps data transfer between main memory and the scratch memory on the core group. A data buffering strategy with automatic adjustment during the runtime is proposed. Then, a new implementation of dense matrix multiplication adapted to the Sunway architecture is proposed. The scalability results demonstrate our routines led to significant promotions. We also analyze the performance on the Hamilton matrix from the Density Matrix Renormalization Group (DMRG) method, which is widely used by the computational physicist. © 2019 IEEE.

关键词： Data transfer

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A system for Evaluating the Robustness of Embedded Intelligent Chips and Models

A system for Evaluating the Robustness of Embedded Intellige...

引用

IEEE international Conference on Software Quality, Reliability and Security Companion (QRS-C)

作者： Chenguang Wang Zhixiao Sun Qing Luo Xinyu Wang Tao Zhang QianRu Wei Jing Cheng Depeng Gao Design And Research Institute AVIC Shenyang Aircraft Shenyang City Liaoning Province China School of Software Northwestern Polytechnical University Xian City Shanxi Province China School of Computer Science and Engineering Xi'an Technological University Xian City Shanxi Province China

ISBN: (纸本)9781665478373

After years of research and development, artificial intelligence has become an indispensable strategic technology in the future international competition. With the progress of artificial intelligence algorithms, more and more deep learning models need to be deployed to embedded devices. However, the existing deep learning algorithms have high requirements for hardware computing power, and the performance of some intelligent chips is insufficient, which is bound to affect the performance of the algorithm. Therefore, according to the relevant characteristics of embedded system, this paper designs a set of artificial intelligence chip robustness evaluation system, and builds a task environment for a series of test algorithms. By counting the performance of the same group of algorithms on different chips, we can comprehensively evaluate the robustness of artificial intelligence chip. After testing several mainstream domestic AI chips, the effectiveness of the test method and the differences between chips are verified.

关键词： Deep learning performance evaluation Computational modeling Software quality Robustness Hardware Software reliability

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Dynamically reconfigurable architecture for high-throughput hash function in key-value store 21

Dynamically reconfigurable architecture for high-throughput ...

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作者： Liu, Ke Zhao, Mengying Ju, Lei Jia, Zhiping School of Computer Science and Technology Shandong University China School of Software Shandong University China

ISBN: (纸本)9781728120584

Distributed in-memory key-value stores (KVSs), such as Redis and Memcached, are widely deployed in modern data centers. In Redis, the throughput of Murmurhash2 is important to the performance of the whole KVS, and further affects the whole server. In this paper, we propose a high-performance scalable architecture for Murmurhash2 to improve data locality and reduce the latency, and deploy partial reconfiguration scheme to maximize the ratio of performance/area. Experiment results on Xilinx SOC platform demonstrate that the proposed architecture can improve the throughput by approximate 1.4x and achieve up to 5.3x performance/watt gain compared with the typical Intel platform. © 2019 IEEE.

关键词： Hash functions

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Characterizations and architectural implications of NVM's external DRAM cache 21

Characterizations and architectural implications of NVM's ex...

引用

作者： Pan, Haiyang Liu, Yuhang Lu, Tianyue Chen, Mingyu University of Chinese Academy of Sciences Beijing China State Key Laboratory of Computer Architecture Institute of Computing Technology CAS Beijing China Peng Cheng Laboratory Shenzhen China

ISBN: (纸本)9781728120584

To meet the memory capacity requirement of big-data applications, a promising architecture is that NVM (Non-Volatile Memory) is used as main memory and external DRAM (off-chip) is used as cache. Compared to LLC versus DRAM (referred to as L-DRAM), external DRAM cache versus NVM main memory (referred to as E-NVM) are significantly different in terms of capacity and latency, thus traditional design cannot be directly borrowed without reconsideration. In this paper, we explore the characteristics and architectural implications of E-NVM in diverse dimensions including cache line granularity, associativity, replacement policy and prefetching methods. Lots of hints have been found for the optimal design of this emerging architecture. © 2019 IEEE.

关键词： Dynamic random access storage

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A reconfigurable address translation cache for interconnect network of high performance computer 21

A reconfigurable address translation cache for interconnect ...

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作者： Zhang, Jianmin Li, Tiejun Xiao, Liquan School of Computer National University of Defense Technology Changsha China

ISBN: (纸本)9781728120584

Most of users are accustomed to utilize the virtual address in their parallel programs running at the scalable high performance parallel computer systems. Therefore the virtual and physical address translation mechanism is necessary and crucial to bridge the hardware interface and software application. In this paper, a new reconfigurable address translation Cache (RATC) is proposed. The RATC employs the large capacity eDRAM (embedded Dynamic Random Access Memory) memory to meet the high hit ratio requirement. The capacity of RATC also can be configured four different sizes to reduce power dissipation. Many tests have been conducted on the real chip which implements the address translation architecture. The results show that the RATC has higher hit ratio than the three typical SRAM-based Cache designs, while running the well-known benchmarks. © 2019 IEEE.

关键词： Virtual addresses

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Towards a Transprecision Polymorphic Floating-Point Unit for Mixed-precision computing 31

Towards a Transprecision Polymorphic Floating-Point Unit for...

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31st international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Linhares, Alisson Azevedo, Rodolfo Univ Campinas Unicamp Inst Comp Campinas Brazil

ISBN: (纸本)9781728141947

Mixed-precision is a paradigm that tries to combine computations with different levels of precision to compose results. This approach has been used extensively to optimize scientific applications and has shown speed and energy gains, without causing any relevant precision loss. However, to exploit mixed precision opportunities most applications need to be recompiled to use different instructions and types. Thus, in this work, we present a new floating-point unit design, able to automatically decide when an instruction should be executed using less precision, without recompilation or user direct intervention. Our proposal takes advantage of ad-hoc polymorphism to perform computations with different data types, dynamically selecting a proper instruction on demand, and can also be configured according to overall precision requirements. Our simulated results show that, for some doubleprecision benchmarks, we are able to execute more than 90% of all floating-point operations in half-precision, without affecting its accuracy and resulting in a precision error below 1%. In addition, this new technology may increase instruction level parallelism and cut down the necessity for type casting operations.

关键词： Transprecision Mixed-Precision Floating-Point Unit RISC-V

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A Serious Game for Introducing Software Engineering Ethics to University students 21st

A Serious Game for Introducing Software Engineering Ethics t...

引用

21st international Conference on Interactive Collaborative Learning (ICL) / 47th IGIP international Conference on Engineering Pedagogy - Teaching and Learning in a Digital World

作者： Xenos, Michalis Velli, Vasiliki Univ Patras Comp Engn & Informat Dept Patras Greece

ISBN: (纸本)9783030119324;9783030119317

This paper presents a game based on storytelling, in which the players are faced with ethical dilemmas related to software engineering specific issues. The players' choices have consequences on how the story unfolds and could lead to various alternative endings. This Ethics Game was used as a tool to mediate the learning activity and it was evaluated by 144 students during a Software Engineering Course on the 2017-2018 academic year. This evaluation was based on a within-subject pre-post design methodology and provided insights on the students learning gain (academic performance), as well as on the students' perceived educational experience. In addition, it provided the results of the students' usability evaluation of the Ethics Game. The results indicated that the students did improve their knowledge about software engineering ethics by playing this game. Also, they considered this game to be a useful educational tool and of high usability. Female students had statistically significant higher knowledge gain and higher evaluation scores than male students, while no statistically significant differences were measured in groups based on the year of study.

关键词： Game-based learning computer engineering ethics Usability evaluation

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Automatic Selection of Sparse Triangular Linear System Solvers on GPUs through Machine Learning Techniques 31

Automatic Selection of Sparse Triangular Linear System Solve...

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31st international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Dufrechou, Ernesto Ezzatti, Pablo Quintana-Orti, Enrique S. Univ Republica Inst Comp Montevideo Uruguay Univ Politecn Valencia Dept Sistemas Informat Sistemas & Comp Valencia Spain

ISBN: (纸本)9781728141947

The solution of sparse triangular linear systems is often the most time-consuming stage of preconditioned iterative methods to solve general sparse linear systems, where it has to be applied several times for the same sparse matrix. For this reason, its computational performance has a strong impact on a wide range of scientific and engineering applications, which has motivated the study of its efficient execution on massively parallel platforms. In this sense, several methods have been proposed to tackle this operation on graphics processing units (GPUs), which can be classified under either the level-set or the self-scheduling paradigms. The results obtained from the experimental evaluation of the different methods suggest that both paradigms perform well for certain problems but poorly for others. Additionally, the relation between the properties of the linear systems and the performance of the different solvers is not evident a-priori. In this context, techniques that allow to predict inexpensively which is be the best solver for a particular linear system can lead to important runtime reductions. Our approach leverages machine learning techniques to select the best sparse triangular solver for a given linear system, with focus on the case where a small number of triangular systems has to be solved for the same matrix. We study the performance of several methods using different features derived from the sparse matrices, obtaining models with more than 80% of accuracy and acceptable prediction speed. These results are an important advance towards the automatic selection of the best GPU solver for a given sparse triangular linear system, and the characterization of the performance of these kernels.

关键词： graphics processors sparse triangular linear systems high performance machine learning

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AgEBO-Tabular: Joint Neural architecture and Hyperparameter Search with Autotuned Data-Parallel Training for Tabular Data

AgEBO-Tabular: Joint Neural Architecture and Hyperparameter ...

引用

Supercomputing Conference

作者： Romain Égelé Prasanna Balaprakash Isabelle Guyon Venkatram Vishwanath Fangfang Xia Rick stevens Zhengying Liu École polytechnique Palaiseau France Argonne National Laboratory Lemont Illinois USA CNRS/Inria-LISN U. Paris-Saclay France

ISBN: (数字)9781450384421

ISBN: (纸本)9781665483902

Developing high-performing predictive models for large tabular data sets is a challenging task. Neural architecture search (NAS) is an AutoML approach that generates and evaluates multiple neural networks with different architectures concurrently to automatically discover an high performing model. A key issue in NAS, particularly for large data sets, is the large computation time required to evaluate each generated architecture. While data-parallel training has the potential to address this issue, a straightforward approach can result in significant loss of accuracy. To that end, we develop AgEBO-Tabular, which combines Aging Evolution (AE) to search over neural architectures and asynchronous Bayesian optimization (BO) to search over hyperparameters to adapt data-parallel training. We evaluate the efficacy of our approach on two large predictive modeling tabular data sets from the Exascale computing Project-CANcer Distributed Learning Environment (ECP-CANDLE).

关键词： Training Exascale computing Distance learning Computational modeling Neural networks Distributed databases computer architecture

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Real-Time Human Violent Activity Recognition Using Complex Action Decomposition

Real-Time Human Violent Activity Recognition Using Complex A...

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2020 international computer symposium, ICS 2020

作者： Coming Lopez, Dylan Josh Lien, Cheng-Chang Adamson University Computer Engineering Department Manila Philippines Chung Hua University Department of Computer Science and Information Engineering Hsinchu Taiwan

ISBN: (纸本)9781728192550

There is a scarcity of intelligent security systems in previous researches focusing on violence detection for public spaces. Previous efforts focus only on system accuracy but not their speed or operability. This defeats the purpose of the safety-critical aspect of security systems. With this, we developed a violence recognition framework for surveillance systems using a two-stream neural network architecture for complex action decomposition. As there is no publicly available dataset for static surveillance cameras for violence recognition considering them as complex actions, the proponents organized a multi-view dataset for determining simple violent actions. The main pipeline of the system utilizes state-of-the-art architectures on object detection for extracting spatial features and optical flow estimation for temporal features that are then fused using a boost fusion algorithm to determine simple actions. The simple actions are then further classified as either violent or non-violent actions by logistic regression which completes the complex action recognition. The experimental results show that our proposed framework has an accuracy of 81.2% and a recall of 81.7%. Previous implementations that included their operating speed reaches 25 FPS on shallow neural networks while this research's operating speed reaches 21 FPS on a very deep network. This shows that the performance of the research has competent accuracy and can operate in real-time safety-critical operations. © 2020 IEEE.

关键词： Real time systems

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